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Source: verilog-parser
Section: python
Priority: optional
Maintainer: Debian Electronics Team <pkg-electronics-devel@alioth-lists.debian.net>
Uploaders: Aryan Karamtoth <aryankmmiv@outlook.com>
Rules-Requires-Root: no
Build-Depends:
debhelper-compat (= 13),
dh-sequence-python3,
python3-setuptools,
python3-all,
python3-lark,
pybuild-plugin-pyproject,
Testsuite: autopkgtest-pkg-python
Standards-Version: 4.7.2
Homepage: https://codeberg.org/tok/py-verilog-parser
Vcs-Browser: https://salsa.debian.org/electronics-team/verilog-parser
Vcs-Git: https://salsa.debian.org/electronics-team/verilog-parser.git
Package: python3-verilog-parser
Architecture: all
Depends:
${python3:Depends},
${misc:Depends},
python3-lark,
Description: Parser for Verilog netlists (structural Verilog)
Lark based parser for Verilog netlists (structural Verilog
without behavioral statements).
This is meant to be used to read netlists as
generated by HDL logic synthesizers such as Yosys.
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