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Source: yosys
Maintainer: Debian Electronics Team <pkg-electronics-devel@lists.alioth.debian.org>
Uploaders: Daniel Gröber <dxld@darkboxed.org>
Section: electronics
Priority: optional
Build-Depends: debhelper-compat (= 13),
dh-python,
tcl-dev,
libreadline-dev,
libbz2-dev,
zlib1g-dev,
bison,
flex,
gawk,
git,
libffi-dev,
pkgconf,
txt2man,
iverilog (>= 12),
python3,
python3-setuptools,
libcxxopts-dev,
gtkwave
Build-Depends-Indep:
texlive-base,
texlive-plain-generic,
texlive-fonts-recommended,
texlive-fonts-extra,
texlive-latex-base,
texlive-latex-extra,
texlive-font-utils,
texlive-science,
texlive-publishers,
texlive-bibtex-extra,
tex-gyre,
latexmk,
lmodern,
graphviz,
faketime,
pdf2svg,
python3-sphinx,
python3-sphinx-press-theme,
python3-sphinxcontrib.bibtex,
python3-click,
Rules-Requires-Root: no
Standards-Version: 4.7.2
Vcs-Browser: https://salsa.debian.org/electronics-team/yosys
Vcs-Git: https://salsa.debian.org/electronics-team/yosys.git
Homepage: https://github.com/YosysHQ/yosys
Package: yosys
Architecture: any
Depends: ${shlibs:Depends},
${python3:Depends},
python3-click,
${misc:Depends},
yosys-abc (>= 0.32-1),
Recommends: xdot
Description: Framework for Verilog RTL synthesis
This is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
Package: yosys-dev
Architecture: any
Depends: ${shlibs:Depends},
${python3:Depends},
${misc:Depends},
tcl-dev,
libffi-dev,
libreadline-dev
Description: Framework for Verilog RTL synthesis (development files)
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
.
This package contains the headers and programs needed to build yosys plugins.
Package: yosys-abc
Architecture: any
Depends: ${shlibs:Depends},
${misc:Depends},
Replaces: yosys (<< 0.32-1)
Breaks: yosys (<< 0.32-1)
Description: Sequential Logic Synthesis and Verification Algorithms
ABC is a system for synthesis and verification of binary sequential logic
circuits appearing in synchronous hardware designs. It combines scalable
logic optimization based on And-Inverter Graphs (AIGs), optimal-delay
DAG-based technology mapping for look-up tables and standard cells, and
innovative algorithms for sequential synthesis and verification.
.
This is a fork of berkeley-abc maintained by the YosysHQ team for use in
the yosys RTL synthesis framework.
Package: yosys-doc
Section: doc
Architecture: all
Depends: ${misc:Depends}
Multi-Arch: foreign
Suggests: yosys
Description: Framework for Verilog RTL synthesis (documentation)
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
.
This package contains the manual.
|
