Description: Escape a hyphen
Bug: https://sourceforge.net/p/covered/patches/1/
Forwarded: https://sourceforge.net/p/covered/patches/_discuss/thread/70633c81/c8e0/attachment/manpage.diff
Author: أحمد المحمودي (Ahmed El-Mahmoudy) <aelmahmoudy@users.sourceforge.net>
--- a/doc/covered.1
+++ b/doc/covered.1
@@ -349,7 +349,7 @@
 .TP
 If you are compiling a NC-Verilog simulation, switch to NC-Verilog's irun command to load the covered shared object: '\-loadvpi /usr/local/libexec/covered.ncv.so:covered_register' and enable all access with '\-access +rwc'. You can hardcode the $covered_sim call into your RTL or you can run it dynamically using the CLI, by adding the \-input input.tcl switch to irun.  Where the input.tcl file looks like the following and tb.dut is the coverage instance:
 .br
-call -systf {$covered_sim} {"scored.cdd"} tb.dut
+call \-systf {$covered_sim} {"scored.cdd"} tb.dut
 .br
 run
 .TP