From 3a80463648e0bf67391cf72bf418bd12b8b0eb30 Mon Sep 17 00:00:00 2001 From: "Shelegov, Maksim" Date: Thu, 10 Nov 2022 22:11:09 +0000 Subject: [PATCH] Add multi indirect byte regioning feature Define the subtarget feature correctly --- IGC/VectorCompiler/lib/GenXCodeGen/GenX.td | 19 +++++++++++++++++++ .../lib/GenXCodeGen/GenXSubtarget.h | 9 +++++++-- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td b/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td index e011a673d..3633657fa 100644 --- a/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td +++ b/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td @@ -160,6 +160,10 @@ def WarnCallable : SubtargetFeature<"warn_callable", "WarnCallable", def OCLRuntime : SubtargetFeature<"ocl_runtime", "OCLRuntime", "true", "Prepare structures for OCL runtime">; +def FeatureMultiIndirectByteRegioning : SubtargetFeature<"multi_indirect_byte_regioning", + "HasMultiIndirectByteRegioning", + "true", + "Vx1 and VxH indirect addressing for Byte datatypes">; //===----------------------------------------------------------------------===// // GenX processors supported. @@ -175,6 +179,7 @@ def : Proc<"BDW", [FeatureLongLong, FeatureSwitchjmp, FeatureFP64, FeatureIEEEDivSqrt, FeatureHasPackedFloat, + FeatureMultiIndirectByteRegioning, FeatureHWTIDFromPredef]>; def : Proc<"SKL", [FeatureLongLong, FeatureSwitchjmp, FeatureIntDivRem32, @@ -184,6 +189,7 @@ def : Proc<"SKL", [FeatureLongLong, FeatureSwitchjmp, FeatureIEEEDivSqrt, FeatureHasPackedFloat, FeatureHWTIDFromPredef, + FeatureMultiIndirectByteRegioning, FeaturePreemption]>; def : Proc<"BXT", [FeatureLongLong, FeatureSwitchjmp, FeatureIntDivRem32, @@ -192,6 +198,7 @@ def : Proc<"BXT", [FeatureLongLong, FeatureSwitchjmp, FeatureFP64, FeatureHasPackedFloat, FeatureHWTIDFromPredef, + FeatureMultiIndirectByteRegioning, FeaturePreemption]>; def : Proc<"KBL", [FeatureLongLong, FeatureSwitchjmp, FeatureIntDivRem32, @@ -201,6 +208,7 @@ def : Proc<"KBL", [FeatureLongLong, FeatureSwitchjmp, FeatureIEEEDivSqrt, FeatureHasPackedFloat, FeatureHWTIDFromPredef, + FeatureMultiIndirectByteRegioning, FeaturePreemption]>; def : Proc<"GLK", [FeatureLongLong, FeatureSwitchjmp, FeatureIntDivRem32, @@ -209,27 +217,32 @@ def : Proc<"GLK", [FeatureLongLong, FeatureSwitchjmp, FeatureFP64, FeatureHasPackedFloat, FeatureHWTIDFromPredef, + FeatureMultiIndirectByteRegioning, FeaturePreemption]>; def : Proc<"ICLLP", [FeatureLongLongEmulation, FeatureSwitchjmp, FeatureIntDivRem32, FeatureInstrBitRotate, FeatureIEEEDivSqrt, FeatureHWTIDFromPredef, FeatureHasPackedFloat, + FeatureMultiIndirectByteRegioning, FeaturePreemption]>; def : Proc<"TGLLP", [FeatureLongLongEmulation, FeatureIntDivRem32, FeatureInstrBitRotate, FeatureWAFusedEUNoMask, FeatureHWTIDFromPredef, FeatureHasPackedFloat, + FeatureMultiIndirectByteRegioning, FeaturePreemption, FeatureFusedEU]>; def : Proc<"RKL", [FeatureLongLongEmulation, FeatureIntDivRem32, FeatureInstrBitRotate, FeatureWAFusedEUNoMask, FeatureHWTIDFromPredef, FeatureHasPackedFloat, + FeatureMultiIndirectByteRegioning, FeaturePreemption, FeatureFusedEU]>; def : Proc<"DG1", [FeatureLongLongEmulation, FeatureIntDivRem32, FeatureInstrBitRotate, FeatureWAFusedEUNoMask, FeatureHWTIDFromPredef, FeatureHasPackedFloat, + FeatureMultiIndirectByteRegioning, FeaturePreemption, FeatureFusedEU]>; def : Proc<"XEHP", [FeatureLongLong, FeatureInstrAdd64, @@ -237,26 +250,31 @@ def : Proc<"XEHP", [FeatureLongLong, FeatureIEEEDivSqrt, FeatureThreadPayloadInMemory, FeatureHasPackedFloat, + FeatureMultiIndirectByteRegioning, FeatureInstrBitRotate, FeatureFusedEU]>; def : Proc<"ADLS", [FeatureLongLongEmulation, FeatureIntDivRem32, FeatureInstrBitRotate, FeatureWAFusedEUNoMask, FeatureHasPackedFloat, FeatureHWTIDFromPredef, + FeatureMultiIndirectByteRegioning, FeaturePreemption, FeatureFusedEU]>; def : Proc<"ADLP", [FeatureLongLongEmulation, FeatureIntDivRem32, FeatureInstrBitRotate, FeatureWAFusedEUNoMask, FeatureHasPackedFloat, FeatureHWTIDFromPredef, + FeatureMultiIndirectByteRegioning, FeaturePreemption, FeatureFusedEU]>; def : Proc<"ADLN", [FeatureLongLongEmulation, FeatureIntDivRem32, FeatureInstrBitRotate, FeatureWAFusedEUNoMask, FeatureHasPackedFloat, FeatureHWTIDFromPredef, + FeatureMultiIndirectByteRegioning, FeaturePreemption, FeatureFusedEU]>; def : Proc<"DG2", [FeatureLongLongEmulation, FeatureThreadPayloadInMemory, FeatureHasPackedFloat, FeatureInstrBitRotate, + FeatureMultiIndirectByteRegioning, FeatureHasLSC, FeatureFusedEU]>; def : Proc<"PVC", [FeatureLongLong, FeatureGRFByteSize64, FeatureLSCMaxWidth32, @@ -298,6 +316,7 @@ def : Proc<"MTL", [FeatureLongLongEmulation, FeatureThreadPayloadInMemory, FeatureInstrBitRotate, FeatureBfMixedModeWidth16, + FeatureMultiIndirectByteRegioning, FeatureHasLSC, FeatureFusedEU]>; def GenX : Target { diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.h b/IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.h index 802b9b006..121b4d0a5 100644 --- a/IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.h +++ b/IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.h @@ -179,6 +179,9 @@ private: // Has L3 flush on GPU-scope invalidate. bool HasL3FlushOnGPUScopeInvalidate = false; + // True if Vx1 and VxH indirect addressing are allowed for Byte datatypes + bool HasMultiIndirectByteRegioning = false; + // Shows which surface should we use for stack PreDefined_Surface StackSurf; @@ -375,9 +378,11 @@ public: return hasIndirectGRFCrossing() && !isPVC(); } - /// * hasMultiIndirectByteRegioning - true if target supports an mutli + /// * hasMultiIndirectByteRegioning - true if target supports an multi /// indirect regions with byte type - bool hasMultiIndirectByteRegioning() const { return !isPVC(); } + bool hasMultiIndirectByteRegioning() const { + return HasMultiIndirectByteRegioning; + }; bool hasNBarrier() const { return GenXVariant >= XE_PVC; } -- 2.20.1