Author: Andreas Beckmann Description: fix typos found by Lintian --- a/lib/events/intel_bdw_events.h +++ b/lib/events/intel_bdw_events.h @@ -2248,7 +2248,7 @@ static const intel_x86_umask_t bdw_ept[] static const intel_x86_umask_t bdw_arith[]={ { .uname = "FPU_DIV_ACTIVE", - .udesc = "Cycles when divider is busy execuing divide operations", + .udesc = "Cycles when divider is busy executing divide operations", .ucode = 0x0100, .uflags= INTEL_X86_DFL, }, --- a/lib/events/power8_events.h +++ b/lib/events/power8_events.h @@ -1691,8 +1691,8 @@ static const pme_power_entry_t power8_pe [ POWER8_PME_PM_DATA_ALL_FROM_L2MISS_MOD ] = { .pme_name = "PM_DATA_ALL_FROM_L2MISS_MOD", .pme_code = 0x61c04e, - .pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either demand loads or data prefetch", - .pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", + .pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L2 due to either demand loads or data prefetch", + .pme_long_desc = "The processor's data cache was reloaded from a location other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_DATA_ALL_FROM_L2_DISP_CONFLICT_LDHITST", @@ -1751,8 +1751,8 @@ static const pme_power_entry_t power8_pe [ POWER8_PME_PM_DATA_ALL_FROM_L3MISS_MOD ] = { .pme_name = "PM_DATA_ALL_FROM_L3MISS_MOD", .pme_code = 0x64c04e, - .pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either demand loads or data prefetch", - .pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", + .pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to either demand loads or data prefetch", + .pme_long_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", }, [ POWER8_PME_PM_DATA_ALL_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_DATA_ALL_FROM_L3_DISP_CONFLICT", @@ -1931,8 +1931,8 @@ static const pme_power_entry_t power8_pe [ POWER8_PME_PM_DATA_FROM_L2MISS_MOD ] = { .pme_name = "PM_DATA_FROM_L2MISS_MOD", .pme_code = 0x1c04e, - .pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to a demand load", - .pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", + .pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load", + .pme_long_desc = "The processor's data cache was reloaded from a location other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST", @@ -1997,8 +1997,8 @@ static const pme_power_entry_t power8_pe [ POWER8_PME_PM_DATA_FROM_L3MISS_MOD ] = { .pme_name = "PM_DATA_FROM_L3MISS_MOD", .pme_code = 0x4c04e, - .pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load", - .pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", + .pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a demand load", + .pme_long_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", }, [ POWER8_PME_PM_DATA_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_DATA_FROM_L3_DISP_CONFLICT", @@ -2327,8 +2327,8 @@ static const pme_power_entry_t power8_pe [ POWER8_PME_PM_DPTEG_FROM_L2MISS ] = { .pme_name = "PM_DPTEG_FROM_L2MISS", .pme_code = 0x1e04e, - .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request", - .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request.", + .pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a data side request", + .pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST", @@ -2387,8 +2387,8 @@ static const pme_power_entry_t power8_pe [ POWER8_PME_PM_DPTEG_FROM_L3MISS ] = { .pme_name = "PM_DPTEG_FROM_L3MISS", .pme_code = 0x4e04e, - .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request", - .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request.", + .pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request", + .pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request.", }, [ POWER8_PME_PM_DPTEG_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_DPTEG_FROM_L3_DISP_CONFLICT", @@ -3083,8 +3083,8 @@ static const pme_power_entry_t power8_pe [ POWER8_PME_PM_INST_ALL_FROM_L2MISS ] = { .pme_name = "PM_INST_ALL_FROM_L2MISS", .pme_code = 0x51404e, - .pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to instruction fetches and prefetches", - .pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", + .pme_short_desc = "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to instruction fetches and prefetches", + .pme_long_desc = "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_INST_ALL_FROM_L2_DISP_CONFLICT_LDHITST", @@ -3143,8 +3143,8 @@ static const pme_power_entry_t power8_pe [ POWER8_PME_PM_INST_ALL_FROM_L3MISS_MOD ] = { .pme_name = "PM_INST_ALL_FROM_L3MISS_MOD", .pme_code = 0x54404e, - .pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch", - .pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", + .pme_short_desc = "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to a instruction fetch", + .pme_long_desc = "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", }, [ POWER8_PME_PM_INST_ALL_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_INST_ALL_FROM_L3_DISP_CONFLICT", @@ -3335,8 +3335,8 @@ static const pme_power_entry_t power8_pe [ POWER8_PME_PM_INST_FROM_L2MISS ] = { .pme_name = "PM_INST_FROM_L2MISS", .pme_code = 0x1404e, - .pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to an instruction fetch (not prefetch)", - .pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", + .pme_short_desc = "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch)", + .pme_long_desc = "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_INST_FROM_L2_DISP_CONFLICT_LDHITST", @@ -3401,8 +3401,8 @@ static const pme_power_entry_t power8_pe [ POWER8_PME_PM_INST_FROM_L3MISS_MOD ] = { .pme_name = "PM_INST_FROM_L3MISS_MOD", .pme_code = 0x4404e, - .pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch", - .pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", + .pme_short_desc = "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to a instruction fetch", + .pme_long_desc = "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", }, [ POWER8_PME_PM_INST_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_INST_FROM_L3_DISP_CONFLICT", @@ -3593,8 +3593,8 @@ static const pme_power_entry_t power8_pe [ POWER8_PME_PM_IPTEG_FROM_L2MISS ] = { .pme_name = "PM_IPTEG_FROM_L2MISS", .pme_code = 0x1504e, - .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request", - .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request.", + .pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a instruction side request", + .pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_IPTEG_FROM_L2_DISP_CONFLICT_LDHITST", @@ -3653,8 +3653,8 @@ static const pme_power_entry_t power8_pe [ POWER8_PME_PM_IPTEG_FROM_L3MISS ] = { .pme_name = "PM_IPTEG_FROM_L3MISS", .pme_code = 0x4504e, - .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request", - .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request.", + .pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request", + .pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request.", }, [ POWER8_PME_PM_IPTEG_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_IPTEG_FROM_L3_DISP_CONFLICT", @@ -5453,8 +5453,8 @@ static const pme_power_entry_t power8_pe [ POWER8_PME_PM_MRK_DATA_FROM_L2MISS_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2MISS_CYC", .pme_code = 0x4c12e, - .pme_short_desc = "Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load", - .pme_long_desc = "Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load.", + .pme_short_desc = "Duration in cycles to reload from a location other than the local core's L2 due to a marked load", + .pme_long_desc = "Duration in cycles to reload from a location other than the local core's L2 due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L2_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_CYC", @@ -5567,14 +5567,14 @@ static const pme_power_entry_t power8_pe [ POWER8_PME_PM_MRK_DATA_FROM_L3MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L3MISS", .pme_code = 0x201e4, - .pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load", - .pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load.", + .pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load", + .pme_long_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L3MISS_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3MISS_CYC", .pme_code = 0x2d12e, - .pme_short_desc = "Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load", - .pme_long_desc = "Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load.", + .pme_short_desc = "Duration in cycles to reload from a location other than the local core's L3 due to a marked load", + .pme_long_desc = "Duration in cycles to reload from a location other than the local core's L3 due to a marked load.", }, [ POWER8_PME_PM_MRK_DATA_FROM_L3_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3_CYC", @@ -5819,8 +5819,8 @@ static const pme_power_entry_t power8_pe [ POWER8_PME_PM_MRK_DPTEG_FROM_L2MISS ] = { .pme_name = "PM_MRK_DPTEG_FROM_L2MISS", .pme_code = 0x1f14e, - .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request", - .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request.", + .pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request", + .pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST ] = { .pme_name = "PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST", @@ -5879,8 +5879,8 @@ static const pme_power_entry_t power8_pe [ POWER8_PME_PM_MRK_DPTEG_FROM_L3MISS ] = { .pme_name = "PM_MRK_DPTEG_FROM_L3MISS", .pme_code = 0x4f14e, - .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request", - .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request.", + .pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a marked data side request", + .pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a marked data side request.", }, [ POWER8_PME_PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT ] = { .pme_name = "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT", --- a/lib/events/power9_events.h +++ b/lib/events/power9_events.h @@ -3206,7 +3206,7 @@ static const pme_power_entry_t power9_pe .pme_name = "PM_ITLB_MISS", .pme_code = 0x00000400FC, .pme_short_desc = "ITLB Reloaded.", - .pme_long_desc = "ITLB Reloaded. Counts 1 per ITLB miss for HPT but multiple for radix depending on number of levels traveresed", + .pme_long_desc = "ITLB Reloaded. Counts 1 per ITLB miss for HPT but multiple for radix depending on number of levels traversed", }, [ POWER9_PME_PM_L1_DCACHE_RELOADED_ALL ] = { .pme_name = "PM_L1_DCACHE_RELOADED_ALL", --- a/lib/events/arm_neoverse_n2_events.h +++ b/lib/events/arm_neoverse_n2_events.h @@ -702,32 +702,32 @@ static const arm_entry_t arm_n2_pe[]={ {.name = "LDST_ALIGN_LAT", .modmsk = ARMV9_ATTRS, .code = 0x4020, - .desc = "Accesses with additonal latency from aligment", + .desc = "Accesses with additional latency from alignment", }, {.name = "LD_ALIGN_LAT", .modmsk = ARMV9_ATTRS, .code = 0x4021, - .desc = "Loads with additonal latency from aligment", + .desc = "Loads with additional latency from alignment", }, {.name = "ST_ALIGN_LAT", .modmsk = ARMV9_ATTRS, .code = 0x4022, - .desc = "Stores with additonal latency from aligment", + .desc = "Stores with additional latency from alignment", }, {.name = "MEM_ACCESS_CHECKED", .modmsk = ARMV9_ATTRS, .code = 0x4024, - .desc = "Checked data memory acess", + .desc = "Checked data memory access", }, {.name = "MEM_ACCESS_RD_CHECKED", .modmsk = ARMV9_ATTRS, .code = 0x4025, - .desc = "Checked data memory read acess", + .desc = "Checked data memory read access", }, {.name = "MEM_ACCESS_WR_CHECKED", .modmsk = ARMV9_ATTRS, .code = 0x4026, - .desc = "Checked data memory write acess", + .desc = "Checked data memory write access", }, {.name = "ASE_INST_SPEC", .modmsk = ARMV9_ATTRS, --- a/lib/events/power10_events.h +++ b/lib/events/power10_events.h @@ -2748,7 +2748,7 @@ static const pme_power_entry_t power10_p {.pme_name = "PM_ISSUE_KILL", .pme_code = 0x40006, .pme_short_desc = "frontend;Cycles in which an instruction or group of instructions were cancelled after being issued.", - .pme_long_desc = "frontend;Cycles in which an instruction or group of instructions were cancelled after being issued. This event increments once per occurance, regardless of how many instructions are included in the issue group", + .pme_long_desc = "frontend;Cycles in which an instruction or group of instructions were cancelled after being issued. This event increments once per occurrence, regardless of how many instructions are included in the issue group", }, {.pme_name = "PM_ISSUE_STALL", .pme_code = 0x20004, --- a/docs/man3/libpfm_intel_gnr.3 +++ b/docs/man3/libpfm_intel_gnr.3 @@ -81,7 +81,7 @@ library offers the list of validated com .SH Topdown via PERF_METRICS -Intel GraniteRapids supports the PERF_METRICS MSR which provides support for Topdown Level 1 and 2 via a single PMU counter. This special counter provides percentages of slots for each metric. This feature must be used in conjunction with fixed counter 3 which counts SLOTS in order to work properly. The Linux kernel exposes PERF_METRICS metrics as individual pseudo events counting in slots unit however to operate correctly all events must be programmed together. The Linux kernel requires all PERF_METRICS events to be programmed as a single event group with the first event as SLOTS required. Example: '{slots,topdown-retiring,topdown-bad-spec,topdown-fe-bound,topdown-be-bound,topdown-heavy-ops,topdown-br-mispredict,topdown-fetch-lat,topdown-mem-bound}'. Libpfm4 provides acces to the PERF_METRICS pseudo events via a dedicated event called \fBTOPDOWN_M\fR. This event uses the pseudo encodings assigned by the Linux kernel to PERF_METRICS pseudo events. Using these encodings ensures the kernel detects them as targeting the PERF_METRICS MSR. Note that libpfm4 only provides the encodings and that it is up the user on Linux to group them and order them properly for the perf_events interface. There exists generic counter encodings for most of the Topdown metrics and libpfm4 provides support for those via the \fBTOPDOWN\fR event. Note that all subevents of \fBTOPDOWN_M\fR use fixed counters which have, by definition, no actual event codes. The library uses the Linux pseudo event codes for them, even when compiled on non Linux operating systems.The same holds true for any fixed counters pseudo event exported by libpfm4. +Intel GraniteRapids supports the PERF_METRICS MSR which provides support for Topdown Level 1 and 2 via a single PMU counter. This special counter provides percentages of slots for each metric. This feature must be used in conjunction with fixed counter 3 which counts SLOTS in order to work properly. The Linux kernel exposes PERF_METRICS metrics as individual pseudo events counting in slots unit however to operate correctly all events must be programmed together. The Linux kernel requires all PERF_METRICS events to be programmed as a single event group with the first event as SLOTS required. Example: '{slots,topdown-retiring,topdown-bad-spec,topdown-fe-bound,topdown-be-bound,topdown-heavy-ops,topdown-br-mispredict,topdown-fetch-lat,topdown-mem-bound}'. Libpfm4 provides access to the PERF_METRICS pseudo events via a dedicated event called \fBTOPDOWN_M\fR. This event uses the pseudo encodings assigned by the Linux kernel to PERF_METRICS pseudo events. Using these encodings ensures the kernel detects them as targeting the PERF_METRICS MSR. Note that libpfm4 only provides the encodings and that it is up the user on Linux to group them and order them properly for the perf_events interface. There exists generic counter encodings for most of the Topdown metrics and libpfm4 provides support for those via the \fBTOPDOWN\fR event. Note that all subevents of \fBTOPDOWN_M\fR use fixed counters which have, by definition, no actual event codes. The library uses the Linux pseudo event codes for them, even when compiled on non Linux operating systems.The same holds true for any fixed counters pseudo event exported by libpfm4. .SH AUTHORS --- a/docs/man3/libpfm_intel_icl.3 +++ b/docs/man3/libpfm_intel_icl.3 @@ -79,7 +79,7 @@ library offers the list of validated com .SH Topdown via PERF_METRICS -Intel Icelake supports the PERF_METRICS MSR which provides support for Topdown Level 1 via a single PMU counter. This special counter provides percentages of slots for each metric. This feature must be used in conjunction with fixed counter 3 which counts SLOTS in order to work properly. The Linux kernel exposes PERF_METRICS metrics as individual pseudo events counting in slots unit however to operate correctly all events must be programmed together. The Linux kernel requires all PERF_METRICS events to be programmed as a single event group with the first event as SLOTS required. Example: '{slots,topdown-retiring,topdown-bad-spec,topdown-fe-bound,topdown-be-bound,topdown-heavy-ops,topdown-br-mispredict,topdown-fetch-lat,topdown-mem-bound}'. Libpfm4 provides acces to the PERF_METRICS pseudo events via a dedicated event called \fBTOPDOWN_M\fR. This event uses the pseudo encodings assigned by the Linux kernel to PERF_METRICS pseudo events. Using these encodings ensures the kernel detects them as targeting the PERF_METRICS MSR. Note that libpfm4 only provides the encodings and that it is up the user on Linux to group them and order them properly for the perf_events interface. There exists generic counter encodings for most of the Topdown metrics and libpfm4 provides support for those via the \fBTOPDOWN\fR event. Note that all subevents of \fBTOPDOWN_M\fR use fixed counters which have, by definition, no actual event codes. The library uses the Linux pseudo event codes for them, even when compiled on non Linux operating systems.The same holds true for any fixed counters pseudo event exported by libpfm4. +Intel Icelake supports the PERF_METRICS MSR which provides support for Topdown Level 1 via a single PMU counter. This special counter provides percentages of slots for each metric. This feature must be used in conjunction with fixed counter 3 which counts SLOTS in order to work properly. The Linux kernel exposes PERF_METRICS metrics as individual pseudo events counting in slots unit however to operate correctly all events must be programmed together. The Linux kernel requires all PERF_METRICS events to be programmed as a single event group with the first event as SLOTS required. Example: '{slots,topdown-retiring,topdown-bad-spec,topdown-fe-bound,topdown-be-bound,topdown-heavy-ops,topdown-br-mispredict,topdown-fetch-lat,topdown-mem-bound}'. Libpfm4 provides access to the PERF_METRICS pseudo events via a dedicated event called \fBTOPDOWN_M\fR. This event uses the pseudo encodings assigned by the Linux kernel to PERF_METRICS pseudo events. Using these encodings ensures the kernel detects them as targeting the PERF_METRICS MSR. Note that libpfm4 only provides the encodings and that it is up the user on Linux to group them and order them properly for the perf_events interface. There exists generic counter encodings for most of the Topdown metrics and libpfm4 provides support for those via the \fBTOPDOWN\fR event. Note that all subevents of \fBTOPDOWN_M\fR use fixed counters which have, by definition, no actual event codes. The library uses the Linux pseudo event codes for them, even when compiled on non Linux operating systems.The same holds true for any fixed counters pseudo event exported by libpfm4. .SH AUTHORS .nf --- a/docs/man3/libpfm_intel_spr.3 +++ b/docs/man3/libpfm_intel_spr.3 @@ -79,7 +79,7 @@ library offers the list of validated com .SH Topdown via PERF_METRICS -Intel SapphireRapids supports the PERF_METRICS MSR which provides support for Topdown Level 1 and 2 via a single PMU counter. This special counter provides percentages of slots for each metric. This feature must be used in conjunction with fixed counter 3 which counts SLOTS in order to work properly. The Linux kernel exposes PERF_METRICS metrics as individual pseudo events counting in slots unit however to operate correctly all events must be programmed together. The Linux kernel requires all PERF_METRICS events to be programmed as a single event group with the first event as SLOTS required. Example: '{slots,topdown-retiring,topdown-bad-spec,topdown-fe-bound,topdown-be-bound,topdown-heavy-ops,topdown-br-mispredict,topdown-fetch-lat,topdown-mem-bound}'. Libpfm4 provides acces to the PERF_METRICS pseudo events via a dedicated event called \fBTOPDOWN_M\fR. This event uses the pseudo encodings assigned by the Linux kernel to PERF_METRICS pseudo events. Using these encodings ensures the kernel detects them as targeting the PERF_METRICS MSR. Note that libpfm4 only provides the encodings and that it is up the user on Linux to group them and order them properly for the perf_events interface. There exists generic counter encodings for most of the Topdown metrics and libpfm4 provides support for those via the \fBTOPDOWN\fR event. Note that all subevents of \fBTOPDOWN_M\fR use fixed counters which have, by definition, no actual event codes. The library uses the Linux pseudo event codes for them, even when compiled on non Linux operating systems.The same holds true for any fixed counters pseudo event exported by libpfm4. +Intel SapphireRapids supports the PERF_METRICS MSR which provides support for Topdown Level 1 and 2 via a single PMU counter. This special counter provides percentages of slots for each metric. This feature must be used in conjunction with fixed counter 3 which counts SLOTS in order to work properly. The Linux kernel exposes PERF_METRICS metrics as individual pseudo events counting in slots unit however to operate correctly all events must be programmed together. The Linux kernel requires all PERF_METRICS events to be programmed as a single event group with the first event as SLOTS required. Example: '{slots,topdown-retiring,topdown-bad-spec,topdown-fe-bound,topdown-be-bound,topdown-heavy-ops,topdown-br-mispredict,topdown-fetch-lat,topdown-mem-bound}'. Libpfm4 provides access to the PERF_METRICS pseudo events via a dedicated event called \fBTOPDOWN_M\fR. This event uses the pseudo encodings assigned by the Linux kernel to PERF_METRICS pseudo events. Using these encodings ensures the kernel detects them as targeting the PERF_METRICS MSR. Note that libpfm4 only provides the encodings and that it is up the user on Linux to group them and order them properly for the perf_events interface. There exists generic counter encodings for most of the Topdown metrics and libpfm4 provides support for those via the \fBTOPDOWN\fR event. Note that all subevents of \fBTOPDOWN_M\fR use fixed counters which have, by definition, no actual event codes. The library uses the Linux pseudo event codes for them, even when compiled on non Linux operating systems.The same holds true for any fixed counters pseudo event exported by libpfm4. .SH AUTHORS .nf --- a/include/perfmon/pfmlib.h +++ b/include/perfmon/pfmlib.h @@ -834,7 +834,7 @@ typedef enum { PFM_PMU_INTEL_GNR_UNC_IMC8, /* Intel GraniteRapids IMC channel 8 */ PFM_PMU_INTEL_GNR_UNC_IMC9, /* Intel GraniteRapids IMC channel 9 */ PFM_PMU_INTEL_GNR_UNC_IMC10, /* Intel GraniteRapids IMC channel 10 */ - PFM_PMU_INTEL_GNR_UNC_IMC11, /* Intel GraniteRapids IMC channel 10 */ + PFM_PMU_INTEL_GNR_UNC_IMC11, /* Intel GraniteRapids IMC channel 11 */ /* MUST ADD NEW PMU MODELS HERE */ PFM_PMU_MAX /* end marker */ --- a/lib/events/arm_neoverse_n1_events.h +++ b/lib/events/arm_neoverse_n1_events.h @@ -96,14 +96,14 @@ static const arm_entry_t arm_n1_pe[]={ }, {.name = "L1I_CACHE_ACCESS", .modmsk = ARMV8_ATTRS, + .equiv = "L1I_CACHE", .code = 0x14, - .desc = "Level 1 instruction cache accesses" + .desc = "Level 1 instruction cache accesses (deprecated)" }, {.name = "L1I_CACHE", - .modmsk = ARMV9_ATTRS, - .equiv = "L1I_CACHE", + .modmsk = ARMV8_ATTRS, .code = 0x14, - .desc = "Level 1 instruction cache accesses (deprecated)" + .desc = "Level 1 instruction cache accesses" }, {.name = "L1D_CACHE_WB", .modmsk = ARMV8_ATTRS, --- a/lib/events/arm_neoverse_v1_events.h +++ b/lib/events/arm_neoverse_v1_events.h @@ -109,7 +109,7 @@ static const arm_entry_t arm_v1_pe[]={ .desc = "Level 1 instruction cache accesses (deprecated)" }, {.name = "L1I_CACHE", - .modmsk = ARMV9_ATTRS, + .modmsk = ARMV8_ATTRS, .code = 0x14, .desc = "Level 1 instruction cache accesses" },