From 2b3a8be3bb771d7fd924dffc6b176cd23297c7d8 Mon Sep 17 00:00:00 2001 From: Christian Taedcke Date: Thu, 4 Feb 2016 23:01:57 +0100 Subject: [PATCH 1/8] Convert regression tests to python 3. --- regress/modules/base_test.py | 26 +++++------ regress/modules/gdb_rsp.py | 56 ++++++++++++------------ regress/regress.py.in | 52 +++++++++++----------- regress/test_opcodes/test_ADC.py | 6 +-- regress/test_opcodes/test_ADD.py | 6 +-- regress/test_opcodes/test_ADIW.py | 8 ++-- regress/test_opcodes/test_AND.py | 6 +-- regress/test_opcodes/test_ANDI.py | 6 +-- regress/test_opcodes/test_ASR.py | 6 +-- regress/test_opcodes/test_BCLR.py | 6 +-- regress/test_opcodes/test_BLD.py | 6 +-- regress/test_opcodes/test_BRBC.py | 6 +-- regress/test_opcodes/test_BRBS.py | 6 +-- regress/test_opcodes/test_BSET.py | 6 +-- regress/test_opcodes/test_BST.py | 6 +-- regress/test_opcodes/test_CALL.py | 6 +-- regress/test_opcodes/test_COM.py | 6 +-- regress/test_opcodes/test_CP.py | 6 +-- regress/test_opcodes/test_CPC.py | 6 +-- regress/test_opcodes/test_CPI.py | 6 +-- regress/test_opcodes/test_CPSE.py | 6 +-- regress/test_opcodes/test_DEC.py | 6 +-- regress/test_opcodes/test_EICALL.py | 18 ++++---- regress/test_opcodes/test_EIJMP.py | 12 ++--- regress/test_opcodes/test_ELPM.py | 16 +++---- regress/test_opcodes/test_ELPM_Z.py | 6 +-- regress/test_opcodes/test_ELPM_Z_incr.py | 16 +++---- regress/test_opcodes/test_EOR.py | 6 +-- regress/test_opcodes/test_ICALL.py | 6 +-- regress/test_opcodes/test_IJMP.py | 6 +-- regress/test_opcodes/test_INC.py | 6 +-- regress/test_opcodes/test_JMP.py | 6 +-- regress/test_opcodes/test_LDD_Y.py | 6 +-- regress/test_opcodes/test_LDD_Z.py | 6 +-- regress/test_opcodes/test_LDI.py | 6 +-- regress/test_opcodes/test_LDS.py | 6 +-- regress/test_opcodes/test_LD_X.py | 6 +-- regress/test_opcodes/test_LD_X_decr.py | 8 ++-- regress/test_opcodes/test_LD_X_incr.py | 8 ++-- regress/test_opcodes/test_LD_Y_decr.py | 8 ++-- regress/test_opcodes/test_LD_Y_incr.py | 8 ++-- regress/test_opcodes/test_LD_Z_decr.py | 6 +-- regress/test_opcodes/test_LD_Z_incr.py | 6 +-- regress/test_opcodes/test_LPM.py | 6 +-- regress/test_opcodes/test_LPM_Z.py | 6 +-- regress/test_opcodes/test_LPM_Z_incr.py | 6 +-- regress/test_opcodes/test_LSR.py | 6 +-- regress/test_opcodes/test_MOV.py | 6 +-- regress/test_opcodes/test_MOVW.py | 8 ++-- regress/test_opcodes/test_MUL.py | 6 +-- regress/test_opcodes/test_MULS.py | 6 +-- regress/test_opcodes/test_MULSU.py | 6 +-- regress/test_opcodes/test_NEG.py | 6 +-- regress/test_opcodes/test_NOP.py | 2 +- regress/test_opcodes/test_OR.py | 6 +-- regress/test_opcodes/test_ORI.py | 6 +-- regress/test_opcodes/test_POP.py | 6 +-- regress/test_opcodes/test_PUSH.py | 6 +-- regress/test_opcodes/test_RCALL.py | 6 +-- regress/test_opcodes/test_RET.py | 6 +-- regress/test_opcodes/test_RETI.py | 6 +-- regress/test_opcodes/test_RJMP.py | 6 +-- regress/test_opcodes/test_ROR.py | 6 +-- regress/test_opcodes/test_SBC.py | 8 ++-- regress/test_opcodes/test_SBCI.py | 6 +-- regress/test_opcodes/test_SBIW.py | 8 ++-- regress/test_opcodes/test_SBRC.py | 6 +-- regress/test_opcodes/test_SBRS.py | 6 +-- regress/test_opcodes/test_STD_Y.py | 6 +-- regress/test_opcodes/test_STD_Z.py | 6 +-- regress/test_opcodes/test_STS.py | 6 +-- regress/test_opcodes/test_ST_X.py | 6 +-- regress/test_opcodes/test_ST_X_decr.py | 8 ++-- regress/test_opcodes/test_ST_X_incr.py | 8 ++-- regress/test_opcodes/test_ST_Y_decr.py | 8 ++-- regress/test_opcodes/test_ST_Y_incr.py | 8 ++-- regress/test_opcodes/test_ST_Z_decr.py | 6 +-- regress/test_opcodes/test_ST_Z_incr.py | 6 +-- regress/test_opcodes/test_SUB.py | 6 +-- regress/test_opcodes/test_SUBI.py | 6 +-- regress/test_opcodes/test_SWAP.py | 6 +-- 81 files changed, 330 insertions(+), 330 deletions(-) diff --git a/regress/modules/base_test.py b/regress/modules/base_test.py index 1737a02..099c42e 100644 --- a/regress/modules/base_test.py +++ b/regress/modules/base_test.py @@ -29,13 +29,13 @@ from registers import Reg, Addr """This module provides base classes for regression test cases. """ -class TestFail: +class TestFail(BaseException): def __init__(self, reason): self.reason = reason def __repr__(self): return self.reason -class TestOpcodeNotSupported: +class TestOpcodeNotSupported(BaseException): def __init__(self, reason): self.reason = reason def __repr__(self): @@ -65,7 +65,7 @@ class opcode_test: If the test fails or the target mcu does not support the opcode, an exception will be raised. """ - self.ensure_target_supports_opcode() # check it the target supports the opcode + self.ensure_target_supports_opcode() # check it the target supports the opcode self.common_setup() # setup the test self.target.step() # execute the opcode test self.common_analyze_results() # do the analysis @@ -124,7 +124,7 @@ class opcode_test: expect = self.setup_regs[Reg.PC] + 2 got = self.anal_regs[Reg.PC] if expect != got: - raise TestFail, 'PC not incremented: expect=%x, got=%x' % (expect, got) + raise TestFail('PC not incremented: expect=%x, got=%x' % (expect, got)) # compare all regs except PC and those in reg_changed list for i in range(Reg.PC): @@ -133,7 +133,7 @@ class opcode_test: expect = self.setup_regs[i] got = self.anal_regs[i] if expect != got: - raise TestFail, 'Register %d changed: expect=%x, got=%x' % (i, expect, got) + raise TestFail('Register %d changed: expect=%x, got=%x' % (i, expect, got)) def ensure_target_supports_opcode(self): """Default method to ensure that the target mcu supports the opcode. @@ -155,7 +155,7 @@ class opcode_test: before running the test. The default does nothing thus if preconditions are required, the derived class must override this. """ - raise TestFail, 'Default setup() method used' + raise TestFail('Default setup() method used') def analyze_result(self): """Analyze the results of the execute() method. @@ -167,9 +167,9 @@ class opcode_test: Raise a TestFail exception if a test fails with a reason for failure string as data. """ - raise TestFail, 'Default analyze_results() method used' + raise TestFail('Default analyze_results() method used') - def opcode_not_supported(self): + def opcode_not_supported(self): """Raises the TestOpcodeNotSupported exception. This method should be called by a test if the opcode is not @@ -220,11 +220,11 @@ class opcode_stack_mixin: def setup_word_to_stack(self, val): # used by RET, RETI setup, since they pop at least a word - if (self.target.pc_size == 2): - mem = [(val & 0xff00)>>8, val & 0xff] - else: - mem = [(val & 0xff0000)>>16, (val & 0xff00)>>8, val & 0xff] - self.target.write_sram(self.SP_val+1, len(mem), mem) + if (self.target.pc_size == 2): + mem = [(val & 0xff00)>>8, val & 0xff] + else: + mem = [(val & 0xff0000)>>16, (val & 0xff00)>>8, val & 0xff] + self.target.write_sram(self.SP_val+1, len(mem), mem) def analyze_read_from_current_stack(self): return self.target.read_sram(self.SP_val, 1)[0] diff --git a/regress/modules/gdb_rsp.py b/regress/modules/gdb_rsp.py index 6fa89e5..de94602 100644 --- a/regress/modules/gdb_rsp.py +++ b/regress/modules/gdb_rsp.py @@ -82,37 +82,37 @@ class GdbRemoteSerialProtocol: def out(self, s): if self.ofile: - print >> self.ofile, s + print(s, file=self.ofile) def cksum(self,pkt): sum = 0 for c in pkt: - sum += ord(c) + sum += c return sum & 0xff def ack(self): self.out( 'Send: "+" (Ack)' ) - self.socket.send('+') + self.socket.send(b'+') def send(self, msg): - s = '$'+msg+'#'+'%02x'%(self.cksum(msg)) + s = '$'+msg+'#'+'%02x'%(self.cksum(msg.encode("ascii"))) self.out( 'Sent: "%s"' % (s) ) - self.socket.send(s) + self.socket.send(s.encode("ascii")) reply = self.socket.recv(1) - if reply != '+': - raise ErrReply, reply + if reply != b'+': + raise ErrReply(reply) else: self.out( '-> Ack' ) def recv(self): c = self.socket.recv(1) - if c == '$': + if c == b'$': max_buf = 400 - pkt = '' + pkt = b'' while max_buf: c = self.socket.recv(1) - if c == '#': + if c == b'#': break pkt += c max_buf -= 1 @@ -122,13 +122,13 @@ class GdbRemoteSerialProtocol: cccc += self.socket.recv(1) csum = int( cccc, 16 ) if sum != csum: - raise ErrCheckSum, 'pkt="%s#%s", %02x : %02x' %(pkt,cccc,sum,csum) + raise ErrCheckSum('pkt="%s#%s", %02x : %02x' %(pkt,cccc,sum,csum)) return pkt - elif c == '+': + elif c == b'+': self.out( 'Ack' ) else: - raise ErrPacket, c + raise ErrPacket(c) return None @@ -164,7 +164,7 @@ class GdbRemoteSerialProtocol: arr.fromstring(struct.pack('<33BHL', *regs)) self.send('G'+self.bin2str(arr)) reply = self.recv() - if reply != 'OK': + if reply != b'OK': raise ErrReply self.out( 'Recv: "%s"' % (reply) ) @@ -191,14 +191,14 @@ class GdbRemoteSerialProtocol: self.send('P%x=%s' % (reg, self.bin2str(arr))) reply = self.recv() - if reply != 'OK': + if reply != b'OK': raise ErrReply self.out( 'Recv: "%s"' % (reply) ) def read_mem(self, addr, _len): self.send('m%x,%x' % (addr,_len)) reply = self.recv() - if reply[0] == 'E': + if reply[0] == b'E': raise ErrMemRead self.out( 'Recv: "%s"' % (reply) ) @@ -207,7 +207,7 @@ class GdbRemoteSerialProtocol: def write_mem(self, addr, _len, buf): self.send( 'M%x,%x:' %(addr,_len) + self.bin2str(buf) ) reply = self.recv() - if reply != 'OK': + if reply != b'OK': raise ErrReply self.out( 'Recv: "%s"' % (reply) ) @@ -216,7 +216,7 @@ class GdbRemoteSerialProtocol: """ while 1: reply = self.recv() - if reply[0] != 'O': + if reply[0] != b'O': break return reply @@ -253,18 +253,18 @@ class GdbRemoteSerialProtocol: pkt = 'Z%d,%x,%x' % (_type, addr, _len) self.send( pkt ) reply = self.recv() - if reply == '': + if reply == b'': self.out( 'Z packets are not supported by target.' ) - elif reply != 'OK': + elif reply != b'OK': raise ErrPacket def break_remove(self, _type, addr, _len): pkt = 'z%d,%x,%x' % (_type, addr, _len) self.send( pkt ) reply = self.recv() - if reply == '': + if reply == b'': self.out( 'Z packets are not supported by target.' ) - elif reply != 'OK': + elif reply != b'OK': raise ErrPacket def interrupt(self): @@ -280,21 +280,21 @@ if __name__ == '__main__': regs = rsp.read_regs() regs[10] = 10 rsp.write_regs(regs) - print rsp.read_regs() + print(rsp.read_regs()) - print rsp.read_reg(12) + print(rsp.read_reg(12)) rsp.write_reg(12,0xaa) - print rsp.read_reg(12) - print rsp.read_reg(34) # PC + print(rsp.read_reg(12)) + print(rsp.read_reg(34)) # PC # Try to read/write memory addr = 0x0 _len = 10 mem = rsp.read_mem(addr,_len) - print mem + print(mem) mem[4] = 10 rsp.write_mem(addr,len(mem),mem) - print rsp.read_mem(addr,_len) + print(rsp.read_mem(addr,_len)) # Write zero's (NOP's) to first 60 bytes of flash arr = array.array('B', [ 0x0 for i in range(60) ]) diff --git a/regress/regress.py.in b/regress/regress.py.in index abdf5f3..f0b42cb 100644 --- a/regress/regress.py.in +++ b/regress/regress.py.in @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -106,7 +106,7 @@ def run_tests(target, tdir=None, tmodule=None, tname=None): tmodule += '.py' test_modules = [tmodule] - print '='*8 + ' running tests in %s directory' % (test_dir) + print('='*8 + ' running tests in %s directory' % (test_dir)) # add tests dir to module search patch sys.path.append(test_dir) @@ -118,7 +118,7 @@ def run_tests(target, tdir=None, tmodule=None, tname=None): # get test module name by stripping off .py from file name test_module_name = file[:-3] - print '-'*4 + ' loading tests from %s module' %(test_module_name) + print('-'*4 + ' loading tests from %s module' %(test_module_name)) test_module = __import__(test_module_name) if tname is None: @@ -136,20 +136,20 @@ def run_tests(target, tdir=None, tmodule=None, tname=None): try: # Create an instance of the test case object and run it - test = apply( getattr(test_module,test_name), (target,) ) - print '%-30s -> ' %(test_name), + test = getattr(test_module,test_name)(*(target,)) + print('%-30s -> ' %(test_name), end=' ') test.run() - except base_test.TestFail, reason: - print 'FAILED: %s' %(reason) + except base_test.TestFail as reason: + print('FAILED: %s' %(reason)) num_fails += 1 # Could also do a sys.exit(1) here is user wishes result = EXIT_STATUS_FAIL - except base_test.TestOpcodeNotSupported, reason: - print reason + except base_test.TestOpcodeNotSupported as reason: + print(reason) num_not_supported += 1 else: num_passes += 1 - print 'passed' + print('passed') num_tests += 1 @@ -164,18 +164,18 @@ def run_tests(target, tdir=None, tmodule=None, tname=None): elapsed = sum(os.times()[:2]) - start_time - print - print 'Ran %d tests in %.3f seconds [%0.3f tests/second].' % \ - (num_tests, elapsed, num_tests/elapsed) - print ' Number of Passing Tests: %d' %(num_passes) - print ' Number of Failing Tests: %d' %(num_fails) - print ' Number of Skipped Tests: %d (opcode not supported by target)' %(num_not_supported) - print + print() + print('Ran %d tests in %.3f seconds [%0.3f tests/second].' % \ + (num_tests, elapsed, num_tests/elapsed)) + print(' Number of Passing Tests: %d' %(num_passes)) + print(' Number of Failing Tests: %d' %(num_fails)) + print(' Number of Skipped Tests: %d (opcode not supported by target)' %(num_not_supported)) + print() return result def usage(): - print >> sys.stderr, """ + print(""" Usage: regress.py [options] [[test_]dir] [[test_]module[.py]] [[test_]case] The 'test_' prefix on all args is optional. The '.py' extension on the test_module arg is also optional. @@ -186,7 +186,7 @@ Options: "atmega128" -s, --sim= : path to simulavr executable --stall : stall the regression engine when done -""" +""", file=sys.stderr) sys.exit(1) def run_simulator(prog, dev, port=1212): @@ -195,11 +195,11 @@ def run_simulator(prog, dev, port=1212): # Check if prog file exists if not os.path.isfile(prog): - print >> sys.stderr, '%s does not exist' %(prog) + print('%s does not exist' %(prog), file=sys.stderr) sys.exit(1) - out = os.open(regressdir+'/sim.out', os.O_WRONLY | os.O_CREAT | os.O_TRUNC, 0644) - err = os.open(regressdir+'/sim.err', os.O_WRONLY | os.O_CREAT | os.O_TRUNC, 0644) + out = os.open(regressdir+'/sim.out', os.O_WRONLY | os.O_CREAT | os.O_TRUNC, 0o644) + err = os.open(regressdir+'/sim.err', os.O_WRONLY | os.O_CREAT | os.O_TRUNC, 0o644) p = subprocess.Popen((prog, '-g', '-G', '-d', dev, '-p', str(port)), shell = False, stdout = out, @@ -241,24 +241,24 @@ if __name__ == '__main__': try: target = avr_target.AvrTarget(device) except socket.error: - print >> sys.stderr, 'Simulator not responding, wait a second and try again' + print('Simulator not responding, wait a second and try again', file=sys.stderr) tries -= 1 time.sleep(1) else: break if tries == 0: - print >> sys.stderr, 'Fatal error: simulator did not start' + print('Fatal error: simulator did not start', file=sys.stderr) sys.exit(1) # run the tests try: - status = apply(run_tests, [target]+args) + status = run_tests(*[target]+args) finally: # We always want to shut down the simulator target.close() if stall: - raw_input('hit enter to quit...') + input('hit enter to quit...') # make sure that the simulator has quit sim_p.wait() diff --git a/regress/test_opcodes/test_ADC.py b/regress/test_opcodes/test_ADC.py index 441120b..6f995a7 100644 --- a/regress/test_opcodes/test_ADC.py +++ b/regress/test_opcodes/test_ADC.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -96,7 +96,7 @@ class test_ADC_rd%02d_vd%02x_rr%02d_vr%02x_C%d(base_ADC): Vr = 0x%x C = %d def fail(self,s): - raise ADC_rd%02d_vd%02x_rr%02d_vr%02x_C%d_TestFail, s + raise ADC_rd%02d_vd%02x_rr%02d_vr%02x_C%d_TestFail(s) """ # @@ -132,4 +132,4 @@ for c in (0,1): for vd,vr in vals: args = (d,vd,d,vd,c)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_ADD.py b/regress/test_opcodes/test_ADD.py index c9612bf..67da3ea 100644 --- a/regress/test_opcodes/test_ADD.py +++ b/regress/test_opcodes/test_ADD.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -96,7 +96,7 @@ class test_ADD_rd%02d_vd%02x_rr%02d_vr%02x_C%d(base_ADD): Vr = 0x%x C = %d def fail(self,s): - raise ADD_rd%02d_vd%02x_rr%02d_vr%02x_C%d_TestFail, s + raise ADD_rd%02d_vd%02x_rr%02d_vr%02x_C%d_TestFail(s) """ # @@ -132,4 +132,4 @@ for c in (0,1): for vd,vr in vals: args = (d,vd,d,vd,c)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_ADIW.py b/regress/test_opcodes/test_ADIW.py index 26940ac..dd4a4e9 100644 --- a/regress/test_opcodes/test_ADIW.py +++ b/regress/test_opcodes/test_ADIW.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -48,7 +48,7 @@ class base_ADIW(base_test.opcode_test): self.setup_regs[self.Rd+1] = (self.vd >> 8) # Return the raw opcode - return 0x9600 | (((self.Rd/2)-12) << 4) | ((self.vk & 0x30) << 2) | (self.vk & 0xf) + return 0x9600 | (((self.Rd//2)-12) << 4) | ((self.vk & 0x30) << 2) | (self.vk & 0xf) def analyze_results(self): self.reg_changed.extend( [self.Rd, self.Rd+1, Reg.SREG] ) @@ -92,7 +92,7 @@ class test_ADIW_r%02d_v%04x_k%02x(base_ADIW): vd = 0x%x vk = 0x%x def fail(self,s): - raise ADIW_r%02d_v%04x_k%02x_TestFail, s + raise ADIW_r%02d_v%04x_k%02x_TestFail(s) """ # reg val, k val (0x00 <= k <= 0x3f) @@ -116,4 +116,4 @@ for d in range(24,32,2): for vd,vk in vals: args = (d,vd,vk)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_AND.py b/regress/test_opcodes/test_AND.py index b11c578..e95f534 100644 --- a/regress/test_opcodes/test_AND.py +++ b/regress/test_opcodes/test_AND.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -90,7 +90,7 @@ class test_AND_rd%02d_vd%02x_rr%02d_vr%02x(base_AND): Rr = %d Vr = 0x%x def fail(self,s): - raise AND_rd%02d_vd%02x_rr%02d_vr%02x_TestFail, s + raise AND_rd%02d_vd%02x_rr%02d_vr%02x_TestFail(s) """ # @@ -125,4 +125,4 @@ for d in range(0,32,4): args = (d,vd,d,vd)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_ANDI.py b/regress/test_opcodes/test_ANDI.py index 2513f6a..dd3c7c5 100644 --- a/regress/test_opcodes/test_ANDI.py +++ b/regress/test_opcodes/test_ANDI.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -88,7 +88,7 @@ class test_ANDI_r%02d_v%02x_k%02x(base_ANDI): Vd = 0x%x Vk = 0x%x def fail(self,s): - raise ANDI_r%02d_v%02x_k%02x_TestFail, s + raise ANDI_r%02d_v%02x_k%02x_TestFail(s) """ # @@ -113,4 +113,4 @@ for d in range(16,32): args = (d,vd,vk)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_ASR.py b/regress/test_opcodes/test_ASR.py index 4808e9f..4df452d 100644 --- a/regress/test_opcodes/test_ASR.py +++ b/regress/test_opcodes/test_ASR.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -90,7 +90,7 @@ class test_ASR_r%02d_v%02x(base_ASR): Rd = %d Vd = 0x%x def fail(self,s): - raise ASR_r%02d_v%02x_TestFail, s + raise ASR_r%02d_v%02x_TestFail(s) """ # @@ -113,4 +113,4 @@ for d in range(32): args = (d,vd)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_BCLR.py b/regress/test_opcodes/test_BCLR.py index 0b6d9c2..f6df9f3 100644 --- a/regress/test_opcodes/test_BCLR.py +++ b/regress/test_opcodes/test_BCLR.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -66,7 +66,7 @@ class BCLR_bit%d_TestFail(BCLR_TestFail): pass class test_BCLR_bit%d(base_BCLR): bit = %d def fail(self,s): - raise BCLR_bit%d_TestFail, s + raise BCLR_bit%d_TestFail(s) """ # @@ -75,4 +75,4 @@ class test_BCLR_bit%d(base_BCLR): code = '' for b in range(8): code += template % (b,b,b,b) -exec code +exec(code) diff --git a/regress/test_opcodes/test_BLD.py b/regress/test_opcodes/test_BLD.py index 1f581cf..a4fd8c9 100644 --- a/regress/test_opcodes/test_BLD.py +++ b/regress/test_opcodes/test_BLD.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -76,7 +76,7 @@ class test_BLD_r%02d_bit%d_T%d(base_BLD): bit = %d T = %d def fail(self,s): - raise BLD_r%02d_bit%d_T%d_TestFail, s + raise BLD_r%02d_bit%d_T%d_TestFail(s) """ # @@ -87,4 +87,4 @@ for t in (0,1): for r in range(32): for b in range(8): code += template % (r,b,t, r,b,t, r,b,t, r,b,t) -exec code +exec(code) diff --git a/regress/test_opcodes/test_BRBC.py b/regress/test_opcodes/test_BRBC.py index ac743e1..64a2269 100644 --- a/regress/test_opcodes/test_BRBC.py +++ b/regress/test_opcodes/test_BRBC.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -74,7 +74,7 @@ class test_BRBC_bit%d_is_%d(base_BRBC): bit = %d val = %d def fail(self,s): - raise BRBC_bit%d_is_%d_TestFail, s + raise BRBC_bit%d_is_%d_TestFail(s) """ # @@ -84,4 +84,4 @@ code = '' for b in range(8): for v in range(2): code += template % (b,v,b,v,b,v,b,v) -exec code +exec(code) diff --git a/regress/test_opcodes/test_BRBS.py b/regress/test_opcodes/test_BRBS.py index 3573306..2102774 100644 --- a/regress/test_opcodes/test_BRBS.py +++ b/regress/test_opcodes/test_BRBS.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -74,7 +74,7 @@ class test_BRBS_bit%d_is_%d(base_BRBS): bit = %d val = %d def fail(self,s): - raise BRBS_bit%d_is_%d_TestFail, s + raise BRBS_bit%d_is_%d_TestFail(s) """ # @@ -84,4 +84,4 @@ code = '' for b in range(8): for v in range(2): code += template % (b,v,b,v,b,v,b,v) -exec code +exec(code) diff --git a/regress/test_opcodes/test_BSET.py b/regress/test_opcodes/test_BSET.py index 4ca8371..8af1064 100644 --- a/regress/test_opcodes/test_BSET.py +++ b/regress/test_opcodes/test_BSET.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -66,7 +66,7 @@ class BSET_bit%d_TestFail(BSET_TestFail): pass class test_BSET_bit%d(base_BSET): bit = %d def fail(self,s): - raise BSET_bit%d_TestFail, s + raise BSET_bit%d_TestFail(s) """ # @@ -75,4 +75,4 @@ class test_BSET_bit%d(base_BSET): code = '' for b in range(8): code += template % (b,b,b,b) -exec code +exec(code) diff --git a/regress/test_opcodes/test_BST.py b/regress/test_opcodes/test_BST.py index 30a2a0b..67b1e7a 100644 --- a/regress/test_opcodes/test_BST.py +++ b/regress/test_opcodes/test_BST.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -76,7 +76,7 @@ class test_BST_r%02d_bit%d_T%d(base_BST): bit = %d T = %d def fail(self,s): - raise BST_r%02d_bit%d_T%d_TestFail, s + raise BST_r%02d_bit%d_T%d_TestFail(s) """ # @@ -87,4 +87,4 @@ for t in (0,1): for r in range(32): for b in range(8): code += template % (r,b,t, r,b,t, r,b,t, r,b,t) -exec code +exec(code) diff --git a/regress/test_opcodes/test_CALL.py b/regress/test_opcodes/test_CALL.py index e9ef1c3..b99839d 100644 --- a/regress/test_opcodes/test_CALL.py +++ b/regress/test_opcodes/test_CALL.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -82,7 +82,7 @@ class CALL_%06x_TestFail(CALL_TestFail): pass class test_CALL_%06x(base_CALL): k = 0x%x def fail(self,s): - raise CALL_%06x_TestFail, s + raise CALL_%06x_TestFail(s) """ # @@ -95,4 +95,4 @@ class test_CALL_%06x(base_CALL): code = '' for k in (0x100, 0x3ff): code += template % ((k & 0xffffff), (k & 0xffffff), k, (k & 0xffffff)) -exec code +exec(code) diff --git a/regress/test_opcodes/test_COM.py b/regress/test_opcodes/test_COM.py index 5771d71..7d22ddf 100644 --- a/regress/test_opcodes/test_COM.py +++ b/regress/test_opcodes/test_COM.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -88,7 +88,7 @@ class test_COM_r%02d_v%02x(base_COM): Rd = %d Vd = 0x%x def fail(self,s): - raise COM_r%02d_v%02x_TestFail, s + raise COM_r%02d_v%02x_TestFail(s) """ # @@ -111,4 +111,4 @@ for d in range(32): args = (d,vd)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_CP.py b/regress/test_opcodes/test_CP.py index 0a81938..ce4a57c 100644 --- a/regress/test_opcodes/test_CP.py +++ b/regress/test_opcodes/test_CP.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -90,7 +90,7 @@ class test_CP_rd%02d_v%02x_rr%02d_v%02x(base_CP): Rr = %d Vr = 0x%x def fail(self,s): - raise CP_rd%02d_v%02x_rr%02d_v%02x_TestFail, s + raise CP_rd%02d_v%02x_rr%02d_v%02x_TestFail(s) """ # @@ -117,4 +117,4 @@ for d in range(0,32,8): args = (d,vd,r,vr)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_CPC.py b/regress/test_opcodes/test_CPC.py index 5d87ea5..1cc3956 100644 --- a/regress/test_opcodes/test_CPC.py +++ b/regress/test_opcodes/test_CPC.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -99,7 +99,7 @@ class test_CPC_rd%02d_v%02x_rr%02d_v%02x_C%d_Z%d(base_CPC): C = %d Z = %d def fail(self,s): - raise CPC_rd%02d_v%02x_rr%02d_v%02x_C%d_Z%d_TestFail, s + raise CPC_rd%02d_v%02x_rr%02d_v%02x_C%d_Z%d_TestFail(s) """ # @@ -127,4 +127,4 @@ for c,z in [ (0,0), (0,1), (1,0), (1,1) ]: args = (d,vd,r,vr,c,z)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_CPI.py b/regress/test_opcodes/test_CPI.py index 8ac9d74..6a1a124 100644 --- a/regress/test_opcodes/test_CPI.py +++ b/regress/test_opcodes/test_CPI.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -88,7 +88,7 @@ class test_CPI_r%02d_v%02x_k%02x(base_CPI): Vd = 0x%x Vk = 0x%x def fail(self,s): - raise CPI_r%02d_v%02x_k%02x_TestFail, s + raise CPI_r%02d_v%02x_k%02x_TestFail(s) """ # @@ -114,4 +114,4 @@ for d in range(16,32): args = (d,vd,vk)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_CPSE.py b/regress/test_opcodes/test_CPSE.py index 3d4a85e..ad3031a 100644 --- a/regress/test_opcodes/test_CPSE.py +++ b/regress/test_opcodes/test_CPSE.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -87,7 +87,7 @@ class test_CPSE_rd%02d_vd%02x_rr%02d_vr%02x_ni%d(base_CPSE): vr = 0x%x ni = %d def fail(self,s): - raise CPSE_rd%02d_vd%02x_rr%02d_vr%02x_ni%d_TestFail, s + raise CPSE_rd%02d_vd%02x_rr%02d_vr%02x_ni%d_TestFail(s) """ vals = ( @@ -113,4 +113,4 @@ for d in range(0,32,step): for ni in (16,32): # is next insn 16 or 32 bits args = (d,vd,d,vd,ni)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_DEC.py b/regress/test_opcodes/test_DEC.py index 5c06516..6158a89 100644 --- a/regress/test_opcodes/test_DEC.py +++ b/regress/test_opcodes/test_DEC.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -88,7 +88,7 @@ class test_DEC_r%02d_v%02x(base_DEC): Rd = %d Vd = 0x%x def fail(self,s): - raise DEC_r%02d_v%02x_TestFail, s + raise DEC_r%02d_v%02x_TestFail(s) """ # @@ -112,4 +112,4 @@ for d in range(32): args = (d,vd)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_EICALL.py b/regress/test_opcodes/test_EICALL.py index e1625f7..8ab901a 100644 --- a/regress/test_opcodes/test_EICALL.py +++ b/regress/test_opcodes/test_EICALL.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -52,8 +52,8 @@ class base_EICALL(base_test.opcode_eind_stack_test): def setup(self): - if (not self.target.has_eind): - self.fail('EICALL failed: Not supported by this device %s' % self.target.device) + if (not self.target.has_eind): + self.fail('EICALL failed: Not supported by this device %s' % self.target.device) # setup PC self.setup_regs[Reg.PC] = 0xff * 2 @@ -62,9 +62,9 @@ class base_EICALL(base_test.opcode_eind_stack_test): self.setup_regs[Reg.R30] = self.k & 0xff self.setup_regs[Reg.R31] = self.k >> 8 & 0xff - #setup EIND register - self.write_register_eind(self.eind & 0xff) - + #setup EIND register + self.write_register_eind(self.eind & 0xff) + return 0x9519 def analyze_results(self): @@ -97,7 +97,7 @@ class test_EICALL_k%04x_ei%02x(base_EICALL): k = 0x%x eind = 0x%x def fail(self,s): - raise EICALL_k%04x_ei%02x_TestFail, s + raise EICALL_k%04x_ei%02x_TestFail(s) """ # @@ -109,5 +109,5 @@ for k in (0x100,0x3ff): for eind in (0x00, 0x01): km = k & 0x3fffff args = (km, eind) * 4 - code += template % args -exec code + code += template % args +exec(code) diff --git a/regress/test_opcodes/test_EIJMP.py b/regress/test_opcodes/test_EIJMP.py index 68e0502..431d7f4 100644 --- a/regress/test_opcodes/test_EIJMP.py +++ b/regress/test_opcodes/test_EIJMP.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -53,8 +53,8 @@ class base_EIJMP(base_test.opcode_eind_test): self.setup_regs[Reg.R31] = (self.k >> 8) & 0xff self.setup_regs[Reg.R30] = (self.k & 0xff) - #setup EIND register - self.write_register_eind(self.eind & 0xff) + #setup EIND register + self.write_register_eind(self.eind & 0xff) return 0x9419 @@ -79,7 +79,7 @@ class test_EIJMP_k%06x_ei%02x(base_EIJMP): k = 0x%x eind = 0x%x def fail(self,s): - raise EIJMP_k%06x_ei%02x_TestFail, s + raise EIJMP_k%06x_ei%02x_TestFail(s) """ # @@ -89,5 +89,5 @@ code = '' for k in (0x36, 0x100, 0x3ff): for eind in (0x00, 0x01): args = (k, eind) * 4 - code += template % args -exec code + code += template % args +exec(code) diff --git a/regress/test_opcodes/test_ELPM.py b/regress/test_opcodes/test_ELPM.py index bfbf098..d74104e 100644 --- a/regress/test_opcodes/test_ELPM.py +++ b/regress/test_opcodes/test_ELPM.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -51,8 +51,8 @@ class base_ELPM(base_test.opcode_rampz_test): self.setup_regs[Reg.R30] = (self.Z & 0xff) self.setup_regs[Reg.R31] = (self.Z >> 8) - #setup RAMPZ register - self.write_register_rampz(self.rampz & 0xff) + #setup RAMPZ register + self.write_register_rampz(self.rampz & 0xff) # set up the val in memory self.prog_word_write(((self.rampz << 16) + self.Z) & 0xfffffe, 0xaa55 ) @@ -83,9 +83,9 @@ class ELPM_Z%04x_RZ%02x_TestFail(ELPM_TestFail): pass class test_ELPM_Z%04x_RZ%02x(base_ELPM): Z = 0x%x - rampz = 0x%x + rampz = 0x%x def fail(self,s): - raise ELPM_Z%04x_RZ%02x_TestFail, s + raise ELPM_Z%04x_RZ%02x_TestFail(s) """ # @@ -94,6 +94,6 @@ class test_ELPM_Z%04x_RZ%02x(base_ELPM): code = '' for z in (0x10, 0x11, 0x100, 0x101): for rampz in (0x00, 0x01, 0x02): - args = (z, rampz) * 4 - code += template % args -exec code + args = (z, rampz) * 4 + code += template % args +exec(code) diff --git a/regress/test_opcodes/test_ELPM_Z.py b/regress/test_opcodes/test_ELPM_Z.py index ed5bc1b..5a7218c 100644 --- a/regress/test_opcodes/test_ELPM_Z.py +++ b/regress/test_opcodes/test_ELPM_Z.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -86,7 +86,7 @@ class test_ELPM_Z_r%02d_Z%04x_RZ%02x(base_ELPM_Z): Z = 0x%x rampz = 0x%x def fail(self,s): - raise ELPM_Z_r%02d_Z%04x_RZ%02x_TestFail, s + raise ELPM_Z_r%02d_Z%04x_RZ%02x_TestFail(s) """ # @@ -98,4 +98,4 @@ for d in range(32): for rampz in (0x00, 0x01, 0x02): args = (d, z, rampz) * 4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_ELPM_Z_incr.py b/regress/test_opcodes/test_ELPM_Z_incr.py index 64446d0..d42a3d0 100644 --- a/regress/test_opcodes/test_ELPM_Z_incr.py +++ b/regress/test_opcodes/test_ELPM_Z_incr.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -76,7 +76,7 @@ class base_ELPM_Z_incr(base_test.opcode_rampz_test): # check that Z was incremented expect = ((self.rampz << 16) + self.Z) + 1 - actual_rampz = self.read_register_rampz() + actual_rampz = self.read_register_rampz() got = (self.anal_regs[Reg.R30] & 0xff) | ((self.anal_regs[Reg.R31] << 8) & 0xff00) | ((actual_rampz << 16) & 0xff0000) if expect != got: @@ -92,9 +92,9 @@ class ELPM_Z_incr_r%02d_Z%04x_RZ%02x_TestFail(ELPM_Z_incr_TestFail): pass class test_ELPM_Z_incr_r%02d_Z%04x_RZ%02x(base_ELPM_Z_incr): Rd = %d Z = 0x%x - rampz = 0x%x + rampz = 0x%x def fail(self,s): - raise ELPM_Z_incr_r%02d_Z%04x_RZ%02x_TestFail, s + raise ELPM_Z_incr_r%02d_Z%04x_RZ%02x_TestFail(s) """ # @@ -104,8 +104,8 @@ class test_ELPM_Z_incr_r%02d_Z%04x_RZ%02x(base_ELPM_Z_incr): # code = '' for d in range(30): - for z in (0x10, 0x11, 0x100, 0x101, 0xFFFF): + for z in (0x10, 0x11, 0x100, 0x101, 0xFFFF): for rampz in (0x00, 0x01, 0x02): - args = (d, z, rampz) * 4 - code += template % args -exec code + args = (d, z, rampz) * 4 + code += template % args +exec(code) diff --git a/regress/test_opcodes/test_EOR.py b/regress/test_opcodes/test_EOR.py index 62587cd..f5fcd10 100644 --- a/regress/test_opcodes/test_EOR.py +++ b/regress/test_opcodes/test_EOR.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -90,7 +90,7 @@ class test_EOR_r%02d_v%02x_r%02d_v%02x(base_EOR): Rr = %d Vr = 0x%x def fail(self,s): - raise EOR_r%02d_v%02x_r%02d_v%02x_TestFail, s + raise EOR_r%02d_v%02x_r%02d_v%02x_TestFail(s) """ # @@ -117,4 +117,4 @@ for d in range(0,32,4): args = (d,vd,r,vr)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_ICALL.py b/regress/test_opcodes/test_ICALL.py index 2704bbe..2572e9c 100644 --- a/regress/test_opcodes/test_ICALL.py +++ b/regress/test_opcodes/test_ICALL.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -84,7 +84,7 @@ class ICALL_%04x_TestFail(ICALL_TestFail): pass class test_ICALL_%04x(base_ICALL): k = 0x%x def fail(self,s): - raise ICALL_%04x_TestFail, s + raise ICALL_%04x_TestFail(s) """ # @@ -93,4 +93,4 @@ class test_ICALL_%04x(base_ICALL): code = '' for k in (0x100,0x3ff): code += template % ((k & 0xffff), (k & 0xffff), k, (k & 0xffff)) -exec code +exec(code) diff --git a/regress/test_opcodes/test_IJMP.py b/regress/test_opcodes/test_IJMP.py index 0145c79..f3123db 100644 --- a/regress/test_opcodes/test_IJMP.py +++ b/regress/test_opcodes/test_IJMP.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -68,7 +68,7 @@ class IJMP_%06x_TestFail(IJMP_TestFail): pass class test_IJMP_%06x(base_IJMP): k = 0x%x def fail(self,s): - raise IJMP_%06x_TestFail, s + raise IJMP_%06x_TestFail(s) """ # @@ -77,4 +77,4 @@ class test_IJMP_%06x(base_IJMP): code = '' for k in (0x36, 0x100, 0x3ff): code += template % (k, k, k, k) -exec code +exec(code) diff --git a/regress/test_opcodes/test_INC.py b/regress/test_opcodes/test_INC.py index 587b27b..6a54a5e 100644 --- a/regress/test_opcodes/test_INC.py +++ b/regress/test_opcodes/test_INC.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -88,7 +88,7 @@ class test_INC_r%02d_v%02x(base_INC): Rd = %d Vd = 0x%x def fail(self,s): - raise INC_r%02d_v%02x_TestFail, s + raise INC_r%02d_v%02x_TestFail(s) """ # @@ -113,4 +113,4 @@ for d in range(32): args = (d,vd)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_JMP.py b/regress/test_opcodes/test_JMP.py index 14864b9..7907d9d 100644 --- a/regress/test_opcodes/test_JMP.py +++ b/regress/test_opcodes/test_JMP.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -66,7 +66,7 @@ class JMP_%06x_TestFail(JMP_TestFail): pass class test_JMP_%06x(base_JMP): k = 0x%x def fail(self,s): - raise JMP_%06x_TestFail, s + raise JMP_%06x_TestFail(s) """ # @@ -75,4 +75,4 @@ class test_JMP_%06x(base_JMP): code = '' for k in (0x100, 0x3ff): code += template % (k, k, k, k) -exec code +exec(code) diff --git a/regress/test_opcodes/test_LDD_Y.py b/regress/test_opcodes/test_LDD_Y.py index afa6c5b..fd57687 100644 --- a/regress/test_opcodes/test_LDD_Y.py +++ b/regress/test_opcodes/test_LDD_Y.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -79,7 +79,7 @@ class test_LDD_Y_r%02d_Y%04x_q%02x_v%02x(base_LDD_Y): q = 0x%x Vd = 0x%x def fail(self,s): - raise LDD_Y_r%02d_Y%04x_q%02x_v%02x_TestFail, s + raise LDD_Y_r%02d_Y%04x_q%02x_v%02x_TestFail(s) """ # @@ -92,4 +92,4 @@ for d in range(0,32,4): for v in (0xaa, 0x55): args = (d,y,q,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_LDD_Z.py b/regress/test_opcodes/test_LDD_Z.py index 35697b8..30d738b 100644 --- a/regress/test_opcodes/test_LDD_Z.py +++ b/regress/test_opcodes/test_LDD_Z.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -79,7 +79,7 @@ class test_LDD_Z_r%02d_Z%04x_q%02x_v%02x(base_LDD_Z): q = 0x%x Vd = 0x%x def fail(self,s): - raise LDD_Z_r%02d_Z%04x_q%02x_v%02x_TestFail, s + raise LDD_Z_r%02d_Z%04x_q%02x_v%02x_TestFail(s) """ # @@ -92,4 +92,4 @@ for d in range(0,32,4): for v in (0xaa, 0x55): args = (d,z,q,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_LDI.py b/regress/test_opcodes/test_LDI.py index 5e9dc28..6b76f22 100644 --- a/regress/test_opcodes/test_LDI.py +++ b/regress/test_opcodes/test_LDI.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -69,7 +69,7 @@ class test_LDI_r%02d_v%02x(base_LDI): Rd = %d Vd = 0x%x def fail(self,s): - raise LDI_r%02d_v%02x_TestFail, s + raise LDI_r%02d_v%02x_TestFail(s) """ # @@ -92,4 +92,4 @@ for d in range(16,32): args = (d,vd)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_LDS.py b/regress/test_opcodes/test_LDS.py index 2518b7b..6397f7d 100644 --- a/regress/test_opcodes/test_LDS.py +++ b/regress/test_opcodes/test_LDS.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -80,7 +80,7 @@ class test_LDS_r%02d_k%04x_v%02x(base_LDS): k = 0x%x v = 0x%x def fail(self,s): - raise LDS_r%02d_k%04x_v%02x_TestFail, s + raise LDS_r%02d_k%04x_v%02x_TestFail(s) """ # @@ -92,4 +92,4 @@ for d in range(0,32): for v in (0xaa, 0x55): args = (d,k,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_LD_X.py b/regress/test_opcodes/test_LD_X.py index fe6010c..9cbc5f6 100644 --- a/regress/test_opcodes/test_LD_X.py +++ b/regress/test_opcodes/test_LD_X.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -76,7 +76,7 @@ class test_LD_X_r%02d_X%04x_v%02x(base_LD_X): X = 0x%x Vd = 0x%x def fail(self,s): - raise LD_X_r%02d_X%04x_v%02x_TestFail, s + raise LD_X_r%02d_X%04x_v%02x_TestFail(s) """ # @@ -88,4 +88,4 @@ for d in range(0,32): for v in (0xaa, 0x55): args = (d,x,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_LD_X_decr.py b/regress/test_opcodes/test_LD_X_decr.py index 36800fd..5242b39 100644 --- a/regress/test_opcodes/test_LD_X_decr.py +++ b/regress/test_opcodes/test_LD_X_decr.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -85,7 +85,7 @@ class test_LD_X_decr_r%02d_X%04x_v%02x(base_LD_X_decr): X = 0x%x Vd = 0x%x def fail(self,s): - raise LD_X_decr_r%02d_X%04x_v%02x_TestFail, s + raise LD_X_decr_r%02d_X%04x_v%02x_TestFail(s) """ # @@ -94,9 +94,9 @@ class test_LD_X_decr_r%02d_X%04x_v%02x(base_LD_X_decr): # Operation is undefined for d = 26 and d = 27. # code = '' -for d in range(0,26)+range(28,32): +for d in list(range(0,26))+list(range(28,32)): for x in (0x20f, 0x2ff): for v in (0xaa, 0x55): args = (d,x,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_LD_X_incr.py b/regress/test_opcodes/test_LD_X_incr.py index 83392ff..66e4029 100644 --- a/regress/test_opcodes/test_LD_X_incr.py +++ b/regress/test_opcodes/test_LD_X_incr.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -85,7 +85,7 @@ class test_LD_X_incr_r%02d_X%04x_v%02x(base_LD_X_incr): X = 0x%x Vd = 0x%x def fail(self,s): - raise LD_X_incr_r%02d_X%04x_v%02x_TestFail, s + raise LD_X_incr_r%02d_X%04x_v%02x_TestFail(s) """ # @@ -94,9 +94,9 @@ class test_LD_X_incr_r%02d_X%04x_v%02x(base_LD_X_incr): # Operation is undefined for d = 26 and d = 27. # code = '' -for d in range(0,26)+range(28,32): +for d in list(range(0,26))+list(range(28,32)): for x in (0x20f, 0x2ff): for v in (0xaa, 0x55): args = (d,x,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_LD_Y_decr.py b/regress/test_opcodes/test_LD_Y_decr.py index 908e854..ba452d2 100644 --- a/regress/test_opcodes/test_LD_Y_decr.py +++ b/regress/test_opcodes/test_LD_Y_decr.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -85,7 +85,7 @@ class test_LD_Y_decr_r%02d_Y%04x_v%02x(base_LD_Y_decr): Y = 0x%x Vd = 0x%x def fail(self,s): - raise LD_Y_decr_r%02d_Y%04x_v%02x_TestFail, s + raise LD_Y_decr_r%02d_Y%04x_v%02x_TestFail(s) """ # @@ -94,9 +94,9 @@ class test_LD_Y_decr_r%02d_Y%04x_v%02x(base_LD_Y_decr): # Operation is undefined for d = 28 and d = 29. # code = '' -for d in range(0,28)+range(30,32): +for d in list(range(0,28))+list(range(30,32)): for y in (0x20f, 0x2ff): for v in (0xaa, 0x55): args = (d,y,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_LD_Y_incr.py b/regress/test_opcodes/test_LD_Y_incr.py index 43d955e..50ba9c9 100644 --- a/regress/test_opcodes/test_LD_Y_incr.py +++ b/regress/test_opcodes/test_LD_Y_incr.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -85,7 +85,7 @@ class test_LD_Y_incr_r%02d_Y%04x_v%02x(base_LD_Y_incr): Y = 0x%x Vd = 0x%x def fail(self,s): - raise LD_Y_incr_r%02d_Y%04x_v%02x_TestFail, s + raise LD_Y_incr_r%02d_Y%04x_v%02x_TestFail(s) """ # @@ -94,9 +94,9 @@ class test_LD_Y_incr_r%02d_Y%04x_v%02x(base_LD_Y_incr): # Operation is undefined for d = 28 and d = 29. # code = '' -for d in range(0,28)+range(30,32): +for d in list(range(0,28))+list(range(30,32)): for y in (0x20f, 0x2ff): for v in (0xaa, 0x55): args = (d,y,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_LD_Z_decr.py b/regress/test_opcodes/test_LD_Z_decr.py index 24660f1..23eef09 100644 --- a/regress/test_opcodes/test_LD_Z_decr.py +++ b/regress/test_opcodes/test_LD_Z_decr.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -85,7 +85,7 @@ class test_LD_Z_decr_r%02d_Z%04x_v%02x(base_LD_Z_decr): Z = 0x%x Vd = 0x%x def fail(self,s): - raise LD_Z_decr_r%02d_Z%04x_v%02x_TestFail, s + raise LD_Z_decr_r%02d_Z%04x_v%02x_TestFail(s) """ # @@ -99,4 +99,4 @@ for d in range(0,30): for v in (0xaa, 0x55): args = (d,z,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_LD_Z_incr.py b/regress/test_opcodes/test_LD_Z_incr.py index 38c0531..e581a5b 100644 --- a/regress/test_opcodes/test_LD_Z_incr.py +++ b/regress/test_opcodes/test_LD_Z_incr.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -85,7 +85,7 @@ class test_LD_Z_incr_r%02d_Z%04x_v%02x(base_LD_Z_incr): Z = 0x%x Vd = 0x%x def fail(self,s): - raise LD_Z_incr_r%02d_Z%04x_v%02x_TestFail, s + raise LD_Z_incr_r%02d_Z%04x_v%02x_TestFail(s) """ # @@ -99,4 +99,4 @@ for d in range(0,30): for v in (0xaa, 0x55): args = (d,z,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_LPM.py b/regress/test_opcodes/test_LPM.py index 14a28b8..ff70108 100644 --- a/regress/test_opcodes/test_LPM.py +++ b/regress/test_opcodes/test_LPM.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -78,7 +78,7 @@ class LPM_Z%04x_TestFail(LPM_TestFail): pass class test_LPM_Z%04x(base_LPM): Z = 0x%x def fail(self,s): - raise LPM_Z%04x_TestFail, s + raise LPM_Z%04x_TestFail(s) """ # @@ -88,4 +88,4 @@ code = '' for z in (0x10, 0x11, 0x100, 0x101): args = (z,)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_LPM_Z.py b/regress/test_opcodes/test_LPM_Z.py index f550cd4..26ea9e8 100644 --- a/regress/test_opcodes/test_LPM_Z.py +++ b/regress/test_opcodes/test_LPM_Z.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -79,7 +79,7 @@ class test_LPM_Z_r%02d_Z%04x(base_LPM_Z): Rd = %d Z = 0x%x def fail(self,s): - raise LPM_Z_r%02d_Z%04x_TestFail, s + raise LPM_Z_r%02d_Z%04x_TestFail(s) """ # @@ -90,4 +90,4 @@ for d in range(32): for z in (0x10, 0x11, 0x100, 0x101): args = (d,z)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_LPM_Z_incr.py b/regress/test_opcodes/test_LPM_Z_incr.py index b3c2619..8763ca9 100644 --- a/regress/test_opcodes/test_LPM_Z_incr.py +++ b/regress/test_opcodes/test_LPM_Z_incr.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -86,7 +86,7 @@ class test_LPM_Z_incr_r%02d_Z%04x(base_LPM_Z_incr): Rd = %d Z = 0x%x def fail(self,s): - raise LPM_Z_incr_r%02d_Z%04x_TestFail, s + raise LPM_Z_incr_r%02d_Z%04x_TestFail(s) """ # @@ -99,4 +99,4 @@ for d in range(30): for z in (0x10, 0x11, 0x100, 0x101): args = (d,z)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_LSR.py b/regress/test_opcodes/test_LSR.py index dc3db06..30080fc 100644 --- a/regress/test_opcodes/test_LSR.py +++ b/regress/test_opcodes/test_LSR.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -89,7 +89,7 @@ class test_LSR_r%02d_v%02x(base_LSR): Rd = %d Vd = 0x%x def fail(self,s): - raise LSR_r%02d_v%02x_TestFail, s + raise LSR_r%02d_v%02x_TestFail(s) """ # @@ -112,4 +112,4 @@ for d in range(32): args = (d,vd)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_MOV.py b/regress/test_opcodes/test_MOV.py index 067f560..c178d5e 100644 --- a/regress/test_opcodes/test_MOV.py +++ b/regress/test_opcodes/test_MOV.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -61,7 +61,7 @@ class test_MOV_r%02d_r%02d(base_MOV): Rd = %d Rr = %d def fail(self,s): - raise MOV_r%02d_r%02d_TestFail, s + raise MOV_r%02d_r%02d_TestFail(s) """ # @@ -72,4 +72,4 @@ for d in range(0,32,8): for r in range(1,32,8): args = (d,r)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_MOVW.py b/regress/test_opcodes/test_MOVW.py index 6178708..9d96f57 100644 --- a/regress/test_opcodes/test_MOVW.py +++ b/regress/test_opcodes/test_MOVW.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -45,7 +45,7 @@ class base_MOVW(base_test.opcode_test): self.setup_regs[self.Rr+1] = 0x5a # opcode is '0000 0001 dddd rrrr' where d and r are Rd/2 and Rr/2 - return 0x0100 | ((self.Rd/2) << 4) | ((self.Rr/2) & 0xf) + return 0x0100 | ((self.Rd//2) << 4) | ((self.Rr//2) & 0xf) def analyze_results(self): self.reg_changed.extend( [self.Rd,self.Rd+1] ) @@ -64,7 +64,7 @@ class test_MOVW_r%02d_r%02d(base_MOVW): Rd = %d Rr = %d def fail(self,s): - raise MOVW_r%02d_r%02d_TestFail, s + raise MOVW_r%02d_r%02d_TestFail(s) """ # @@ -75,4 +75,4 @@ for d in range(0,32,4): for r in range(2,32,4): args = (d,r)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_MUL.py b/regress/test_opcodes/test_MUL.py index d9b3b55..6026040 100644 --- a/regress/test_opcodes/test_MUL.py +++ b/regress/test_opcodes/test_MUL.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -90,7 +90,7 @@ class test_MUL_rd%02d_vd%02x_rr%02d_vr%02x(base_MUL): Rr = %d Vr = 0x%x def fail(self,s): - raise MUL_rd%02d_vd%02x_rr%02d_vr%02xTestFail, s + raise MUL_rd%02d_vd%02x_rr%02d_vr%02xTestFail(s) """ # @@ -124,4 +124,4 @@ for d in range(0,32,step): for vd,vr in vals: args = (d, vd, d, vd)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_MULS.py b/regress/test_opcodes/test_MULS.py index 2ca2016..197999e 100644 --- a/regress/test_opcodes/test_MULS.py +++ b/regress/test_opcodes/test_MULS.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -97,7 +97,7 @@ class test_MULS_rd%02d_vd%02x_rr%02d_vr%02x(base_MULS): Rr = %d Vr = %d def fail(self,s): - raise MULS_rd%02d_vd%02x_rr%02d_vr%02x_TestFail, s + raise MULS_rd%02d_vd%02x_rr%02d_vr%02x_TestFail(s) """ # @@ -135,4 +135,4 @@ for d in range(16,32,step): for vd,vr in vals: args = (d, vd, d, vd)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_MULSU.py b/regress/test_opcodes/test_MULSU.py index 416a93a..1f3409d 100644 --- a/regress/test_opcodes/test_MULSU.py +++ b/regress/test_opcodes/test_MULSU.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -95,7 +95,7 @@ class test_MULSU_rd%02d_vd%02x_rr%02d_vr%02x(base_MULSU): Rr = %d Vr = %d def fail(self,s): - raise MULSU_rd%02d_vd%02x_rr%02d_vr%02x_TestFail, s + raise MULSU_rd%02d_vd%02x_rr%02d_vr%02x_TestFail(s) """ # @@ -135,4 +135,4 @@ for d in range(16,24,step): for vd,vr in vals: args = (d, vd, d, vd)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_NEG.py b/regress/test_opcodes/test_NEG.py index d7b04bb..8ca0d30 100644 --- a/regress/test_opcodes/test_NEG.py +++ b/regress/test_opcodes/test_NEG.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -91,7 +91,7 @@ class test_NEG_r%02d_v%02x(base_NEG): Rd = %d Vd = 0x%x def fail(self,s): - raise NEG_r%02d_v%02x_TestFail, s + raise NEG_r%02d_v%02x_TestFail(s) """ # @@ -115,4 +115,4 @@ for d in range(32): args = (d,vd)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_NOP.py b/regress/test_opcodes/test_NOP.py index 4fa3d0f..8bc4326 100644 --- a/regress/test_opcodes/test_NOP.py +++ b/regress/test_opcodes/test_NOP.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. diff --git a/regress/test_opcodes/test_OR.py b/regress/test_opcodes/test_OR.py index a02b1ca..f88e6a1 100644 --- a/regress/test_opcodes/test_OR.py +++ b/regress/test_opcodes/test_OR.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -90,7 +90,7 @@ class test_OR_rd%02d_vd%02x_rr%02d_vr%02x(base_OR): Rr = %d Vr = 0x%x def fail(self,s): - raise OR_rd%02d_vd%02x_rr%02d_vr%02x_TestFail, s + raise OR_rd%02d_vd%02x_rr%02d_vr%02x_TestFail(s) """ # @@ -117,4 +117,4 @@ for d in range(0,32,4): args = (d,vd,r,vr)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_ORI.py b/regress/test_opcodes/test_ORI.py index bcb998f..26ae9fd 100644 --- a/regress/test_opcodes/test_ORI.py +++ b/regress/test_opcodes/test_ORI.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -88,7 +88,7 @@ class test_ORI_r%02d_v%02x_k%02x(base_ORI): Vd = 0x%x Vk = 0x%x def fail(self,s): - raise ORI_r%02d_v%02x_k%02x_TestFail, s + raise ORI_r%02d_v%02x_k%02x_TestFail(s) """ # @@ -113,4 +113,4 @@ for d in range(16,32): args = (d,vd,vk)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_POP.py b/regress/test_opcodes/test_POP.py index e7d3e9b..8946524 100644 --- a/regress/test_opcodes/test_POP.py +++ b/regress/test_opcodes/test_POP.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -83,7 +83,7 @@ class test_POP_r%02d_%02x(base_POP): Rd = %d k = 0x%x def fail(self,s): - raise POP_r%02d_%02x_TestFail, s + raise POP_r%02d_%02x_TestFail(s) """ # @@ -94,4 +94,4 @@ for rd in range(32): for k in (0x55,0xaa): args = (rd,k)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_PUSH.py b/regress/test_opcodes/test_PUSH.py index 20b98e7..33059cd 100644 --- a/regress/test_opcodes/test_PUSH.py +++ b/regress/test_opcodes/test_PUSH.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -80,7 +80,7 @@ class test_PUSH_r%02d_%02x(base_PUSH): Rd = %d k = 0x%x def fail(self,s): - raise PUSH_r%02d_%02x_TestFail, s + raise PUSH_r%02d_%02x_TestFail(s) """ # @@ -91,4 +91,4 @@ for rd in range(32): for k in (0x55,0xaa): args = (rd,k)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_RCALL.py b/regress/test_opcodes/test_RCALL.py index 8493689..728c747 100644 --- a/regress/test_opcodes/test_RCALL.py +++ b/regress/test_opcodes/test_RCALL.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -83,7 +83,7 @@ class RCALL_%03x_TestFail(RCALL_TestFail): pass class test_RCALL_%03x(base_RCALL): k = 0x%x def fail(self,s): - raise RCALL_%03x_TestFail, s + raise RCALL_%03x_TestFail(s) """ # @@ -96,4 +96,4 @@ class test_RCALL_%03x(base_RCALL): code = '' for k in (-100,100): code += template % ((k & 0xfff), (k & 0xfff), (k & 0xfff), (k & 0xfff)) -exec code +exec(code) diff --git a/regress/test_opcodes/test_RET.py b/regress/test_opcodes/test_RET.py index 2365287..c555aec 100644 --- a/regress/test_opcodes/test_RET.py +++ b/regress/test_opcodes/test_RET.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -80,7 +80,7 @@ class test_RET_old_%06x_new_%06x(base_RET): old_pc = %d new_pc = %d def fail(self,s): - raise RET_new_%06x_old_%06x_TestFail, s + raise RET_new_%06x_old_%06x_TestFail(s) """ # @@ -92,7 +92,7 @@ for old_pc in (0,255,256,(8*1024/2-1)): for new_pc in (0,1,2,3,255,256,(8*1024/2-1)): args = (old_pc,new_pc)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_RETI.py b/regress/test_opcodes/test_RETI.py index 650c06e..353cc72 100644 --- a/regress/test_opcodes/test_RETI.py +++ b/regress/test_opcodes/test_RETI.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -93,7 +93,7 @@ class test_RETI_old_%06x_new_%06x(base_RETI): old_pc = 0x%06x new_pc = 0x%06x def fail(self,s): - raise RETI_new_%06x_old_%06x_TestFail, s + raise RETI_new_%06x_old_%06x_TestFail(s) """ # @@ -105,4 +105,4 @@ for old_pc in (0,255,256,(8*1024/2-1)): for new_pc in (0,1,2,3,255,256,(8*1024/2-1)): args = (old_pc,new_pc)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_RJMP.py b/regress/test_opcodes/test_RJMP.py index 074ac41..ee2d53c 100644 --- a/regress/test_opcodes/test_RJMP.py +++ b/regress/test_opcodes/test_RJMP.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -68,7 +68,7 @@ class RJMP_%03x_TestFail(RJMP_TestFail): pass class test_RJMP_%03x(base_RJMP): k = 0x%x def fail(self,s): - raise RJMP_%03x_TestFail, s + raise RJMP_%03x_TestFail(s) """ # @@ -81,4 +81,4 @@ class test_RJMP_%03x(base_RJMP): code = '' for k in (-100,100): code += template % ((k & 0xfff), (k & 0xfff), (k & 0xfff), (k & 0xfff)) -exec code +exec(code) diff --git a/regress/test_opcodes/test_ROR.py b/regress/test_opcodes/test_ROR.py index 984ed1d..ccfbe4a 100644 --- a/regress/test_opcodes/test_ROR.py +++ b/regress/test_opcodes/test_ROR.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -91,7 +91,7 @@ class test_ROR_r%02d_v%02x_C%d(base_ROR): Vd = 0x%x C = %d def fail(self,s): - raise ROR_r%02d_v%02x_C%d_TestFail, s + raise ROR_r%02d_v%02x_C%d_TestFail(s) """ # @@ -117,4 +117,4 @@ for c in (0,1): args = (d,vd,c)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_SBC.py b/regress/test_opcodes/test_SBC.py index e8f73e2..c0daa98 100644 --- a/regress/test_opcodes/test_SBC.py +++ b/regress/test_opcodes/test_SBC.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -42,7 +42,7 @@ class base_SBC(base_test.opcode_test): def setup(self): # Set SREG to zero or (Z and/or C flag set) self.setup_regs[Reg.SREG] = (self.C << SREG.C) | (self.Z << SREG.Z) - self.setup_regs[Reg.PC] = 0x0100 + self.setup_regs[Reg.PC] = 0x0100 # Set the register values self.setup_regs[self.Rd] = self.Vd @@ -102,7 +102,7 @@ class test_SBC_rd%02d_vd%02x_rr%02d_vr%02x_C%d_Z%d(base_SBC): C = %d Z = %d def fail(self,s): - raise SBC_rd%02d_vd%02x_rr%02d_vr%02x_C%d_Z%d_TestFail, s + raise SBC_rd%02d_vd%02x_rr%02d_vr%02x_C%d_Z%d_TestFail(s) """ # @@ -136,4 +136,4 @@ for c,z in ((0,0), (1,0), (0,1), (1,1)): for vd,vr in vals: args = (d,vd,d,vd,c,z)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_SBCI.py b/regress/test_opcodes/test_SBCI.py index 3359ccf..d512f8c 100644 --- a/regress/test_opcodes/test_SBCI.py +++ b/regress/test_opcodes/test_SBCI.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -99,7 +99,7 @@ class test_SBCI_r%02d_v%02x_k%02x_C%d_Z%d(base_SBCI): C = %d Z = %d def fail(self,s): - raise SBCI_r%02d_v%02x_k%02x_C%d_Z%d_TestFail, s + raise SBCI_r%02d_v%02x_k%02x_C%d_Z%d_TestFail(s) """ # @@ -126,4 +126,4 @@ for c,z in ((0,0), (1,0), (0,1), (1,1)): args = (d,vd,vk,c,z)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_SBIW.py b/regress/test_opcodes/test_SBIW.py index c4567a6..732165c 100644 --- a/regress/test_opcodes/test_SBIW.py +++ b/regress/test_opcodes/test_SBIW.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -48,7 +48,7 @@ class base_SBIW(base_test.opcode_test): self.setup_regs[self.Rd+1] = (self.vd >> 8) # Return the raw opcode - return 0x9700 | (((self.Rd/2)-12) << 4) | ((self.vk & 0x30) << 2) | (self.vk & 0xf) + return 0x9700 | (((self.Rd//2)-12) << 4) | ((self.vk & 0x30) << 2) | (self.vk & 0xf) def analyze_results(self): self.reg_changed.extend( [self.Rd, self.Rd+1, Reg.SREG] ) @@ -92,7 +92,7 @@ class test_SBIW_r%02d_v%04x_k%02x(base_SBIW): vd = 0x%x vk = 0x%x def fail(self,s): - raise SBIW_r%02d_v%04x_k%02x_TestFail, s + raise SBIW_r%02d_v%04x_k%02x_TestFail(s) """ # reg val, k val (0x00 <= k <= 0x3f) @@ -115,4 +115,4 @@ for d in range(24,32,2): for vd,vk in vals: args = (d,vd,vk)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_SBRC.py b/regress/test_opcodes/test_SBRC.py index 804d5b7..7feb658 100644 --- a/regress/test_opcodes/test_SBRC.py +++ b/regress/test_opcodes/test_SBRC.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -84,7 +84,7 @@ class test_SBRC_r%02d_b%d_v%02x_ni%d(base_SBRC): v = %d ni = %d def fail(self,s): - raise SBRC_r%02d_b%d_v%02x_ni%d_TestFail, s + raise SBRC_r%02d_b%d_v%02x_ni%d_TestFail(s) """ # @@ -97,4 +97,4 @@ for d in range(32): for ni in (16,32): # is next insn 16 or 32 bits args = (d,b,v,ni)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_SBRS.py b/regress/test_opcodes/test_SBRS.py index 6d68568..8e69ed9 100644 --- a/regress/test_opcodes/test_SBRS.py +++ b/regress/test_opcodes/test_SBRS.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -84,7 +84,7 @@ class test_SRBS_r%02d_b%d_v%02x_ni%d(base_SRBS): v = %d ni = %d def fail(self,s): - raise SRBS_r%02d_b%d_v%02x_ni%d_TestFail, s + raise SRBS_r%02d_b%d_v%02x_ni%d_TestFail(s) """ # @@ -97,4 +97,4 @@ for d in range(32): for ni in (16,32): # is next insn 16 or 32 bits args = (d,b,v,ni)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_STD_Y.py b/regress/test_opcodes/test_STD_Y.py index 965ed0f..6c0c737 100644 --- a/regress/test_opcodes/test_STD_Y.py +++ b/regress/test_opcodes/test_STD_Y.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -82,7 +82,7 @@ class test_STD_Y_r%02d_Y%04x_q%02x_v%02x(base_STD_Y): q = 0x%x Vd = 0x%x def fail(self,s): - raise STD_Y_r%02d_Y%04x_q%02x_v%02x_TestFail, s + raise STD_Y_r%02d_Y%04x_q%02x_v%02x_TestFail(s) """ # @@ -95,4 +95,4 @@ for d in range(0,32): for v in (0xaa, 0x55): args = (d,y,q,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_STD_Z.py b/regress/test_opcodes/test_STD_Z.py index f1ab30d..4d698a5 100644 --- a/regress/test_opcodes/test_STD_Z.py +++ b/regress/test_opcodes/test_STD_Z.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -82,7 +82,7 @@ class test_STD_Z_r%02d_Z%04x_q%02x_v%02x(base_STD_Z): q = 0x%x Vd = 0x%x def fail(self,s): - raise STD_Z_r%02d_Z%04x_q%02x_v%02x_TestFail, s + raise STD_Z_r%02d_Z%04x_q%02x_v%02x_TestFail(s) """ # @@ -95,4 +95,4 @@ for d in range(0,32): for v in (0xaa, 0x55): args = (d,z,q,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_STS.py b/regress/test_opcodes/test_STS.py index cf2cbc0..0aec124 100644 --- a/regress/test_opcodes/test_STS.py +++ b/regress/test_opcodes/test_STS.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -77,7 +77,7 @@ class test_STS_r%02d_k%04x_v%02x(base_STS): k = 0x%x v = 0x%x def fail(self,s): - raise STS_r%02d_k%04x_v%02x_TestFail, s + raise STS_r%02d_k%04x_v%02x_TestFail(s) """ # @@ -89,4 +89,4 @@ for d in range(0,32): for v in (0xaa, 0x55): args = (d,k,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_ST_X.py b/regress/test_opcodes/test_ST_X.py index a880ad3..5e1165c 100644 --- a/regress/test_opcodes/test_ST_X.py +++ b/regress/test_opcodes/test_ST_X.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -79,7 +79,7 @@ class test_ST_X_r%02d_X%04x_v%02x(base_ST_X): X = 0x%x Vd = 0x%x def fail(self,s): - raise ST_X_r%02d_X%04x_v%02x_TestFail, s + raise ST_X_r%02d_X%04x_v%02x_TestFail(s) """ # @@ -91,4 +91,4 @@ for d in range(0,32): for v in (0xaa, 0x55): args = (d,x,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_ST_X_decr.py b/regress/test_opcodes/test_ST_X_decr.py index da78a3c..c040785 100644 --- a/regress/test_opcodes/test_ST_X_decr.py +++ b/regress/test_opcodes/test_ST_X_decr.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -81,7 +81,7 @@ class test_ST_X_decr_r%02d_X%04x_v%02x(base_ST_X_decr): X = 0x%x Vd = 0x%x def fail(self,s): - raise ST_X_decr_r%02d_X%04x_v%02x_TestFail, s + raise ST_X_decr_r%02d_X%04x_v%02x_TestFail(s) """ # @@ -90,9 +90,9 @@ class test_ST_X_decr_r%02d_X%04x_v%02x(base_ST_X_decr): # Operation is undefined for d = 26 and d = 27. # code = '' -for d in range(0,26)+range(28,32): +for d in list(range(0,26))+list(range(28,32)): for x in (0x20f, 0x2ff): for v in (0xaa, 0x55): args = (d,x,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_ST_X_incr.py b/regress/test_opcodes/test_ST_X_incr.py index 3b2398e..15038fd 100644 --- a/regress/test_opcodes/test_ST_X_incr.py +++ b/regress/test_opcodes/test_ST_X_incr.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -80,7 +80,7 @@ class test_ST_X_incr_r%02d_X%04x_v%02x(base_ST_X_incr): X = 0x%x Vd = 0x%x def fail(self,s): - raise ST_X_incr_r%02d_X%04x_v%02x_TestFail, s + raise ST_X_incr_r%02d_X%04x_v%02x_TestFail(s) """ # @@ -89,9 +89,9 @@ class test_ST_X_incr_r%02d_X%04x_v%02x(base_ST_X_incr): # Operation is undefined for d = 26 and d = 27. # code = '' -for d in range(0,26)+range(28,32): +for d in list(range(0,26))+list(range(28,32)): for x in (0x20f, 0x2ff): for v in (0xaa, 0x55): args = (d,x,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_ST_Y_decr.py b/regress/test_opcodes/test_ST_Y_decr.py index 57e2711..8d1669e 100644 --- a/regress/test_opcodes/test_ST_Y_decr.py +++ b/regress/test_opcodes/test_ST_Y_decr.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -81,7 +81,7 @@ class test_ST_Y_decr_r%02d_Y%04x_v%02x(base_ST_Y_decr): Y = 0x%x Vd = 0x%x def fail(self,s): - raise ST_Y_decr_r%02d_Y%04x_v%02x_TestFail, s + raise ST_Y_decr_r%02d_Y%04x_v%02x_TestFail(s) """ # @@ -90,9 +90,9 @@ class test_ST_Y_decr_r%02d_Y%04x_v%02x(base_ST_Y_decr): # Operation is undefined for d = 28 and d = 29. # code = '' -for d in range(0,28)+range(30,32): +for d in list(range(0,28))+list(range(30,32)): for x in (0x20f, 0x2ff): for v in (0xaa, 0x55): args = (d,x,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_ST_Y_incr.py b/regress/test_opcodes/test_ST_Y_incr.py index e6ed9fd..4688c61 100644 --- a/regress/test_opcodes/test_ST_Y_incr.py +++ b/regress/test_opcodes/test_ST_Y_incr.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -80,7 +80,7 @@ class test_ST_Y_incr_r%02d_Y%04x_v%02x(base_ST_Y_incr): Y = 0x%x Vd = 0x%x def fail(self,s): - raise ST_Y_incr_r%02d_Y%04x_v%02x_TestFail, s + raise ST_Y_incr_r%02d_Y%04x_v%02x_TestFail(s) """ # @@ -89,9 +89,9 @@ class test_ST_Y_incr_r%02d_Y%04x_v%02x(base_ST_Y_incr): # Operation is undefined for d = 28 and d = 29. # code = '' -for d in range(0,28)+range(30,32): +for d in list(range(0,28))+list(range(30,32)): for x in (0x20f, 0x2ff): for v in (0xaa, 0x55): args = (d,x,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_ST_Z_decr.py b/regress/test_opcodes/test_ST_Z_decr.py index d146fd0..dcf39c1 100644 --- a/regress/test_opcodes/test_ST_Z_decr.py +++ b/regress/test_opcodes/test_ST_Z_decr.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -81,7 +81,7 @@ class test_ST_Z_decr_r%02d_Z%04x_v%02x(base_ST_Z_decr): Z = 0x%x Vd = 0x%x def fail(self,s): - raise ST_Z_decr_r%02d_Z%04x_v%02x_TestFail, s + raise ST_Z_decr_r%02d_Z%04x_v%02x_TestFail(s) """ # @@ -95,4 +95,4 @@ for d in range(0,30): for v in (0xaa, 0x55): args = (d,x,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_ST_Z_incr.py b/regress/test_opcodes/test_ST_Z_incr.py index 9548ee9..05e961c 100644 --- a/regress/test_opcodes/test_ST_Z_incr.py +++ b/regress/test_opcodes/test_ST_Z_incr.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -80,7 +80,7 @@ class test_ST_Z_incr_r%02d_Z%04x_v%02x(base_ST_Z_incr): Z = 0x%x Vd = 0x%x def fail(self,s): - raise ST_Z_incr_r%02d_Z%04x_v%02x_TestFail, s + raise ST_Z_incr_r%02d_Z%04x_v%02x_TestFail(s) """ # @@ -94,4 +94,4 @@ for d in range(0,30): for v in (0xaa, 0x55): args = (d,x,v)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_SUB.py b/regress/test_opcodes/test_SUB.py index 278c2c5..2e02b45 100644 --- a/regress/test_opcodes/test_SUB.py +++ b/regress/test_opcodes/test_SUB.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -97,7 +97,7 @@ class test_SUB_rd%02d_vd%02x_rr%02d_vr%02x(base_SUB): Rr = %d Vr = 0x%x def fail(self,s): - raise SUB_rd%02d_vd%02x_rr%02d_vr%02x_TestFail, s + raise SUB_rd%02d_vd%02x_rr%02d_vr%02x_TestFail(s) """ # @@ -129,4 +129,4 @@ for d in range(2,32,4): for vd,vr in vals: args = (d,vd,d,vd)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_SUBI.py b/regress/test_opcodes/test_SUBI.py index 41b814a..28a57a4 100644 --- a/regress/test_opcodes/test_SUBI.py +++ b/regress/test_opcodes/test_SUBI.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -95,7 +95,7 @@ class test_SUBI_r%02d_v%02x_k%02x(base_SUBI): Vd = 0x%x Vk = 0x%x def fail(self,s): - raise SUBI_r%02d_v%02x_k%02x_TestFail, s + raise SUBI_r%02d_v%02x_k%02x_TestFail(s) """ # @@ -120,4 +120,4 @@ for d in range(16,32): args = (d,vd,vk)*4 code += template % args -exec code +exec(code) diff --git a/regress/test_opcodes/test_SWAP.py b/regress/test_opcodes/test_SWAP.py index f57ab73..3c7d64e 100644 --- a/regress/test_opcodes/test_SWAP.py +++ b/regress/test_opcodes/test_SWAP.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python3 ############################################################################### # # simulavr - A simulator for the Atmel AVR family of microcontrollers. @@ -62,7 +62,7 @@ class SWAP_r%02d_TestFail(SWAP_TestFail): pass class test_SWAP_r%02d(base_SWAP): reg = %d def fail(self,s): - raise SWAP_r%02d_TestFail, s + raise SWAP_r%02d_TestFail(s) """ # @@ -71,4 +71,4 @@ class test_SWAP_r%02d(base_SWAP): code = '' for i in range(32): code += template % (i,i,i,i) -exec code +exec(code) -- 2.24.0