// Verilog Behavioral Simulator
// Copyright (C) 1995-1997 Lay Hoon Tho, Jimen Ching
//
// This file is part of the Verilog Behavioral Simulator package.
// See the file COPYRIGHT for copyright and disclaimer information.
// See the file COPYING for the licensing terms and conditions.
// See the file CONTRIBUTORS for a list of contributing authors.
//
// random.cc

#include "stmt/random.h"

sysfunc_random::sysfunc_random()
	: _name("$random")
	{}

sysfunc_random::ostream_type &
sysfunc_random::display(ostream_type &s) const
	{ s << _name; return s; }

void
sysfunc_random::setup(const setup_type &setup)
	{ setup(this); }

bool
sysfunc_random::trigger(const trigger_type &trigger)
	{ return trigger(this); }