gas/ChangeLog | 10 10 + 0 - 0 !
gas/testsuite/gas/riscv/alias-csr.d | 23 23 + 0 - 0 !
gas/testsuite/gas/riscv/alias-csr.s | 14 14 + 0 - 0 !
gas/testsuite/gas/riscv/no-aliases-csr.d | 23 23 + 0 - 0 !
gas/testsuite/gas/riscv/priv-reg.d | 2 1 + 1 - 0 !
opcodes/ChangeLog | 8 8 + 0 - 0 !
opcodes/riscv-opc.c | 32 16 + 16 - 0 !
7 files changed, 95 insertions(+), 17 deletions(-)

 risc-v: fix minor issues with fp csr instructions.

	Mel Chen <mel.chen@sifive.com>
	gas/
	* testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access
	alias instructions.
	* testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with
	-Mno-aliases.
	* testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s.
	* testsuite/gas/riscv/priv-reg.d: Update.
	opcodes/
	* riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
	fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
	* riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
	fscsr.

bfd/ChangeLog | 5 5 + 0 - 0 !
bfd/elfnn-riscv.c | 9 7 + 2 - 0 !
2 files changed, 12 insertions(+), 2 deletions(-)

 risc-v: fix lui relax failure with relro.

	bfd/ChangeLog
	Ilia Diachkov  <ilia.diachkov@optimitech.com>
	* elfnn-riscv.c (_bfd_riscv_relax_lui): Set lui relax safety area to
	two pages in relro presence.

bfd/ChangeLog | 6 6 + 0 - 0 !
bfd/elfnn-riscv.c | 16 14 + 2 - 0 !
ld/ChangeLog | 7 7 + 0 - 0 !
ld/testsuite/ld-riscv-elf/c-lui-2.d | 19 19 + 0 - 0 !
ld/testsuite/ld-riscv-elf/c-lui-2.ld | 6 6 + 0 - 0 !
ld/testsuite/ld-riscv-elf/c-lui-2.s | 12 12 + 0 - 0 !
ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp | 1 1 + 0 - 0 !
7 files changed, 65 insertions(+), 2 deletions(-)

 risc-v: fix lui relaxation issue with code at address 0.

This fixes a problem originally reported at
    https://github.com/riscv/riscv-binutils-gdb/issues/173

If you have code linked at address zero, you can have a lui instruction
loading a value 0x800 which gets relaxed to a c.lui which is valid (c.lui 0x1
followed by addi -0x800).  Relaxation can reduce the value below 0x800 at which
point the c.lui 0x0 is no longer valid.  We can fix this by converting the
c.lui to a c.li which can load 0.

	bfd/
	* elfnn-riscv.c (perform_relocation) <R_RISCV_RVC_LUI>: If
	RISCV_CONST_HIGH_PART (value) is zero, then convert c.lui instruction
	to c.li instruction, and use ENCODE_RVC_IMM to set value.

	ld/
	* testsuite/ld-riscv-elf/c-lui-2.d: New.
	* testsuite/ld-riscv-elf/c-lui-2.ld: New.
	* testsuite/ld-riscv-elf/c-lui-2.s: New.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run the c-lui-2 test.

gas/testsuite/gas/riscv/priv-reg.d | 4 4 + 0 - 0 !
gas/testsuite/gas/riscv/priv-reg.s | 6 6 + 0 - 0 !
include/opcode/riscv-opc.h | 19 19 + 0 - 0 !
3 files changed, 29 insertions(+)

 add support for sifive clic csrs.

bfd/ChangeLog | 6 6 + 0 - 0 !
bfd/elfnn-riscv.c | 17 10 + 7 - 0 !
2 files changed, 16 insertions(+), 7 deletions(-)

 risc-v: fix a gp relaxation reloc overflow error.

This was broken when I changed how we compute the value for the gp register.
It used to be computed inside the sdata section.  Now it is computed at the
end which makes it an abs section symbol.  There is code that tries to use
the alignment of the section that the gp value is in, but this does not work
if it is in the abs section, as the abs section has alignment of 1 byte.
There are people using alternative linker scripts that still define it in the
sdata section, so the code is still useful.  Thus adding a check to disable
this when gp is in the abs section.

	bfd/
	* elfnn-riscv.c (_bfd_riscv_relax_lui): Add check to exclude abs
	section when setting max_alignment.  Update comment.
	(_bfd_riscv_relax_pc): Likewise.

bfd/ChangeLog | 5 5 + 0 - 0 !
bfd/elfnn-riscv.c | 5 4 + 1 - 0 !
2 files changed, 9 insertions(+), 1 deletion(-)

 risc-v: force linker error exit after unresolvable reloc.

This was noticed while trying to test the compiler -msave-restore support.
Putting non-pic code in a shared library gives a linker error, but doesn't
stop the build.

rohan:2030$ cat libtmp.c
extern int sub2 (int);
int sub (int i) { return sub2 (i + 10); }
rohan:2031$ cat libtmp2.c
extern int sub (int);
int sub2 (int i) { return sub (i + 10); }
rohan:2032$ riscv64-unknown-linux-gnu-gcc --shared -o libtmp.so libtmp.c
rohan:2033$ riscv64-unknown-linux-gnu-gcc --shared -o libtmp2.so libtmp2.c libtmp.so
/home/jimw/FOSS/install-riscv64/lib/gcc/riscv64-unknown-linux-gnu/8.3.0/../../../../riscv64-unknown-linux-gnu/bin/ld: /tmp/cctrsIBe.o(.text+0x18): unresolvable R_RISCV_CALL relocation against symbol `sub'
rohan:2034$ echo $?
0
rohan:2035$ ls -lt libtmp2.so
-rwxr-xr-x 1 jimw jimw 6912 Aug 30 14:32 libtmp2.so
rohan:2036$

The patch fixes this by forcing a linker error.  I now get this.

ohan:2059$ sh tmp.script
/home/jimw/FOSS/BINUTILS/X-riscv64-linux/ld/ld-new: libtmp2.o(.text+0x18): unresolvable R_RISCV_CALL relocation against symbol `sub'
/home/jimw/FOSS/BINUTILS/X-riscv64-linux/ld/ld-new: final link failed: bad value
rohan:2060$ echo $?
1
rohan:2061$ ls -lt libtmp2.so
ls: cannot access 'libtmp2.so': No such file or directory

	bfd/
	* elfnn-riscv.c (riscv_elf_relocate_section): For unresolvable reloc
	error, call bfd_set_error, set ret to FALSE, and goto out label.

bfd/ChangeLog | 6 6 + 0 - 0 !
bfd/elfnn-riscv.c | 14 14 + 0 - 0 !
2 files changed, 20 insertions(+)

 risc-v: fix linker problems with tls copy relocs.

The linker doesn't allocate memory space for sections that are only SEC_ALLOC
and SEC_THREAD_LOCAL.  See the IS_TBSS test in ld/ldlang.c.  So we need to
pretend that .tdata.dyn sections have contents to get the right result.  It
will be marked this way anyways if there is a .tdata section to merge with.

	bfd/
	PR 23825
	* elfnn-riscv.c (riscv_elf_create_dynamic_sections): Add SEC_LOAD,
	SEC_DATA, and SEC_HAS_CONTENTS to .tdata.dyn section.

gas/testsuite/gas/riscv/cache-control.d | 15 15 + 0 - 0 !
gas/testsuite/gas/riscv/cache-control.s | 7 7 + 0 - 0 !
include/opcode/riscv-opc.h | 10 10 + 0 - 0 !
opcodes/riscv-opc.c | 5 5 + 0 - 0 !
4 files changed, 37 insertions(+)

 support sifive specific cache control instructions.

There are three cache control instructions,
1. CFLUSH.D.L1   RS1
2. CDISCARD.D.L1 RS1
3. CFLUSH.I.L1

These instructions use the same funct3 0x0 [14:12].  CFLUSH.D.L1 use 0xfc000073
opcode (0xfc0 [31:20] + 0x0 [11:7] + SYSTEM OP [6:2] + 0x3 [1:0]) with optional
rs1.  CDISCARD.D.L1 use 0xfc200073 opcode (0xfc2 [31:20], ...) with optional
rs1.  CFLUSH.I.L1 use 0xfc100073 opcode.