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--- a/tpic.cc
+++ b/tpic.cc
@@ -438,13 +438,15 @@ TRegister TPic::Read(TData_Address addr)
TBool Page1 = Bit_Read(Regs.STATUS,STATUS_RP0);
if (addr == 0x00)
- if( (addr = Regs.FSR) == 0x00 )
- return 0x00;
- else
- {
- Page1 = (addr & 0x80) != 0x00;
- addr &= 0x7F;
- }
+ {
+ if( (addr = Regs.FSR) == 0x00 )
+ return 0x00;
+ else
+ {
+ Page1 = (addr & 0x80) != 0x00;
+ addr &= 0x7F;
+ }
+ }
switch (addr)
{
@@ -575,26 +577,28 @@ void TPic::Write(TData_Address addr, TRe
break;
case 0x07: break;
- case f_EEDATA: if (Page1) {
+
+ case f_EEDATA:
+ if (Page1) {
- if (Bit_Read(Regs.EECON1,EECON1_WREN) == 0)
- data=Bit_Clear(data,EECON1_WR);
+ if (Bit_Read(Regs.EECON1,EECON1_WREN) == 0)
+ data=Bit_Clear(data,EECON1_WR);
- if (Bit_Read(data,EECON1_WR) && (EEPROM_Write_Status==-1)) {
- EEPROM_Write_Data=Regs.EEDATA;
- EEPROM_Write_Addr=Regs.EEADR;
- EEPROM_Write_Status=(unsigned long int) (0.010*(Clock_Frequency/4.0)); /* 10ms */
- }
-
- if (Bit_Read(data,EECON1_RD)) {
- Regs.EEDATA=EEPROM.Mem[Regs.EEADR & 0x7F];
- data=Bit_Clear(data,EECON1_RD);
- }
- Regs.EECON1=data & 0x1F;
- }
- else
- Regs.EEDATA=data;
- break;
+ if (Bit_Read(data,EECON1_WR) && (EEPROM_Write_Status==-1)) {
+ EEPROM_Write_Data=Regs.EEDATA;
+ EEPROM_Write_Addr=Regs.EEADR;
+ EEPROM_Write_Status=(unsigned long int) (0.010*(Clock_Frequency/4.0)); /* 10ms */
+ }
+
+ if (Bit_Read(data,EECON1_RD)) {
+ Regs.EEDATA=EEPROM.Mem[Regs.EEADR & 0x7F];
+ data=Bit_Clear(data,EECON1_RD);
+ }
+ Regs.EECON1=data & 0x1F;
+ }
+ else
+ Regs.EEDATA=data;
+ break;
case f_EEADR:
if (Page1) {
@@ -926,10 +930,12 @@ void TPic::Clock()
Reset=FALSE;
if (WDT_Fuse && Update_WDT())
+ {
if (Sleep)
Reset_WDT_Sleep();
else
Reset_WDT_Normal();
+ }
if (Sleep && (INT_Event() || RB_Change_Event() || (EEPROM_Write_Status==1)))
Reset_Int_Wake_Up();
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