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From e2d680a06acc7a02ec9a784597760a0a437119b4 Mon Sep 17 00:00:00 2001
From: Adam Borowski <kilobyte@angband.pl>
Date: Wed, 19 Jun 2019 01:41:22 +0200
Subject: [PATCH] Fix SIGILL on dcache flushes on arm64.
Only "dc cvau" was supported; the list is:
* cvau: to Point of Unification (icache = dcache, usu. L2)
* cvac: to Point of Coherence (all hardware that can access memory)
* cvap: to Point of Persistence (v8.2, usu. memory controller)
* cvadp: to Point of Deep Persistence (v8.5)
* civac: cvac + invalidate
For tools other than cachegrind, we don't care about which exact flush
is used; this patch doesn't yet teach cachegrind that -- but at least
there's no crash, and all other tools work right.
---
VEX/priv/guest_arm64_toIR.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
--- a/VEX/priv/guest_arm64_toIR.c
+++ b/VEX/priv/guest_arm64_toIR.c
@@ -7335,12 +7335,19 @@
return True;
}
+ /* ------------------ DC_CVAC ------------------ */
/* ------------------ DC_CVAU ------------------ */
- /* D5 0B 7B 001 Rt dc cvau, rT
+ /* ------------------ DC_CVAP ------------------ */
+ /* ------------------ DC_CVADP ----------------- */
+ /* ------------------ DC_CIVAC ----------------- */
+ /* D5 0B 7A 001 Rt dc cvac, rT
+ D5 0B 7B 001 Rt dc cvau, rT
+ D5 0B 7C 001 Rt dc cvap, rT
+ D5 0B 7D 001 Rt dc cvadp, rT
D5 0B 7E 001 Rt dc civac, rT
+ 78, 79 and 7F are unassigned -- speculate they'll also be dcache flushes.
*/
- if ( (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7B20
- || (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7E20) {
+ if ((INSN(31,0) & 0xFFFFF8E0) == 0xD50B7820) {
/* Exactly the same scheme as for IC IVAU, except we observe the
dMinLine size, and request an Ijk_FlushDCache instead of
Ijk_InvalICache. */
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