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# /*------------------------------------------------------------\
# | |
# | File : README |
# | |
# | Author : Jacomme Ludovic |
# | |
# \------------------------------------------------------------*/
This directory contains the VHDL description of a 16 bits adder-accumulator and
the associated stimuli file, and also a configuration file for IO
placement (used during the Place and Route step).
The Makefile set environment variables properly and run Alliance tools,
following each step of the design flow from VHDL up to real layout in a
pseudo 0.35 techno.
copy the folder "addaccu16" to any writable folder of your choice and type:
$ make
The main targets of the makefile are listed below (following the design flow).
#
# RTL SYNTHESIS
#
addaccu.vbe : Run the VHDL analyzer (VASY) on the VHDL description
(addaccu.vhdl) and transform it into a boolean network (addaccu.vbe).
res_vasy_1.pat : Run the VHDL simulator (ASIMUT) on addaccu.vbe using the pattern/stimuli file
addaccu.pat. This step checks if the addaccu.vbe description is working properly.
xpat_vasy : Run the graphical waveform viewer (XPAT) on the resulting file res_vasy_1.pat
addaccu_o.vbe : Run the Boolean network optimizer (BOOM) on the addaccu.vbe and
factorize/minimize boolean equations, and generate a new description
addaccu_o.vbe.
addaccu_o.vst : Run the boolean mapper (BOOG) on the optimized description addaccu_o.vbe
and using the sxlib standard cell library, map all boolean nodes to
an equivalent set of standard cells.
xsch_addaccu_o : Run the schematic viewer (XSCH) on the structural netlist addaccu_o.vst
addaccu.vst : Run the net optimizer (LOON) on the structural description addaccu_o.vst.
It inserts buffers on the critical path using the sxlib standard cell library
and generates a new structural netlist addaccu.vst .
xsch_addaccu : Run the schematic viewer (XSCH) on the bufferized netlist addaccu.vst .
The critical path would be displayed in red color.
res_synth_1.pat : Run the VHDL simulator (ASIMUT) on the structural description addaccu.vst using
the pattern/stimuli file addaccu.pat and the behavioral description (.VBE) of each
cells of the standard cell library (sxlib).
This step checks if the addaccu.vst description is still working properly.
#
# PLACE AND ROUTE
#
addaccu_p.ap : Run the placement tool (OCP) on the structural description addaccu.vst.
It generates a physical placement file (addaccu_p.ap) that would be given
to the router (NERO).
graal_addaccu_p : Launch the physical layout editor (GRAAL) and display the result of the placement tool
(addaccu_p.ap).
addaccu.ap : Run the router tool (NERO). Given the structural description addaccu.vst, the
placement file (addaccu_p) and the position of external connectors (addaccu.ioc)
the router generates a physical view (addaccu.ap) where all nets have been routed.
graal_addaccu : Launch the physical layout editor (GRAAL) and display the result of the router tool
(addaccu.ap).
#
# Netlist / parasitics extraction
#
addaccu_e.al : Run the hierarchical netlist extractor (COUGAR) and extracts the netlist with parasitic
informations (physical parameters are taken in the techno-035.rds file).
This tool generates the extracted netlist addaccu_e.al
xsch_addaccu_e : Run the schematic viewer (XSCH) on the hierarchical extracted netlist (addaccu_e.al).
addaccu_et.al : Run the netlist extractor (COUGAR) and extracts the netlist at the transistor level
with parasitics informations (addaccu_et.al).
xsch_addaccu_et : Run the schematic viewer (XSCH) on the extracted transistor netlist (addaccu_et.al).
#
# Netlists comparison
#
lvx.done : Run the gate netlist comparator (LVX) and checks if the extracted netlist is the same as
the structural structural netlist. This step checks if the place and route phases are ok.
#
# Design rule checker
#
druc.done : Launch the design rule checker on the layout generated by the router (addaccu.ap). The design
rules are specified in the RDS file (techno-symb.rds).
#
# Symbolic layout to real layout
#
addaccu.cif : Transforms the symbolic layout in lambda (addaccu.ap) in a 0.35u real layout using the tool S2R.
It generates a CIF file (addaccu.cif).
dreal_addaccu : Launch the real layout editor (DREAL) and display the result of S2R
(addaccu.cif).
#
# Clean
The clean target remove all generated files ...
|
