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entity rome is
port (
address : in bit_vector (5 downto 0);
e_n : in bit;
data : out mux_vector (31 downto 0) bus;
vdd : in bit;
vss : in bit);
end rome;
architecture VBE of rome is
signal rom_out : bit_vector (31 downto 0);
begin
write_out : block (e_n = '0')
begin
data <= guarded rom_out;
end block;
with address (5 downto 0) select
rom_out <=
X"afdd0000" when B"100000",
X"afdc0004" when B"100001",
X"201c003c" when B"100010",
X"401d6800" when B"100011",
X"00000021" when B"100100",
X"03bce824" when B"100101",
X"201b0020" when B"100110",
X"17bb0008" when B"100111",
X"00000021" when B"101000",
X"8fdd0000" when B"101001",
X"8fdc0004" when B"101010",
X"401f7000" when B"101011",
X"00000021" when B"101100",
X"23ff0008" when B"101101",
X"03e00008" when B"101110",
X"42000010" when B"101111",
X"401f7000" when B"110000",
X"00000021" when B"110001",
X"23ff0004" when B"110010",
X"03e00008" when B"110011",
X"42000010" when B"110100",
X"00000000" when others;
end;
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