1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity calcul is
port ( ck : in std_logic;
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
res : out std_logic_vector(7 downto 0);
ra_eq_rb : out std_logic;
ra_inf_rb : out std_logic;
wres_ra : in std_logic;
wres_rb : in std_logic;
ra_sub_rb : in std_logic;
s_read : in std_logic );
end calcul;
architecture behavioral of calcul is
signal RA : std_logic_vector(7 downto 0);
signal RB : std_logic_vector(7 downto 0);
signal RES_int : std_logic_vector(7 downto 0);
begin
process( ck )
begin
if ( rising_edge( ck ) )
then if ( s_read = '1' ) then RA <= A;
elsif ( wres_ra = '1' ) then RA <= RES_int;
end if;
end if;
end process;
process( ck )
begin
if ( rising_edge( ck ) )
then if ( s_read = '1' ) then RB <= B;
elsif ( wres_rb = '1' ) then RB <= RES_int;
end if;
end if;
end process;
process( RA, RB, ra_sub_rb )
begin
if ( ra_sub_rb = '1' )
then RES_int <= std_logic_vector(unsigned(RA) - unsigned(RB));
else RES_int <= std_logic_vector(unsigned(RB) - unsigned(RA));
end if;
end process;
RES <= RA;
process( RA, RB )
begin
if ( unsigned(RA) < unsigned( RB ) )
then ra_inf_rb <= '1';
else ra_inf_rb <= '0';
end if;
end process;
process( RA, RB )
begin
if ( RA = RB )
then ra_eq_rb <= '1';
else ra_eq_rb <= '0';
end if;
end process;
end behavioral;
|
