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entity sr64_8a is
port (
E_N : in bit ;
W_N : in bit ;
DAT : inout mux_vector ( 7 downto 0) bus;
ADR : in bit_vector ( 5 downto 0) ;
VDD : in bit ;
VSS : in bit
);
end sr64_8a;
architecture STRUCTURAL of sr64_8a is
component sr64_1a
port (
E_N : in bit ;
W_N : in bit ;
D : in bit ;
Q : out mux_bit bus;
A : in bit_vector (5 downto 0) ;
VDD : in bit ;
VSS : in bit
);
end component;
begin
bit7 : sr64_1a
port map (
E_N => E_N ,
W_N => W_N ,
D => DAT (7) ,
Q => DAT (7) ,
A => ADR ,
VDD => VDD ,
VSS => VSS
);
bit6 : sr64_1a
port map (
E_N => E_N ,
W_N => W_N ,
D => DAT (6) ,
Q => DAT (6) ,
A => ADR ,
VDD => VDD ,
VSS => VSS
);
bit5 : sr64_1a
port map (
E_N => E_N ,
W_N => W_N ,
D => DAT (5) ,
Q => DAT (5) ,
A => ADR ,
VDD => VDD ,
VSS => VSS
);
bit4 : sr64_1a
port map (
E_N => E_N ,
W_N => W_N ,
D => DAT (4) ,
Q => DAT (4) ,
A => ADR ,
VDD => VDD ,
VSS => VSS
);
bit3 : sr64_1a
port map (
E_N => E_N ,
W_N => W_N ,
D => DAT (3) ,
Q => DAT (3) ,
A => ADR ,
VDD => VDD ,
VSS => VSS
);
bit2 : sr64_1a
port map (
E_N => E_N ,
W_N => W_N ,
D => DAT (2) ,
Q => DAT (2) ,
A => ADR ,
VDD => VDD ,
VSS => VSS
);
bit1 : sr64_1a
port map (
E_N => E_N ,
W_N => W_N ,
D => DAT (1) ,
Q => DAT (1) ,
A => ADR ,
VDD => VDD ,
VSS => VSS
);
bit0 : sr64_1a
port map (
E_N => E_N ,
W_N => W_N ,
D => DAT (0) ,
Q => DAT (0) ,
A => ADR ,
VDD => VDD ,
VSS => VSS
);
end ;
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