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# Generated by Yosys 0.5+ 292 (git sha1 6f9a6fd, clang 6.1.0 -fPIC -Os)
.model top
.inputs REFERENCECLK EXTFEEDBACK DYNAMICDELAY[0] DYNAMICDELAY[1] DYNAMICDELAY[2] DYNAMICDELAY[3] DYNAMICDELAY[4] DYNAMICDELAY[5] DYNAMICDELAY[6] DYNAMICDELAY[7] BYPASS RESETB LATCHINPUTVALUE SDI SCLK
.outputs PLLOUTCORE[0] PLLOUTCORE[1] PLLOUTGLOBAL[0] PLLOUTGLOBAL[1] LOCK SDO
.names $false
.names $true
1
.names $undef
.gate SB_PLL40_2F_CORE BYPASS=BYPASS DYNAMICDELAY[0]=DYNAMICDELAY[0] DYNAMICDELAY[1]=DYNAMICDELAY[1] DYNAMICDELAY[2]=DYNAMICDELAY[2] DYNAMICDELAY[3]=DYNAMICDELAY[3] DYNAMICDELAY[4]=DYNAMICDELAY[4] DYNAMICDELAY[5]=DYNAMICDELAY[5] DYNAMICDELAY[6]=DYNAMICDELAY[6] DYNAMICDELAY[7]=DYNAMICDELAY[7] EXTFEEDBACK=EXTFEEDBACK LATCHINPUTVALUE=LATCHINPUTVALUE LOCK=LOCK PLLOUTCOREA=PLLOUTCORE[0] PLLOUTCOREB=PLLOUTCORE[1] PLLOUTGLOBALA=PLLOUTGLOBAL[0] PLLOUTGLOBALB=PLLOUTGLOBAL[1] REFERENCECLK=REFERENCECLK RESETB=RESETB SCLK=SCLK SDI=SDI SDO=SDO
.attr src "sb_pll40_2f_core.v:17"
.param DELAY_ADJUSTMENT_MODE_FEEDBACK "FIXED"
.param DELAY_ADJUSTMENT_MODE_RELATIVE "FIXED"
.param DIVF 0000000
.param DIVQ 001
.param DIVR 0000
.param ENABLE_ICEGATE_PORTA 0
.param ENABLE_ICEGATE_PORTB 0
.param FDA_FEEDBACK 1111
.param FDA_RELATIVE 1111
.param FEEDBACK_PATH "DELAY"
.param FILTER_RANGE 000
.param PLLOUT_SELECT_PORTA "GENCLK"
.param PLLOUT_SELECT_PORTB "GENCLK"
.param SHIFTREG_DIV_MODE 0
.param TEST_MODE 0
.end
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