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/*
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define LIT_CAPACITY 239
#define MID_CAPACITY 686
#define BIG_CAPACITY 1024
#define MHU_TX_COMPAT "arm,mhuv3"
#define MHU_TX_INT_NAME ""
#define MHU_RX_COMPAT "arm,mhuv3"
#define MHU_OFFSET 0x10000
#define MHU_MBOX_CELLS 3
#define MHU_RX_INT_NUM 300
#define MHU_RX_INT_NAME "combined"
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000
#if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000
#define DPU_IRQ 579
#elif TARGET_FLAVOUR_FPGA
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#endif
#include "tc-base.dtsi"
/ {
cpus {
CPU2:cpu@200 {
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
};
CPU3:cpu@300 {
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
};
CPU6:cpu@600 {
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
};
CPU7:cpu@700 {
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
};
};
gic: interrupt-controller@GIC_CTRL_ADDR {
ppi-partitions {
ppi_partition_little: interrupt-partition-0 {
affinity = <&CPU0>, <&CPU1>;
};
ppi_partition_mid: interrupt-partition-1 {
affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
};
ppi_partition_big: interrupt-partition-2 {
affinity = <&CPU6>, <&CPU7>;
};
};
};
sram: sram@6000000 {
cpu_scp_scmi_p2a: scp-shmem@80 {
compatible = "arm,scmi-shmem";
reg = <0x80 0x80>;
};
};
firmware {
scmi {
mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>;
shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
};
};
};
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