1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
|
/*
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <platform_def.h>
#define MHU_TX_ADDR 46040000 /* hex */
#define MHU_RX_ADDR 46140000 /* hex */
#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu"
#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu"
#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu"
#define ETHERNET_ADDR 18000000
#define ETHERNET_INT 109
#define SYS_REGS_ADDR 1c010000
#define MMC_ADDR 1c050000
#define MMC_INT_0 107
#define MMC_INT_1 108
#define RTC_ADDR 1c170000
#define RTC_INT 100
#define KMI_0_ADDR 1c060000
#define KMI_0_INT 197
#define KMI_1_ADDR 1c070000
#define KMI_1_INT 103
#define VIRTIO_BLOCK_ADDR 1c130000
#define VIRTIO_BLOCK_INT 204
#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"
#else
#include "tc-fpga.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
#include "tc3-4-base.dtsi"
/ {
cs-pmu@0 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
};
cs-pmu@1 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>;
};
cs-pmu@2 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>;
};
cs-pmu@3 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>;
};
spe-pmu-mid {
status = "okay";
};
spe-pmu-big {
status = "okay";
};
dsu-pmu {
compatible = "arm,dsu-pmu";
cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
};
ni-pmu {
compatible = "arm,ni-tower";
reg = <0x0 0x4f000000 0x0 0x4000000>;
};
#if TARGET_FLAVOUR_FVP
smmu_700: iommu@3f000000 {
status = "okay";
};
smmu_700_dpu: iommu@4002a00000 {
status = "okay";
};
#else
smmu_600: smmu@2ce00000 {
status = "okay";
};
#endif
dp0: display@DPU_ADDR {
#if TARGET_FLAVOUR_FVP
iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
<&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
#else /* TARGET_FLAVOUR_FPGA */
iommus = <&smmu_600 0>, <&smmu_600 1>, <&smmu_600 2>, <&smmu_600 3>,
<&smmu_600 4>, <&smmu_600 5>, <&smmu_600 6>, <&smmu_600 7>,
<&smmu_600 8>, <&smmu_600 9>;
#endif
};
gpu: gpu@2d000000 {
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "JOB", "MMU", "GPU";
#if TARGET_FLAVOUR_FVP
iommus = <&smmu_700 0x200>;
#endif
};
};
|
