File: x86-64-avx512er-rcigrne-intel.d

package info (click to toggle)
binutils-riscv64-unknown-elf 2.32.2019.08+dfsg-1
  • links: PTS, VCS
  • area: main
  • in suites: bullseye, sid
  • size: 413,812 kB
  • sloc: ansic: 2,327,452; asm: 982,944; exp: 218,246; cpp: 147,855; makefile: 63,075; sh: 33,816; yacc: 27,082; lisp: 15,389; perl: 6,480; xml: 5,239; ada: 5,117; python: 4,996; pascal: 3,266; lex: 2,272; cs: 879; f90: 535; sed: 334; awk: 165; objc: 134; fortran: 43
file content (32 lines) | stat: -rw-r--r-- 1,682 bytes parent folder | download | duplicates (25)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
#as: -mevexrcig=rne
#objdump: -dw -Mintel
#name: x86_64 AVX512ER rcig insns (Intel disassembly)
#source: x86-64-avx512er-rcig.s

.*: +file format .*


Disassembly of section \.text:

0+ <_start>:
[ 	]*[a-f0-9]+:[ 	]*62 02 7d 18 c8 f5[ 	]*vexp2ps zmm30,zmm29,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 fd 18 c8 f5[ 	]*vexp2pd zmm30,zmm29,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 7d 18 ca f5[ 	]*vrcp28ps zmm30,zmm29,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 fd 18 ca f5[ 	]*vrcp28pd zmm30,zmm29,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 15 10 cb f4[ 	]*vrcp28ss xmm30,xmm29,xmm28,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 95 10 cb f4[ 	]*vrcp28sd xmm30,xmm29,xmm28,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 7d 18 cc f5[ 	]*vrsqrt28ps zmm30,zmm29,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 fd 18 cc f5[ 	]*vrsqrt28pd zmm30,zmm29,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 15 10 cd f4[ 	]*vrsqrt28ss xmm30,xmm29,xmm28,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 95 10 cd f4[ 	]*vrsqrt28sd xmm30,xmm29,xmm28,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 7d 18 c8 f5[ 	]*vexp2ps zmm30,zmm29,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 fd 18 c8 f5[ 	]*vexp2pd zmm30,zmm29,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 7d 18 ca f5[ 	]*vrcp28ps zmm30,zmm29,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 fd 18 ca f5[ 	]*vrcp28pd zmm30,zmm29,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 15 10 cb f4[ 	]*vrcp28ss xmm30,xmm29,xmm28,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 95 10 cb f4[ 	]*vrcp28sd xmm30,xmm29,xmm28,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 7d 18 cc f5[ 	]*vrsqrt28ps zmm30,zmm29,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 fd 18 cc f5[ 	]*vrsqrt28pd zmm30,zmm29,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 15 10 cd f4[ 	]*vrsqrt28ss xmm30,xmm29,xmm28,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 02 95 10 cd f4[ 	]*vrsqrt28sd xmm30,xmm29,xmm28,\{sae\}
#pass