File: vr4120-2.d

package info (click to toggle)
binutils 2.31.1-12
  • links: PTS, VCS
  • area: main
  • in suites: buster
  • size: 307,644 kB
  • sloc: ansic: 1,161,122; asm: 638,494; cpp: 128,815; exp: 68,557; makefile: 55,828; sh: 22,360; yacc: 14,238; lisp: 13,272; perl: 2,111; ada: 1,681; lex: 1,652; pascal: 1,446; cs: 879; sed: 195; python: 154; xml: 95; awk: 25
file content (172 lines) | stat: -rw-r--r-- 3,323 bytes parent folder | download | duplicates (45)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
#objdump: -dz --prefix-addresses -m mips:4120
#as: -32 -march=vr4120 -mfix-vr4120
#name: MIPS vr4120 workarounds

.*: +file format .*mips.*

Disassembly of section .text:
.* <[^>]*> macc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> div	zero,a3,t0
.* <[^>]*> or	a0,a0,a1
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> div	zero,a3,t0
.* <[^>]*> or	a0,a0,a1
.* <[^>]*> macc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> divu	zero,a3,t0
.* <[^>]*> or	a0,a0,a1
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> divu	zero,a3,t0
.* <[^>]*> or	a0,a0,a1
.* <[^>]*> macc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> ddiv	zero,a3,t0
.* <[^>]*> or	a0,a0,a1
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> ddiv	zero,a3,t0
.* <[^>]*> or	a0,a0,a1
.* <[^>]*> macc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> ddivu	zero,a3,t0
.* <[^>]*> or	a0,a0,a1
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> ddivu	zero,a3,t0
.* <[^>]*> or	a0,a0,a1
.* <[^>]*> dmult	a0,a1
.* <[^>]*> nop
.* <[^>]*> dmult	a2,a3
.* <[^>]*> or	a0,a0,a1
.* <[^>]*> dmultu	a0,a1
.* <[^>]*> nop
.* <[^>]*> dmultu	a2,a3
.* <[^>]*> or	a0,a0,a1
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> dmacc	a2,a3,t0
.* <[^>]*> or	a0,a0,a1
.* <[^>]*> dmult	a0,a1
.* <[^>]*> nop
.* <[^>]*> dmacc	a2,a3,t0
.* <[^>]*> or	a0,a0,a1
.* <[^>]*> macc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> mtlo	a3
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> mtlo	a3
.* <[^>]*> macc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> mthi	a3
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> mthi	a3
#
# vr4181a_md1:
#
.* <[^>]*> macc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> mult	a0,a1
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> macc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> multu	a0,a1
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> macc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> dmult	a0,a1
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> macc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> dmultu	a0,a1
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> mult	a0,a1
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> multu	a0,a1
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> dmult	a0,a1
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> nop
.* <[^>]*> dmultu	a0,a1
.* <[^>]*> or	a0,a0,a1
#
# vr4181a_md4:
#
.* <[^>]*> dmult	a0,a1
.* <[^>]*> nop
.* <[^>]*> macc	a0,a1,a2
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> dmultu	a0,a1
.* <[^>]*> nop
.* <[^>]*> macc	a0,a1,a2
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> div	zero,a0,a1
.* <[^>]*> nop
.* <[^>]*> macc	a0,a1,a2
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> divu	zero,a0,a1
.* <[^>]*> nop
.* <[^>]*> macc	a0,a1,a2
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> ddiv	zero,a0,a1
.* <[^>]*> nop
.* <[^>]*> macc	a0,a1,a2
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> ddivu	zero,a0,a1
.* <[^>]*> nop
.* <[^>]*> macc	a0,a1,a2
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> dmult	a0,a1
.* <[^>]*> nop
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> dmultu	a0,a1
.* <[^>]*> nop
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> div	zero,a0,a1
.* <[^>]*> nop
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> divu	zero,a0,a1
.* <[^>]*> nop
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> ddiv	zero,a0,a1
.* <[^>]*> nop
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> or	a0,a0,a1
#
.* <[^>]*> ddivu	zero,a0,a1
.* <[^>]*> nop
.* <[^>]*> dmacc	a0,a1,a2
.* <[^>]*> or	a0,a0,a1
#...