1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
|
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS16 PC-relative relocation with addend 8 (n32)
#as: -n32
#source: mips16-pcrel-addend-8.s
.*: +file format .*mips.*
Disassembly of section \.text:
\.\.\.
[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468
[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468
[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468
[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468
[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x12345678
[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x12345678
[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x12345678
[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x12345678
[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468ace0
[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468ace0
[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468ace0
[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468ace0
[0-9a-f]+ <[^>]*> 6500 nop
\.\.\.
|