File: edge_detector.vhd

package info (click to toggle)
bladerf 0.2017.12~rc1-2
  • links: PTS, VCS
  • area: main
  • in suites: buster
  • size: 14,620 kB
  • sloc: ansic: 50,123; vhdl: 12,873; python: 1,062; tcl: 1,060; xml: 1,017; makefile: 657; sh: 589; csh: 18; cpp: 9
file content (56 lines) | stat: -rwxr-xr-x 1,774 bytes parent folder | download
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
-- Copyright (c) 2017 Nuand LLC
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

entity edge_detector is
   generic (
      EDGE_RISE  :  std_logic ;
      EDGE_FALL  :  std_logic ;
      NUM_PULSES :  positive range 1 to 1023 := 2
   ) ;
   port (
      clock      :  in std_logic ;
      reset      :  in std_logic ;
      sync_in    :  in std_logic ;
      pulse_out  : out std_logic
   ) ;
end entity ;

architecture arch of edge_detector is
   signal pulses : std_logic_vector( NUM_PULSES - 1 downto 0 ) ;
begin

   process( clock, reset )
   begin
      if( reset = '1' ) then
         pulses <= ( others => sync_in ) ;
         pulse_out <= '0' ;
      elsif( rising_edge( clock ) ) then
         pulses <= sync_in & pulses( NUM_PULSES - 1 downto 1 ) ;

         if( EDGE_RISE = '1' and pulses(1 downto 0) = "10" ) then
            pulse_out <= '1' ;
         elsif ( EDGE_FALL = '1' and pulses(1 downto 0) = "01" ) then
            pulse_out <= '1' ;
         else
            pulse_out <= '0' ;
         end if ;
      end if ;
   end process ;

end architecture ;