1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
|
/////////////////////////////////////////////////////////////////////////
// $Id: bcd.cc,v 1.17 2006/03/06 22:02:51 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
//
// MandrakeSoft S.A.
// 43, rue d'Aboukir
// 75002 Paris - France
// http://www.linux-mandrake.com/
// http://www.mandrakesoft.com/
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
void BX_CPU_C::AAA(bxInstruction_c *)
{
/*
* Note: This instruction incorrectly documented in Intel's materials.
* The right description is:
*
* IF (((AL and 0FH) > 9) or (AF==1)
* THEN
* IF CPU<286 THEN { AL <- AL+6 }
* ELSE { AX <- AX+6 }
* AH <- AH+1
* CF <- 1
* AF <- 1
* ELSE
* CF <- 0
* AF <- 0
* ENDIF
* AL <- AL and 0Fh
*/
/* Validated against Intel Pentium family hardware. */
/* AAA affects the following flags: A,C */
if ( ((AL & 0x0f) > 9) || get_AF() )
{
AX = AX + 0x106;
set_AF(1);
set_CF(1);
}
else {
set_AF(0);
set_CF(0);
}
AL = AL & 0x0f;
/* AAA affects also the following flags: Z,S,O,P */
/* modification of the flags is undocumented */
/* The following behaviour seems to match the P6 and
its derived processors. */
set_OF(0);
set_SF(0); /* sign is always 0 because bits 4-7 of AL are zeroed */
set_ZF(AL == 0);
set_PF_base(AL);
}
void BX_CPU_C::AAS(bxInstruction_c *)
{
/* AAS affects the following flags: A,C */
if ( ((AL & 0x0F) > 0x09) || get_AF() )
{
AX = AX - 0x106;
set_AF(1);
set_CF(1);
}
else {
set_CF(0);
set_AF(0);
}
AL = AL & 0x0f;
/* AAS affects also the following flags: Z,S,O,P */
/* modification of the flags is undocumented */
/* The following behaviour seems to match the P6 and
its derived processors. */
set_OF(0);
set_SF(0); /* sign is always 0 because bits 4-7 of AL are zeroed */
set_ZF(AL == 0);
set_PF_base(AL);
}
void BX_CPU_C::AAM(bxInstruction_c *i)
{
Bit8u al, imm8 = i->Ib();
if (imm8 == 0)
exception(BX_DE_EXCEPTION, 0, 0);
al = AL;
AH = al / imm8;
AL = al % imm8;
/* AAM effects the following flags: A,C,O,S,Z,P */
/* modification of flags A,C,O is undocumented */
/* The following behaviour seems to match the P6 and
its derived processors. */
clear_OF(); /* undocumented flag modification */
clear_AF();
clear_CF();
/* AAM affects the following flags: S,Z,P */
set_SF(AL >= 0x80);
set_ZF(AL == 0);
set_PF_base(AL);
}
void BX_CPU_C::AAD(bxInstruction_c *i)
{
Bit8u imm8 = i->Ib();
Bit16u tmp = AH;
tmp *= imm8;
tmp += AL;
AL = tmp & 0xff;
AH = 0;
/* AAD effects the following flags: A,C,O,S,Z,P */
/* modification of flags A,C,O is undocumented */
/* The following behaviour seems to match the P6 and
its derived processors. */
clear_OF(); /* undocumented flag modification */
clear_AF();
clear_CF();
set_SF(AL >= 0x80);
set_ZF(AL == 0);
set_PF_base(AL);
}
void BX_CPU_C::DAA(bxInstruction_c *)
{
Bit8u tmpAL = AL;
int tmpCF = 0;
/* Validated against Intel Pentium family hardware. */
// DAA affects the following flags: S,Z,A,P,C
if (((tmpAL & 0x0F) > 0x09) || get_AF())
{
tmpCF = ((AL > 0xF9) || get_CF());
AL = AL + 0x06;
set_AF(1);
}
else
set_AF(0);
if ((tmpAL > 0x99) || get_CF())
{
AL = AL + 0x60;
tmpCF = 1;
}
else
tmpCF = 0;
set_OF(0); /* undocumented flag modification */
set_SF(AL >= 0x80);
set_ZF(AL==0);
set_PF_base(AL);
set_CF(tmpCF);
}
void BX_CPU_C::DAS(bxInstruction_c *)
{
/* The algorithm for DAS is fashioned after the pseudo code in the
* Pentium Processor Family Developer's Manual, volume 3. It seems
* to have changed from earlier processor's manuals. I'm not sure
* if this is a correction in the algorithm printed, or Intel has
* changed the handling of instruction. Validated against Intel
* Pentium family hardware.
*/
Bit8u tmpAL = AL;
int tmpCF = 0;
/* DAS effect the following flags: A,C,S,Z,P */
if (((tmpAL & 0x0F) > 0x09) || get_AF())
{
tmpCF = (AL < 0x06) || get_CF();
AL = AL - 0x06;
set_AF(1);
}
else
set_AF(0);
if ((tmpAL > 0x99) || get_CF())
{
AL = AL - 0x60;
tmpCF = 1;
}
set_OF(0); /* undocumented flag modification */
set_SF(AL >= 0x80);
set_ZF(AL==0);
set_PF_base(AL);
set_CF(tmpCF);
}
|
