File: Tline.m4

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circuit-macros 10.1.4-1
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.PS
# `Tline.m4'
cct_init
hgt = elen_*1.5
ewd = dimen_*0.9
define(`sresistor',`resistor(right_ ewd); llabel(,r)')
define(`sinductor',`inductor(right_ ewd,W); llabel(,L)')
define(`tsection',`sinductor
  { dot; line down_ hgt*0.25; dot
    parallel_(`resistor(down_ hgt*0.5); rlabel(,R)',
              `capacitor(down_ hgt*0.5); rlabel(,C)')
    dot; line down_ hgt*0.25; dot }
  sresistor ')

SW: Here
  gap(up_ hgt)
  sresistor
  for i=1 to 4 do { tsection }
  line dotted right_ dimen_/2
  tsection
  gap(down_ hgt)
  line to SW
.PE