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#!/bin/sh
# autopkgtest check: test_dff from README.md
set -e
WORKDIR=$(mktemp -d)
trap "rm -rf $WORKDIR" 0 INT QUIT ABRT PIPE TERM
cd $WORKDIR
cat > Makefile << 'EOF'
TOPLEVEL_LANG ?= verilog
ifeq ($(TOPLEVEL_LANG),verilog)
VERILOG_SOURCES = $(shell pwd)/dff.sv
else ifeq ($(TOPLEVEL_LANG),vhdl)
VHDL_SOURCES = $(shell pwd)/dff.vhdl
endif
COCOTB_TEST_MODULES = test_dff
COCOTB_TOPLEVEL = dff
include $(shell cocotb-config --makefiles)/Makefile.sim
EOF
cat > dff.sv << 'EOF'
`timescale 1us/1us
module dff (
input logic clk, d,
output logic q
);
always @(posedge clk) begin
q <= d;
end
endmodule
EOF
cat > test_dff.py << 'EOF'
import os
import random
from pathlib import Path
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb_tools.runner import get_runner
LANGUAGE = os.getenv("HDL_TOPLEVEL_LANG", "verilog").lower().strip()
@cocotb.test()
async def dff_simple_test(dut):
"""Test that d propagates to q"""
# Set initial input value to prevent it from floating
dut.d.value = 0
# Create a 10us period clock driver on port `clk`
clock = Clock(dut.clk, 10, unit="us")
# Start the clock. Start it low to avoid issues on the first RisingEdge
clock.start(start_high=False)
# Synchronize with the clock. This will register the initial `d` value
await RisingEdge(dut.clk)
expected_val = 0 # Matches initial input value
for i in range(10):
val = random.randint(0, 1)
dut.d.value = val # Assign the random value val to the input port d
await RisingEdge(dut.clk)
assert dut.q.value == expected_val, f"output q was incorrect on the {i}th cycle"
expected_val = val # Save random value for next RisingEdge
# Check the final input on the next clock
await RisingEdge(dut.clk)
assert dut.q.value == expected_val, "output q was incorrect on the last cycle"
def test_simple_dff_runner():
sim = os.getenv("SIM", "icarus")
proj_path = Path(__file__).resolve().parent
if LANGUAGE == "verilog":
sources = [proj_path / "dff.sv"]
else:
sources = [proj_path / "dff.vhdl"]
runner = get_runner(sim)
runner.build(
sources=sources,
hdl_toplevel="dff",
always=True,
)
runner.test(hdl_toplevel="dff", test_module="test_dff,")
if __name__ == "__main__":
test_simple_dff_runner()
EOF
# Disable warning about experimental runners feature:
export PYTHONWARNINGS="ignore:Python runners:UserWarning"
make SIM=icarus
|
