1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity x is
port(
rst : in std_logic;
clk : in std_logic;
d : in std_logic;
q : out std_logic_vector;
a, b : in std_logic;
v : out std_logic
);
end x;
architecture behavioral of x is
signal q_i : std_logic_vector(q'range);
begin
v <= a when b = '1' else '0';
gen: for j in q'low to q'high generate
gen_first: if j = q'low generate
variable foo : boolean := false;
begin
stage1: process (rst, clk) begin
if rst = '1' then
q_i(j) <= '0';
elsif rising_edge(clk) then
q_i(j) <= d;
case a is
when 1 =>
when 2 =>
when others =>
end case;
end if;
end process;
else generate
stages: process (rst, clk)
begin
if rst = '1' then
q_i(j) <= '0';
elsif rising_edge(clk) then
for u in 0 to 7 loop
q_i(j) <= q_i(j - 1);
end loop;
end if;
end process;
end generate;
end generate;
L: case expression generate
when choice1 =>
when choice2 =>
end generate L;
end behavioral;
|
