File: mux.vhdl

package info (click to toggle)
doxygen 1.8.12-1
  • links: PTS
  • area: main
  • in suites: stretch
  • size: 19,856 kB
  • ctags: 30,758
  • sloc: cpp: 237,683; lex: 35,587; xml: 8,286; python: 2,768; ansic: 629; tcl: 594; php: 446; perl: 370; makefile: 241; yacc: 235; objc: 14; sh: 11; java: 1
file content (32 lines) | stat: -rw-r--r-- 860 bytes parent folder | download | duplicates (19) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
 
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------

--! Use standard library
library ieee;
--! Use logic elements
    use ieee.std_logic_1164.all;

--! Mux entity brief description

--! Detailed description of this 
--! mux design element.
entity mux_using_with is
    port (
        din_0   : in  std_logic; --! Mux first input
        din_1   : in  std_logic; --! Mux Second input
        sel     : in  std_logic; --! Select input
        mux_out : out std_logic  --! Mux output
    );
end entity;

--! @brief Architecture definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
    with (sel) select
    mux_out <= din_0 when '0',
               din_1 when others;
end architecture;