1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510 4511 4512 4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598 4599 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681 4682 4683 4684 4685 4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710 4711 4712 4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754 4755 4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809 4810 4811 4812 4813 4814 4815 4816 4817 4818 4819 4820 4821 4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922 4923 4924 4925 4926 4927 4928 4929 4930 4931 4932 4933 4934 4935 4936 4937 4938 4939 4940 4941 4942 4943 4944 4945 4946 4947 4948 4949 4950 4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971 4972 4973 4974 4975 4976 4977 4978 4979 4980 4981 4982 4983 4984 4985 4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013 5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025 5026 5027 5028 5029 5030 5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059 5060 5061 5062 5063 5064 5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101 5102 5103 5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115 5116 5117 5118 5119 5120 5121 5122 5123 5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137 5138 5139 5140 5141 5142 5143 5144 5145 5146 5147 5148 5149 5150 5151 5152 5153 5154 5155 5156 5157 5158 5159 5160 5161 5162 5163 5164 5165 5166 5167 5168 5169 5170 5171 5172 5173 5174 5175 5176 5177 5178 5179 5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190 5191 5192 5193 5194 5195 5196 5197 5198 5199 5200 5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213 5214 5215 5216 5217 5218 5219 5220 5221 5222 5223 5224 5225 5226 5227 5228 5229 5230 5231 5232 5233 5234 5235 5236 5237 5238 5239 5240 5241 5242 5243 5244 5245 5246 5247 5248 5249 5250 5251 5252 5253 5254 5255 5256 5257 5258 5259 5260 5261 5262 5263 5264 5265 5266 5267 5268 5269 5270 5271 5272 5273 5274 5275 5276 5277 5278 5279 5280 5281 5282 5283 5284 5285 5286 5287 5288 5289 5290 5291 5292 5293 5294 5295 5296 5297 5298 5299 5300 5301 5302 5303 5304 5305 5306 5307 5308 5309 5310 5311 5312 5313 5314 5315 5316 5317 5318 5319 5320 5321 5322 5323 5324 5325 5326 5327 5328 5329 5330 5331 5332 5333 5334 5335 5336 5337 5338 5339 5340 5341 5342 5343 5344 5345 5346 5347 5348 5349 5350 5351 5352 5353 5354 5355 5356 5357 5358 5359 5360 5361 5362 5363 5364 5365 5366 5367 5368 5369 5370 5371 5372 5373 5374 5375 5376 5377 5378 5379 5380 5381 5382 5383 5384 5385 5386 5387 5388 5389 5390 5391 5392 5393 5394 5395 5396 5397 5398 5399 5400 5401 5402 5403 5404 5405 5406 5407 5408 5409 5410 5411 5412 5413 5414 5415 5416 5417 5418 5419 5420 5421 5422 5423 5424 5425 5426 5427 5428 5429 5430 5431 5432 5433 5434 5435 5436 5437 5438 5439 5440 5441 5442 5443 5444 5445 5446 5447 5448 5449 5450 5451 5452 5453 5454 5455 5456 5457 5458 5459 5460 5461 5462 5463 5464 5465 5466 5467 5468 5469 5470 5471 5472 5473 5474 5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490 5491 5492 5493 5494 5495 5496 5497 5498 5499 5500 5501 5502 5503 5504 5505 5506 5507 5508 5509 5510 5511 5512 5513 5514 5515 5516 5517 5518 5519 5520 5521 5522 5523 5524 5525 5526 5527 5528 5529 5530 5531 5532 5533 5534 5535 5536 5537 5538 5539 5540 5541 5542 5543 5544 5545 5546 5547 5548 5549 5550 5551 5552 5553 5554 5555 5556 5557 5558 5559 5560 5561 5562 5563 5564 5565 5566 5567 5568 5569 5570 5571 5572 5573 5574 5575 5576 5577 5578 5579 5580 5581 5582 5583 5584 5585 5586 5587 5588 5589 5590 5591 5592 5593 5594 5595 5596 5597 5598 5599 5600 5601 5602 5603 5604 5605 5606 5607 5608 5609 5610 5611 5612 5613 5614 5615 5616 5617 5618 5619 5620 5621 5622 5623 5624 5625 5626 5627 5628 5629 5630 5631 5632 5633 5634 5635 5636 5637 5638 5639 5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650 5651 5652 5653 5654 5655 5656 5657 5658 5659 5660 5661 5662 5663 5664 5665 5666 5667 5668 5669 5670 5671 5672 5673 5674 5675 5676 5677 5678 5679 5680 5681 5682 5683 5684 5685 5686 5687 5688 5689 5690 5691 5692 5693 5694 5695 5696 5697 5698 5699 5700 5701 5702 5703 5704 5705 5706 5707 5708 5709 5710 5711 5712 5713 5714 5715 5716 5717 5718 5719 5720 5721 5722 5723 5724 5725 5726 5727 5728 5729 5730 5731 5732 5733 5734 5735 5736 5737 5738 5739 5740 5741 5742 5743 5744 5745 5746 5747 5748 5749 5750 5751 5752 5753 5754 5755 5756 5757 5758 5759 5760 5761 5762 5763 5764 5765 5766 5767 5768 5769 5770 5771 5772 5773 5774 5775 5776 5777 5778 5779 5780 5781 5782 5783 5784 5785 5786 5787 5788 5789 5790 5791 5792 5793 5794 5795 5796 5797 5798 5799 5800 5801 5802 5803 5804 5805 5806 5807 5808 5809 5810 5811 5812 5813 5814 5815 5816 5817 5818 5819 5820 5821 5822 5823 5824 5825 5826 5827 5828 5829 5830 5831 5832 5833 5834 5835 5836 5837 5838 5839 5840 5841 5842 5843 5844 5845 5846 5847 5848 5849 5850 5851 5852 5853 5854 5855 5856 5857 5858 5859 5860 5861 5862 5863 5864 5865 5866 5867 5868 5869 5870 5871 5872 5873 5874 5875 5876 5877 5878 5879 5880 5881 5882 5883 5884 5885 5886 5887 5888 5889 5890 5891 5892 5893 5894 5895 5896 5897 5898 5899 5900 5901 5902 5903 5904 5905 5906 5907 5908 5909 5910 5911 5912 5913 5914 5915 5916 5917 5918 5919 5920 5921 5922 5923 5924 5925 5926 5927 5928 5929 5930 5931 5932 5933 5934 5935 5936 5937 5938 5939 5940 5941 5942 5943 5944 5945 5946 5947 5948 5949 5950 5951 5952 5953 5954 5955 5956 5957 5958 5959 5960 5961 5962 5963 5964 5965 5966 5967 5968 5969 5970 5971 5972 5973 5974 5975 5976 5977 5978 5979 5980 5981 5982 5983 5984 5985 5986 5987 5988 5989 5990 5991 5992 5993 5994 5995 5996 5997 5998 5999 6000 6001 6002 6003 6004 6005 6006 6007 6008 6009 6010 6011 6012 6013 6014 6015 6016 6017 6018 6019 6020 6021 6022 6023 6024 6025 6026 6027 6028 6029 6030 6031 6032 6033 6034 6035 6036 6037 6038 6039 6040 6041 6042 6043 6044 6045 6046 6047 6048 6049 6050 6051 6052 6053 6054 6055 6056 6057 6058 6059 6060 6061 6062 6063 6064 6065 6066 6067 6068 6069 6070 6071 6072 6073 6074 6075 6076 6077 6078 6079 6080 6081 6082 6083 6084 6085 6086 6087 6088 6089 6090 6091 6092 6093 6094 6095 6096 6097 6098 6099 6100 6101 6102 6103 6104 6105 6106 6107 6108 6109 6110 6111 6112 6113 6114 6115 6116 6117 6118 6119 6120 6121 6122 6123 6124 6125 6126 6127 6128 6129 6130 6131 6132 6133 6134 6135 6136 6137 6138 6139 6140 6141 6142 6143 6144 6145 6146 6147 6148 6149 6150 6151 6152 6153 6154 6155 6156 6157 6158 6159 6160 6161 6162 6163 6164 6165 6166 6167 6168 6169 6170 6171 6172 6173 6174 6175 6176 6177 6178 6179 6180 6181 6182 6183 6184 6185 6186 6187 6188 6189 6190 6191 6192 6193 6194 6195 6196 6197 6198 6199 6200 6201 6202 6203 6204 6205 6206 6207 6208 6209 6210 6211 6212 6213 6214 6215 6216 6217 6218 6219 6220 6221 6222 6223 6224 6225 6226 6227 6228 6229 6230 6231 6232 6233 6234 6235 6236 6237 6238 6239 6240 6241 6242 6243 6244 6245 6246 6247 6248 6249 6250 6251 6252 6253 6254 6255 6256 6257 6258 6259 6260 6261 6262 6263 6264 6265 6266 6267 6268 6269 6270 6271 6272 6273 6274 6275 6276 6277 6278 6279 6280 6281 6282 6283 6284 6285 6286 6287 6288 6289 6290 6291 6292 6293 6294 6295 6296 6297 6298 6299 6300 6301 6302 6303 6304 6305 6306 6307 6308 6309 6310 6311 6312 6313 6314 6315 6316 6317 6318 6319 6320 6321 6322 6323 6324 6325 6326 6327 6328 6329 6330 6331 6332 6333 6334 6335 6336 6337 6338 6339 6340 6341 6342 6343 6344 6345 6346 6347 6348 6349 6350 6351 6352 6353 6354 6355 6356 6357 6358 6359 6360 6361 6362 6363 6364 6365 6366 6367 6368 6369 6370 6371 6372 6373 6374 6375 6376 6377 6378 6379 6380 6381 6382 6383 6384 6385 6386 6387 6388 6389 6390 6391 6392 6393 6394 6395 6396 6397 6398 6399 6400 6401 6402 6403 6404 6405 6406 6407 6408 6409 6410 6411 6412 6413 6414 6415 6416 6417 6418 6419 6420 6421 6422 6423 6424 6425 6426 6427 6428 6429 6430 6431 6432 6433 6434 6435 6436 6437 6438 6439 6440 6441 6442 6443 6444 6445 6446 6447 6448 6449 6450 6451 6452 6453 6454 6455 6456 6457 6458 6459 6460 6461 6462 6463 6464 6465 6466 6467 6468 6469 6470 6471 6472 6473 6474 6475 6476 6477 6478 6479 6480 6481 6482 6483 6484 6485 6486 6487 6488 6489 6490 6491 6492 6493 6494 6495 6496 6497 6498 6499 6500 6501 6502 6503 6504 6505 6506 6507 6508 6509 6510 6511 6512 6513 6514 6515 6516 6517 6518 6519 6520 6521 6522 6523 6524 6525 6526 6527 6528 6529 6530 6531 6532 6533 6534 6535 6536 6537 6538 6539 6540 6541 6542 6543 6544 6545 6546 6547 6548 6549 6550 6551 6552 6553 6554 6555 6556 6557 6558 6559 6560 6561 6562 6563 6564 6565 6566 6567 6568 6569 6570 6571 6572 6573 6574 6575 6576 6577 6578 6579 6580 6581 6582 6583 6584 6585 6586 6587 6588 6589 6590 6591 6592 6593 6594 6595 6596 6597 6598 6599 6600 6601 6602 6603 6604 6605 6606 6607 6608 6609 6610 6611 6612 6613 6614 6615 6616 6617 6618 6619 6620 6621 6622 6623 6624 6625 6626 6627 6628 6629 6630 6631 6632 6633 6634 6635 6636 6637 6638 6639 6640 6641 6642 6643 6644 6645 6646 6647 6648 6649 6650 6651 6652 6653 6654 6655 6656 6657 6658 6659 6660 6661 6662 6663 6664 6665 6666 6667 6668 6669 6670 6671 6672 6673 6674 6675 6676 6677 6678 6679 6680 6681 6682 6683 6684 6685 6686 6687 6688 6689 6690 6691 6692 6693 6694 6695 6696 6697 6698 6699 6700 6701 6702 6703 6704 6705 6706 6707 6708 6709 6710 6711 6712 6713 6714 6715 6716 6717 6718 6719 6720 6721 6722 6723 6724 6725 6726 6727 6728 6729 6730 6731 6732 6733 6734 6735 6736 6737 6738 6739 6740 6741 6742 6743 6744 6745 6746 6747 6748 6749 6750 6751 6752 6753 6754 6755 6756 6757 6758 6759 6760 6761 6762 6763 6764 6765 6766 6767 6768 6769 6770 6771 6772 6773 6774 6775 6776 6777 6778 6779 6780 6781 6782 6783 6784 6785 6786 6787 6788 6789 6790 6791 6792 6793 6794 6795 6796 6797 6798 6799 6800 6801 6802 6803 6804 6805 6806 6807 6808 6809 6810 6811 6812 6813 6814 6815 6816 6817 6818 6819 6820 6821 6822 6823 6824 6825 6826 6827 6828 6829 6830 6831 6832 6833 6834 6835 6836 6837 6838 6839 6840 6841 6842 6843 6844 6845 6846 6847 6848 6849 6850 6851 6852 6853 6854 6855 6856 6857 6858 6859 6860 6861 6862 6863 6864 6865 6866 6867 6868 6869 6870 6871 6872 6873 6874 6875 6876 6877 6878 6879 6880 6881 6882 6883 6884 6885 6886 6887 6888 6889 6890 6891 6892 6893 6894 6895 6896 6897 6898 6899 6900 6901 6902 6903 6904 6905 6906 6907 6908 6909 6910 6911 6912 6913 6914 6915 6916 6917 6918 6919 6920 6921 6922 6923 6924 6925 6926 6927 6928 6929 6930 6931 6932 6933 6934 6935 6936 6937 6938 6939 6940 6941 6942 6943 6944 6945 6946 6947 6948 6949 6950 6951 6952 6953 6954 6955 6956 6957 6958 6959 6960 6961 6962 6963 6964 6965 6966 6967 6968 6969 6970 6971 6972 6973 6974 6975 6976 6977 6978 6979 6980 6981 6982 6983 6984 6985 6986 6987 6988 6989 6990 6991 6992 6993 6994 6995 6996 6997 6998 6999 7000 7001 7002 7003 7004 7005 7006 7007 7008 7009 7010 7011 7012 7013 7014 7015 7016 7017 7018 7019 7020 7021 7022 7023 7024 7025 7026 7027 7028 7029 7030 7031 7032 7033 7034 7035 7036 7037 7038 7039 7040 7041 7042 7043 7044 7045 7046 7047 7048 7049 7050 7051 7052 7053 7054 7055 7056 7057 7058 7059 7060 7061 7062 7063 7064 7065 7066 7067 7068 7069 7070 7071 7072 7073 7074 7075 7076 7077 7078 7079 7080 7081 7082 7083 7084 7085 7086 7087 7088 7089 7090 7091 7092 7093 7094 7095 7096 7097 7098 7099 7100 7101 7102 7103 7104 7105 7106 7107 7108 7109 7110 7111 7112 7113 7114 7115 7116 7117 7118 7119 7120 7121 7122 7123 7124 7125 7126 7127 7128 7129 7130 7131 7132 7133 7134 7135 7136 7137 7138 7139 7140 7141 7142 7143 7144 7145 7146 7147 7148 7149 7150 7151 7152 7153 7154 7155 7156 7157 7158 7159 7160 7161 7162 7163 7164 7165 7166 7167 7168 7169 7170 7171 7172 7173 7174 7175 7176 7177 7178 7179 7180 7181 7182 7183 7184 7185 7186 7187 7188 7189 7190 7191 7192 7193 7194 7195 7196 7197 7198 7199 7200 7201 7202 7203 7204 7205 7206 7207 7208 7209 7210 7211 7212 7213 7214 7215 7216 7217 7218 7219 7220 7221 7222 7223 7224 7225 7226 7227 7228 7229 7230 7231 7232 7233 7234 7235 7236 7237 7238 7239 7240 7241 7242 7243 7244 7245 7246 7247 7248 7249 7250 7251 7252 7253 7254 7255 7256 7257 7258 7259 7260 7261 7262 7263 7264 7265 7266 7267 7268 7269 7270 7271 7272 7273 7274 7275 7276 7277 7278 7279 7280 7281 7282 7283 7284 7285 7286 7287 7288 7289 7290 7291 7292 7293 7294 7295 7296 7297 7298 7299 7300 7301 7302 7303 7304 7305 7306 7307 7308 7309 7310 7311 7312 7313 7314 7315 7316 7317 7318 7319 7320 7321 7322 7323 7324 7325 7326 7327 7328 7329 7330 7331 7332 7333 7334 7335 7336 7337 7338 7339 7340 7341 7342 7343 7344 7345 7346 7347 7348 7349 7350 7351 7352 7353 7354 7355 7356 7357 7358 7359 7360 7361 7362 7363 7364 7365 7366 7367 7368 7369 7370 7371 7372 7373 7374 7375 7376 7377 7378 7379 7380 7381 7382 7383 7384 7385 7386 7387 7388 7389 7390 7391 7392 7393 7394 7395 7396 7397 7398 7399 7400 7401 7402 7403 7404 7405 7406 7407 7408 7409 7410 7411 7412 7413 7414 7415 7416 7417 7418 7419 7420 7421 7422 7423 7424 7425 7426 7427 7428 7429 7430 7431 7432 7433 7434 7435 7436 7437 7438 7439 7440 7441 7442 7443 7444 7445 7446 7447 7448 7449 7450 7451 7452 7453 7454 7455 7456 7457 7458 7459 7460 7461 7462 7463 7464 7465 7466 7467 7468 7469 7470 7471 7472 7473 7474 7475 7476 7477 7478 7479 7480 7481 7482 7483 7484 7485 7486 7487 7488 7489 7490 7491 7492 7493 7494 7495 7496 7497 7498 7499 7500 7501 7502 7503 7504 7505 7506 7507 7508 7509 7510 7511 7512 7513 7514 7515 7516 7517 7518 7519 7520 7521 7522 7523 7524 7525 7526 7527 7528 7529 7530 7531 7532 7533 7534 7535 7536 7537 7538 7539 7540 7541 7542 7543 7544 7545 7546 7547 7548 7549 7550 7551 7552 7553 7554 7555 7556 7557 7558 7559 7560 7561 7562 7563 7564 7565 7566 7567 7568 7569 7570 7571 7572 7573 7574 7575 7576 7577 7578 7579 7580 7581 7582 7583 7584 7585 7586 7587 7588 7589 7590 7591 7592 7593 7594 7595 7596 7597 7598 7599 7600 7601 7602 7603 7604 7605 7606 7607 7608 7609 7610 7611 7612 7613 7614 7615 7616 7617 7618 7619 7620 7621 7622 7623 7624 7625 7626 7627 7628 7629 7630 7631 7632 7633 7634 7635 7636 7637 7638 7639 7640 7641 7642 7643 7644 7645 7646 7647 7648 7649 7650 7651 7652 7653 7654 7655 7656 7657 7658 7659 7660 7661 7662 7663 7664 7665 7666 7667 7668 7669 7670 7671 7672 7673 7674 7675 7676 7677 7678 7679 7680 7681 7682 7683 7684 7685 7686 7687 7688 7689 7690 7691 7692 7693 7694 7695 7696 7697 7698 7699 7700 7701 7702 7703 7704 7705 7706 7707 7708 7709 7710 7711 7712 7713 7714 7715 7716 7717 7718 7719 7720 7721 7722 7723 7724 7725 7726 7727 7728 7729 7730 7731 7732 7733 7734 7735 7736 7737 7738 7739 7740 7741 7742 7743 7744 7745 7746 7747 7748 7749 7750 7751 7752 7753 7754 7755 7756 7757 7758 7759 7760 7761 7762 7763 7764 7765 7766 7767 7768 7769 7770 7771 7772 7773 7774 7775 7776 7777 7778 7779 7780 7781 7782 7783 7784 7785 7786 7787 7788 7789 7790 7791 7792 7793 7794 7795 7796 7797 7798 7799 7800 7801 7802 7803 7804 7805 7806 7807 7808 7809 7810 7811 7812 7813 7814 7815 7816 7817 7818 7819 7820 7821 7822 7823 7824 7825 7826 7827 7828 7829 7830 7831 7832 7833 7834 7835 7836 7837 7838 7839 7840 7841 7842 7843 7844 7845 7846 7847 7848 7849 7850 7851 7852 7853 7854 7855 7856 7857 7858 7859 7860 7861 7862 7863 7864 7865 7866 7867 7868 7869 7870 7871 7872 7873 7874 7875 7876 7877 7878 7879 7880 7881 7882 7883 7884 7885 7886 7887 7888 7889 7890 7891 7892 7893 7894 7895 7896 7897 7898 7899 7900 7901 7902 7903 7904 7905 7906 7907 7908 7909 7910 7911 7912 7913 7914 7915 7916 7917 7918 7919 7920 7921 7922 7923 7924 7925 7926 7927 7928 7929 7930 7931 7932 7933 7934 7935 7936 7937 7938 7939 7940 7941 7942 7943 7944 7945 7946 7947 7948 7949 7950 7951 7952 7953 7954 7955 7956 7957 7958 7959 7960 7961 7962 7963 7964 7965 7966 7967 7968 7969 7970 7971 7972 7973 7974 7975 7976 7977 7978 7979 7980 7981 7982 7983 7984 7985 7986 7987 7988 7989 7990 7991 7992 7993 7994 7995 7996 7997 7998 7999 8000 8001 8002 8003 8004 8005 8006 8007 8008 8009 8010 8011 8012 8013 8014 8015 8016 8017 8018 8019 8020 8021 8022 8023 8024 8025 8026 8027 8028 8029 8030 8031 8032 8033 8034 8035 8036 8037 8038 8039 8040 8041 8042 8043 8044 8045 8046 8047 8048 8049 8050 8051 8052 8053 8054 8055 8056 8057 8058 8059 8060 8061 8062 8063 8064 8065 8066 8067 8068 8069 8070 8071 8072 8073 8074 8075 8076 8077 8078 8079 8080 8081 8082 8083 8084 8085 8086 8087 8088 8089 8090 8091 8092 8093 8094 8095 8096 8097 8098 8099 8100 8101 8102 8103 8104 8105 8106 8107 8108 8109 8110 8111 8112 8113 8114 8115 8116 8117 8118 8119 8120 8121 8122 8123 8124 8125 8126 8127 8128 8129 8130 8131 8132 8133 8134 8135 8136 8137 8138 8139 8140 8141 8142 8143 8144 8145 8146 8147 8148 8149 8150 8151 8152 8153 8154 8155 8156 8157 8158 8159 8160 8161 8162 8163 8164 8165 8166 8167 8168 8169 8170 8171 8172 8173 8174 8175 8176 8177 8178 8179 8180 8181 8182 8183 8184 8185 8186 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 8197 8198 8199 8200 8201 8202 8203 8204 8205 8206 8207 8208 8209 8210 8211 8212 8213 8214 8215 8216 8217 8218 8219 8220 8221 8222 8223 8224 8225 8226 8227 8228 8229 8230 8231 8232 8233 8234 8235 8236 8237 8238 8239 8240 8241 8242 8243 8244 8245 8246 8247 8248 8249 8250 8251 8252 8253 8254 8255 8256 8257 8258 8259 8260 8261 8262 8263 8264 8265 8266 8267 8268 8269 8270 8271 8272 8273 8274 8275 8276 8277 8278 8279 8280 8281 8282 8283 8284 8285 8286 8287 8288 8289 8290 8291 8292 8293 8294 8295 8296 8297 8298 8299 8300 8301 8302 8303 8304 8305 8306 8307 8308 8309 8310 8311 8312 8313 8314 8315 8316 8317 8318 8319 8320 8321 8322 8323 8324 8325 8326 8327 8328 8329 8330 8331 8332 8333 8334 8335 8336 8337 8338 8339 8340 8341 8342 8343 8344 8345 8346 8347 8348 8349 8350 8351 8352 8353 8354 8355 8356 8357 8358 8359 8360 8361 8362 8363 8364 8365 8366 8367 8368 8369 8370 8371 8372 8373 8374 8375 8376 8377 8378 8379 8380 8381 8382 8383 8384 8385 8386 8387 8388 8389 8390 8391 8392 8393 8394 8395 8396 8397 8398 8399 8400 8401 8402 8403 8404 8405 8406 8407 8408 8409 8410 8411 8412 8413 8414 8415 8416 8417 8418 8419 8420 8421 8422 8423 8424 8425 8426 8427 8428 8429 8430 8431 8432 8433 8434 8435 8436 8437 8438 8439 8440 8441 8442 8443 8444 8445 8446 8447 8448 8449 8450 8451 8452 8453 8454 8455 8456 8457 8458 8459 8460 8461 8462 8463 8464 8465 8466 8467 8468 8469 8470 8471 8472 8473 8474 8475 8476 8477 8478 8479 8480 8481 8482 8483 8484 8485 8486 8487 8488 8489 8490 8491 8492 8493 8494 8495 8496 8497 8498 8499 8500 8501 8502 8503 8504 8505 8506 8507 8508 8509 8510 8511 8512 8513 8514 8515 8516 8517 8518 8519 8520 8521 8522 8523 8524 8525 8526 8527 8528 8529 8530 8531 8532 8533 8534 8535 8536 8537 8538 8539 8540 8541 8542 8543 8544 8545 8546 8547 8548 8549 8550 8551 8552 8553 8554 8555 8556 8557 8558 8559 8560 8561 8562 8563 8564 8565 8566 8567 8568 8569 8570 8571 8572 8573 8574 8575 8576 8577 8578 8579 8580 8581 8582 8583 8584 8585 8586 8587 8588 8589 8590 8591 8592 8593 8594 8595 8596 8597 8598 8599 8600 8601 8602 8603 8604 8605 8606 8607 8608 8609 8610 8611 8612 8613 8614 8615 8616 8617 8618 8619 8620 8621 8622 8623 8624 8625 8626 8627 8628 8629 8630 8631 8632 8633 8634 8635 8636 8637 8638 8639 8640 8641 8642 8643 8644 8645 8646 8647 8648 8649 8650 8651 8652 8653 8654 8655 8656 8657 8658 8659 8660 8661 8662 8663 8664 8665 8666 8667 8668 8669 8670 8671 8672 8673 8674 8675 8676 8677 8678 8679 8680 8681 8682 8683 8684 8685 8686 8687 8688 8689 8690 8691 8692 8693 8694 8695 8696 8697 8698 8699 8700 8701 8702 8703 8704 8705 8706 8707 8708 8709 8710 8711 8712 8713 8714 8715 8716 8717 8718 8719 8720 8721 8722 8723 8724 8725 8726 8727 8728 8729 8730 8731 8732 8733 8734 8735 8736 8737 8738 8739 8740 8741 8742 8743 8744 8745 8746 8747 8748 8749 8750 8751 8752 8753 8754 8755 8756 8757 8758 8759 8760 8761 8762 8763 8764 8765 8766 8767 8768 8769 8770 8771 8772 8773 8774 8775 8776 8777 8778 8779 8780 8781 8782 8783 8784 8785 8786 8787 8788 8789 8790 8791 8792 8793 8794 8795 8796 8797 8798 8799 8800 8801 8802 8803 8804 8805 8806 8807 8808 8809 8810 8811 8812 8813 8814 8815 8816 8817 8818 8819 8820 8821 8822 8823 8824 8825 8826 8827 8828 8829 8830 8831 8832 8833 8834 8835 8836 8837 8838 8839 8840 8841 8842 8843 8844 8845 8846 8847 8848 8849 8850 8851 8852 8853 8854 8855 8856 8857 8858 8859 8860 8861 8862 8863 8864 8865 8866 8867 8868 8869 8870 8871 8872 8873 8874 8875 8876 8877 8878 8879 8880 8881 8882 8883 8884 8885 8886 8887 8888 8889 8890 8891 8892 8893 8894 8895 8896 8897 8898 8899 8900 8901 8902 8903 8904 8905 8906 8907 8908 8909 8910 8911 8912 8913 8914 8915 8916 8917 8918 8919 8920 8921 8922 8923 8924 8925 8926 8927 8928 8929 8930 8931 8932 8933 8934 8935 8936 8937 8938 8939 8940 8941 8942 8943 8944 8945 8946 8947 8948 8949 8950 8951 8952 8953 8954 8955 8956 8957 8958 8959 8960 8961 8962 8963 8964 8965 8966 8967 8968 8969 8970 8971 8972 8973 8974 8975 8976 8977 8978 8979 8980 8981 8982 8983 8984 8985 8986 8987 8988 8989 8990 8991 8992 8993 8994 8995 8996 8997 8998 8999 9000 9001 9002 9003 9004 9005 9006 9007 9008 9009 9010 9011 9012 9013 9014 9015 9016 9017 9018 9019 9020 9021 9022 9023 9024 9025 9026 9027 9028 9029 9030 9031 9032 9033 9034 9035 9036 9037 9038 9039 9040 9041 9042 9043 9044 9045 9046 9047 9048 9049 9050 9051 9052 9053 9054 9055 9056 9057 9058 9059 9060 9061 9062 9063 9064 9065 9066 9067 9068 9069 9070 9071 9072 9073 9074 9075 9076 9077 9078 9079 9080 9081 9082 9083 9084 9085 9086 9087 9088 9089 9090 9091 9092 9093 9094 9095 9096 9097 9098 9099 9100 9101 9102 9103 9104 9105 9106 9107 9108 9109 9110 9111 9112 9113 9114 9115 9116 9117 9118 9119 9120 9121 9122 9123 9124 9125 9126 9127 9128 9129 9130 9131 9132 9133 9134 9135 9136 9137 9138 9139 9140 9141 9142 9143 9144 9145 9146 9147 9148 9149 9150 9151 9152 9153 9154 9155 9156 9157 9158 9159 9160 9161 9162 9163 9164 9165 9166 9167 9168 9169 9170 9171 9172 9173 9174 9175 9176 9177 9178 9179 9180 9181 9182 9183 9184 9185 9186 9187 9188 9189 9190 9191 9192 9193 9194 9195 9196 9197 9198 9199 9200 9201 9202 9203 9204 9205 9206 9207 9208 9209 9210 9211 9212 9213 9214 9215 9216 9217 9218 9219 9220 9221 9222 9223 9224 9225 9226 9227 9228 9229 9230 9231 9232 9233 9234 9235 9236 9237 9238 9239 9240 9241 9242 9243 9244 9245 9246 9247 9248 9249 9250 9251 9252 9253 9254 9255 9256 9257 9258 9259 9260 9261 9262 9263 9264 9265 9266 9267 9268 9269 9270 9271 9272 9273 9274 9275 9276 9277 9278 9279 9280 9281 9282 9283 9284 9285 9286 9287 9288 9289 9290 9291 9292 9293 9294 9295 9296 9297 9298 9299 9300 9301 9302 9303 9304 9305 9306 9307 9308 9309 9310 9311 9312 9313 9314 9315 9316 9317 9318 9319 9320 9321 9322 9323 9324 9325 9326 9327 9328 9329 9330 9331 9332 9333 9334 9335 9336 9337 9338 9339 9340 9341 9342 9343 9344 9345 9346 9347 9348 9349 9350 9351 9352 9353 9354 9355 9356 9357 9358 9359 9360 9361 9362 9363 9364 9365 9366 9367 9368 9369 9370 9371 9372 9373 9374 9375 9376 9377 9378 9379 9380 9381 9382 9383 9384 9385 9386 9387 9388 9389 9390 9391 9392 9393 9394 9395 9396 9397 9398 9399 9400 9401 9402 9403 9404 9405 9406 9407 9408 9409 9410 9411 9412 9413 9414 9415 9416 9417 9418 9419 9420 9421 9422 9423 9424 9425 9426 9427 9428 9429 9430 9431 9432 9433 9434 9435 9436 9437 9438 9439 9440 9441 9442 9443 9444 9445 9446 9447 9448 9449 9450 9451 9452 9453 9454 9455 9456 9457 9458 9459 9460 9461 9462 9463 9464 9465 9466 9467 9468 9469 9470 9471 9472 9473 9474 9475 9476 9477 9478 9479 9480 9481 9482 9483 9484 9485 9486 9487 9488 9489 9490 9491 9492 9493 9494 9495 9496 9497 9498 9499 9500 9501 9502 9503 9504 9505 9506 9507 9508 9509 9510 9511 9512 9513 9514 9515 9516 9517 9518 9519 9520 9521 9522 9523 9524 9525 9526 9527 9528 9529 9530 9531 9532 9533 9534 9535 9536 9537 9538 9539 9540 9541 9542 9543 9544 9545 9546 9547 9548 9549 9550 9551 9552 9553 9554 9555 9556 9557 9558 9559 9560 9561 9562 9563 9564 9565 9566 9567 9568 9569 9570 9571 9572 9573 9574 9575 9576 9577 9578 9579 9580 9581 9582 9583 9584 9585 9586 9587 9588 9589 9590 9591 9592 9593 9594 9595 9596 9597 9598 9599 9600 9601 9602 9603 9604 9605 9606 9607 9608 9609 9610 9611 9612 9613 9614 9615 9616 9617 9618 9619 9620 9621 9622 9623 9624 9625 9626 9627 9628 9629 9630 9631 9632 9633 9634 9635 9636 9637 9638 9639 9640 9641 9642 9643 9644 9645 9646 9647 9648 9649 9650 9651 9652 9653 9654 9655 9656 9657 9658 9659 9660 9661 9662 9663 9664 9665 9666 9667 9668 9669 9670 9671 9672 9673 9674 9675 9676 9677 9678 9679 9680 9681 9682 9683 9684 9685 9686 9687 9688 9689 9690 9691 9692 9693 9694 9695 9696 9697 9698 9699 9700 9701 9702 9703 9704 9705 9706 9707 9708 9709 9710 9711 9712 9713 9714 9715 9716 9717 9718 9719 9720 9721 9722 9723 9724 9725 9726 9727 9728 9729 9730 9731 9732 9733 9734 9735 9736 9737 9738 9739 9740 9741 9742 9743 9744 9745 9746 9747 9748 9749 9750 9751 9752 9753 9754 9755 9756 9757 9758 9759 9760 9761 9762 9763 9764 9765 9766 9767 9768 9769 9770 9771 9772 9773 9774 9775 9776 9777 9778 9779 9780 9781 9782 9783 9784 9785 9786 9787 9788 9789 9790 9791 9792 9793 9794 9795 9796 9797 9798 9799 9800 9801 9802 9803 9804 9805 9806 9807 9808 9809 9810 9811 9812 9813 9814 9815 9816 9817 9818 9819 9820 9821 9822 9823 9824 9825 9826 9827 9828 9829 9830 9831 9832 9833 9834 9835 9836 9837 9838 9839 9840 9841 9842 9843 9844 9845 9846 9847 9848 9849 9850 9851 9852 9853 9854 9855 9856 9857 9858 9859 9860 9861 9862 9863 9864 9865 9866 9867 9868 9869 9870 9871 9872 9873 9874 9875 9876 9877 9878 9879 9880 9881 9882 9883 9884 9885 9886 9887 9888 9889 9890 9891 9892 9893 9894 9895 9896 9897 9898 9899 9900 9901 9902 9903 9904 9905 9906 9907 9908 9909 9910 9911 9912 9913 9914 9915 9916 9917 9918 9919 9920 9921 9922 9923 9924 9925 9926 9927 9928 9929 9930 9931 9932 9933 9934 9935 9936 9937 9938 9939 9940 9941 9942 9943 9944 9945 9946 9947 9948 9949 9950 9951 9952 9953 9954 9955 9956 9957 9958 9959 9960 9961 9962 9963 9964 9965 9966 9967 9968 9969 9970 9971 9972 9973 9974 9975 9976 9977 9978 9979 9980 9981 9982 9983 9984 9985 9986 9987 9988 9989 9990 9991 9992 9993 9994 9995 9996 9997 9998 9999 10000 10001 10002 10003 10004 10005 10006 10007 10008 10009 10010 10011 10012 10013 10014 10015 10016 10017 10018 10019 10020 10021 10022 10023 10024 10025 10026 10027 10028 10029 10030 10031 10032 10033 10034 10035 10036 10037 10038 10039 10040 10041 10042 10043 10044 10045 10046 10047 10048 10049 10050 10051 10052 10053 10054 10055 10056 10057 10058 10059 10060 10061 10062 10063 10064 10065 10066 10067 10068 10069 10070 10071 10072 10073 10074 10075 10076 10077 10078 10079 10080 10081 10082 10083 10084 10085 10086 10087 10088 10089 10090 10091 10092 10093 10094 10095 10096 10097 10098 10099 10100 10101 10102 10103 10104 10105 10106 10107 10108 10109 10110 10111 10112 10113 10114 10115 10116 10117 10118 10119 10120 10121 10122 10123 10124 10125 10126 10127 10128 10129 10130 10131 10132 10133 10134 10135 10136 10137 10138 10139 10140 10141 10142 10143 10144 10145 10146 10147 10148 10149 10150 10151 10152 10153 10154 10155 10156 10157 10158 10159 10160 10161 10162 10163 10164 10165 10166 10167 10168 10169 10170 10171 10172 10173 10174 10175 10176 10177 10178 10179 10180 10181 10182 10183 10184 10185 10186 10187 10188 10189 10190 10191 10192 10193 10194 10195 10196 10197 10198 10199 10200 10201 10202 10203 10204 10205 10206 10207 10208 10209 10210 10211 10212 10213 10214 10215 10216 10217 10218 10219 10220 10221 10222 10223 10224 10225 10226 10227 10228 10229 10230 10231 10232 10233 10234 10235 10236 10237 10238 10239 10240 10241 10242 10243 10244 10245 10246 10247 10248 10249 10250 10251 10252 10253 10254 10255 10256 10257 10258 10259 10260 10261 10262 10263 10264 10265 10266 10267 10268 10269 10270 10271 10272 10273 10274 10275 10276 10277 10278 10279 10280 10281 10282 10283 10284 10285 10286 10287 10288 10289 10290 10291 10292 10293 10294 10295 10296 10297 10298 10299
|
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2001-2023 Intel Corporation
*/
#include "ice_common.h"
#include "ice_switch.h"
#include "ice_flex_type.h"
#include "ice_flow.h"
#define ICE_ETH_DA_OFFSET 0
#define ICE_ETH_ETHTYPE_OFFSET 12
#define ICE_ETH_VLAN_TCI_OFFSET 14
#define ICE_MAX_VLAN_ID 0xFFF
#define ICE_IPV6_ETHER_ID 0x86DD
#define ICE_PPP_IPV6_PROTO_ID 0x0057
#define ICE_IPV4_NVGRE_PROTO_ID 0x002F
#define ICE_TCP_PROTO_ID 0x06
#define ICE_GTPU_PROFILE 24
#define ICE_MPLS_ETHER_ID 0x8847
#define ICE_ETH_P_8021Q 0x8100
/* Dummy ethernet header needed in the ice_sw_rule_*
* struct to configure any switch filter rules.
* {DA (6 bytes), SA(6 bytes),
* Ether type (2 bytes for header without VLAN tag) OR
* VLAN tag (4 bytes for header with VLAN tag) }
*
* Word on Hardcoded values
* byte 0 = 0x2: to identify it as locally administered DA MAC
* byte 6 = 0x2: to identify it as locally administered SA MAC
* byte 12 = 0x81 & byte 13 = 0x00:
* In case of VLAN filter first two bytes defines ether type (0x8100)
* and remaining two bytes are placeholder for programming a given VLAN ID
* In case of Ether type filter it is treated as header without VLAN tag
* and byte 12 and 13 is used to program a given Ether type instead
*/
static const u8 dummy_eth_header[DUMMY_ETH_HDR_LEN] = { 0x2, 0, 0, 0, 0, 0,
0x2, 0, 0, 0, 0, 0,
0x81, 0, 0, 0};
static const struct ice_dummy_pkt_offsets dummy_gre_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_ETYPE_OL, 12 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_NVGRE, 34 },
{ ICE_MAC_IL, 42 },
{ ICE_ETYPE_IL, 54 },
{ ICE_IPV4_IL, 56 },
{ ICE_TCP_IL, 76 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_gre_tcp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00, /* ICE_ETYPE_OL 12 */
0x45, 0x00, 0x00, 0x3E, /* ICE_IPV4_OFOS 14 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x2F, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x80, 0x00, 0x65, 0x58, /* ICE_NVGRE 34 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00, /* ICE_ETYPE_IL 54 */
0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 56 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x06, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 76 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x50, 0x02, 0x20, 0x00,
0x00, 0x00, 0x00, 0x00
};
static const struct ice_dummy_pkt_offsets dummy_gre_udp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_ETYPE_OL, 12 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_NVGRE, 34 },
{ ICE_MAC_IL, 42 },
{ ICE_ETYPE_IL, 54 },
{ ICE_IPV4_IL, 56 },
{ ICE_UDP_ILOS, 76 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_gre_udp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00, /* ICE_ETYPE_OL 12 */
0x45, 0x00, 0x00, 0x3E, /* ICE_IPV4_OFOS 14 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x2F, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x80, 0x00, 0x65, 0x58, /* ICE_NVGRE 34 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00, /* ICE_ETYPE_IL 54 */
0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 56 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 76 */
0x00, 0x08, 0x00, 0x00,
};
static const struct ice_dummy_pkt_offsets dummy_udp_tun_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_ETYPE_OL, 12 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_VXLAN, 42 },
{ ICE_GENEVE, 42 },
{ ICE_VXLAN_GPE, 42 },
{ ICE_MAC_IL, 50 },
{ ICE_ETYPE_IL, 62 },
{ ICE_IPV4_IL, 64 },
{ ICE_TCP_IL, 84 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_udp_tun_tcp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00, /* ICE_ETYPE_OL 12 */
0x45, 0x00, 0x00, 0x5a, /* ICE_IPV4_OFOS 14 */
0x00, 0x01, 0x00, 0x00,
0x40, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x12, 0xb5, /* ICE_UDP_OF 34 */
0x00, 0x46, 0x00, 0x00,
0x00, 0x00, 0x65, 0x58, /* ICE_VXLAN 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00, /* ICE_ETYPE_IL 62*/
0x45, 0x00, 0x00, 0x28, /* ICE_IPV4_IL 64 */
0x00, 0x01, 0x00, 0x00,
0x40, 0x06, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 84 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x50, 0x02, 0x20, 0x00,
0x00, 0x00, 0x00, 0x00
};
static const struct ice_dummy_pkt_offsets dummy_udp_tun_udp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_ETYPE_OL, 12 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_VXLAN, 42 },
{ ICE_GENEVE, 42 },
{ ICE_VXLAN_GPE, 42 },
{ ICE_MAC_IL, 50 },
{ ICE_ETYPE_IL, 62 },
{ ICE_IPV4_IL, 64 },
{ ICE_UDP_ILOS, 84 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_udp_tun_udp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00, /* ICE_ETYPE_OL 12 */
0x45, 0x00, 0x00, 0x4e, /* ICE_IPV4_OFOS 14 */
0x00, 0x01, 0x00, 0x00,
0x00, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x12, 0xb5, /* ICE_UDP_OF 34 */
0x00, 0x3a, 0x00, 0x00,
0x00, 0x00, 0x65, 0x58, /* ICE_VXLAN 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00, /* ICE_ETYPE_IL 62 */
0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_IL 64 */
0x00, 0x01, 0x00, 0x00,
0x00, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 84 */
0x00, 0x08, 0x00, 0x00,
};
static const struct ice_dummy_pkt_offsets
dummy_gre_ipv6_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_ETYPE_OL, 12 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_NVGRE, 34 },
{ ICE_MAC_IL, 42 },
{ ICE_ETYPE_IL, 54 },
{ ICE_IPV6_IL, 56 },
{ ICE_TCP_IL, 96 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_gre_ipv6_tcp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00, /* ICE_ETYPE_OL 12 */
0x45, 0x00, 0x00, 0x66, /* ICE_IPV4_OFOS 14 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x2F, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x80, 0x00, 0x65, 0x58, /* ICE_NVGRE 34 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xdd, /* ICE_ETYPE_IL 54 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_IL 56 */
0x00, 0x08, 0x06, 0x40,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 96 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x50, 0x02, 0x20, 0x00,
0x00, 0x00, 0x00, 0x00
};
static const struct ice_dummy_pkt_offsets
dummy_gre_ipv6_udp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_ETYPE_OL, 12 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_NVGRE, 34 },
{ ICE_MAC_IL, 42 },
{ ICE_ETYPE_IL, 54 },
{ ICE_IPV6_IL, 56 },
{ ICE_UDP_ILOS, 96 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_gre_ipv6_udp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00, /* ICE_ETYPE_OL 12 */
0x45, 0x00, 0x00, 0x5a, /* ICE_IPV4_OFOS 14 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x2F, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x80, 0x00, 0x65, 0x58, /* ICE_NVGRE 34 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xdd, /* ICE_ETYPE_IL 54 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_IL 56 */
0x00, 0x08, 0x11, 0x40,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 96 */
0x00, 0x08, 0x00, 0x00,
};
static const struct ice_dummy_pkt_offsets
dummy_udp_tun_ipv6_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_ETYPE_OL, 12 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_VXLAN, 42 },
{ ICE_GENEVE, 42 },
{ ICE_VXLAN_GPE, 42 },
{ ICE_MAC_IL, 50 },
{ ICE_ETYPE_IL, 62 },
{ ICE_IPV6_IL, 64 },
{ ICE_TCP_IL, 104 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_udp_tun_ipv6_tcp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00, /* ICE_ETYPE_OL 12 */
0x45, 0x00, 0x00, 0x6e, /* ICE_IPV4_OFOS 14 */
0x00, 0x01, 0x00, 0x00,
0x40, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x12, 0xb5, /* ICE_UDP_OF 34 */
0x00, 0x5a, 0x00, 0x00,
0x00, 0x00, 0x65, 0x58, /* ICE_VXLAN 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xdd, /* ICE_ETYPE_IL 62 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_IL 64 */
0x00, 0x08, 0x06, 0x40,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 104 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x50, 0x02, 0x20, 0x00,
0x00, 0x00, 0x00, 0x00
};
static const struct ice_dummy_pkt_offsets
dummy_udp_tun_ipv6_udp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_ETYPE_OL, 12 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_VXLAN, 42 },
{ ICE_GENEVE, 42 },
{ ICE_VXLAN_GPE, 42 },
{ ICE_MAC_IL, 50 },
{ ICE_ETYPE_IL, 62 },
{ ICE_IPV6_IL, 64 },
{ ICE_UDP_ILOS, 104 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_udp_tun_ipv6_udp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00, /* ICE_ETYPE_OL 12 */
0x45, 0x00, 0x00, 0x62, /* ICE_IPV4_OFOS 14 */
0x00, 0x01, 0x00, 0x00,
0x00, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x12, 0xb5, /* ICE_UDP_OF 34 */
0x00, 0x4e, 0x00, 0x00,
0x00, 0x00, 0x65, 0x58, /* ICE_VXLAN 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xdd, /* ICE_ETYPE_IL 62 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_IL 64 */
0x00, 0x08, 0x11, 0x40,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 104 */
0x00, 0x08, 0x00, 0x00,
};
/* offset info for MAC + IPv4 + UDP dummy packet */
static const struct ice_dummy_pkt_offsets dummy_udp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_ETYPE_OL, 12 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_ILOS, 34 },
{ ICE_PROTOCOL_LAST, 0 },
};
/* Dummy packet for MAC + IPv4 + UDP */
static const u8 dummy_udp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00, /* ICE_ETYPE_OL 12 */
0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_OFOS 14 */
0x00, 0x01, 0x00, 0x00,
0x00, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 34 */
0x00, 0x08, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
/* offset info for MAC + VLAN + IPv4 + UDP dummy packet */
static const struct ice_dummy_pkt_offsets dummy_vlan_udp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_OFOS, 12 },
{ ICE_ETYPE_OL, 16 },
{ ICE_IPV4_OFOS, 18 },
{ ICE_UDP_ILOS, 38 },
{ ICE_PROTOCOL_LAST, 0 },
};
/* C-tag (801.1Q), IPv4:UDP dummy packet */
static const u8 dummy_vlan_udp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
0x08, 0x00, /* ICE_ETYPE_OL 16 */
0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_OFOS 18 */
0x00, 0x01, 0x00, 0x00,
0x00, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 38 */
0x00, 0x08, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
/* offset info for MAC + IPv4 + TCP dummy packet */
static const struct ice_dummy_pkt_offsets dummy_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_ETYPE_OL, 12 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_TCP_IL, 34 },
{ ICE_PROTOCOL_LAST, 0 },
};
/* Dummy packet for MAC + IPv4 + TCP */
static const u8 dummy_tcp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00, /* ICE_ETYPE_OL 12 */
0x45, 0x00, 0x00, 0x28, /* ICE_IPV4_OFOS 14 */
0x00, 0x01, 0x00, 0x00,
0x00, 0x06, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 34 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x50, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
/* offset info for MAC + VLAN (C-tag, 802.1Q) + IPv4 + TCP dummy packet */
static const struct ice_dummy_pkt_offsets dummy_vlan_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_OFOS, 12 },
{ ICE_ETYPE_OL, 16 },
{ ICE_IPV4_OFOS, 18 },
{ ICE_TCP_IL, 38 },
{ ICE_PROTOCOL_LAST, 0 },
};
/* C-tag (801.1Q), IPv4:TCP dummy packet */
static const u8 dummy_vlan_tcp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
0x08, 0x00, /* ICE_ETYPE_OL 16 */
0x45, 0x00, 0x00, 0x28, /* ICE_IPV4_OFOS 18 */
0x00, 0x01, 0x00, 0x00,
0x00, 0x06, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 38 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x50, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
static const struct ice_dummy_pkt_offsets dummy_tcp_ipv6_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_ETYPE_OL, 12 },
{ ICE_IPV6_OFOS, 14 },
{ ICE_TCP_IL, 54 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_tcp_ipv6_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xDD, /* ICE_ETYPE_OL 12 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 40 */
0x00, 0x14, 0x06, 0x00, /* Next header is TCP */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 54 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x50, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
/* C-tag (802.1Q): IPv6 + TCP */
static const struct ice_dummy_pkt_offsets
dummy_vlan_tcp_ipv6_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_OFOS, 12 },
{ ICE_ETYPE_OL, 16 },
{ ICE_IPV6_OFOS, 18 },
{ ICE_TCP_IL, 58 },
{ ICE_PROTOCOL_LAST, 0 },
};
/* C-tag (802.1Q), IPv6 + TCP dummy packet */
static const u8 dummy_vlan_tcp_ipv6_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
0x86, 0xDD, /* ICE_ETYPE_OL 16 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 18 */
0x00, 0x14, 0x06, 0x00, /* Next header is TCP */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 58 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x50, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
/* IPv6 + UDP */
static const struct ice_dummy_pkt_offsets dummy_udp_ipv6_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_ETYPE_OL, 12 },
{ ICE_IPV6_OFOS, 14 },
{ ICE_UDP_ILOS, 54 },
{ ICE_PROTOCOL_LAST, 0 },
};
/* IPv6 + UDP dummy packet */
static const u8 dummy_udp_ipv6_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xDD, /* ICE_ETYPE_OL 12 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 40 */
0x00, 0x10, 0x11, 0x00, /* Next header UDP */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 54 */
0x00, 0x10, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* needed for ESP packets */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
/* C-tag (802.1Q): IPv6 + UDP */
static const struct ice_dummy_pkt_offsets
dummy_vlan_udp_ipv6_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_OFOS, 12 },
{ ICE_ETYPE_OL, 16 },
{ ICE_IPV6_OFOS, 18 },
{ ICE_UDP_ILOS, 58 },
{ ICE_PROTOCOL_LAST, 0 },
};
/* C-tag (802.1Q), IPv6 + UDP dummy packet */
static const u8 dummy_vlan_udp_ipv6_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x81, 0x00, 0x00, 0x00,/* ICE_VLAN_OFOS 12 */
0x86, 0xDD, /* ICE_ETYPE_OL 16 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 18 */
0x00, 0x08, 0x11, 0x00, /* Next header UDP */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 58 */
0x00, 0x08, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
/* Outer IPv4 + Outer UDP + GTP + Inner IPv4 + Inner TCP */
static const struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv4_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_GTP, 42 },
{ ICE_IPV4_IL, 62 },
{ ICE_TCP_IL, 82 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv4_gtpu_ipv4_tcp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* Ethernet 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00,
0x45, 0x00, 0x00, 0x58, /* IP 14 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x08, 0x68, /* UDP 34 */
0x00, 0x44, 0x00, 0x00,
0x34, 0xff, 0x00, 0x34, /* GTP-U Header 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x85,
0x02, 0x00, 0x00, 0x00, /* GTP_PDUSession_ExtensionHeader 54 */
0x00, 0x00, 0x00, 0x00,
0x45, 0x00, 0x00, 0x28, /* IP 62 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x06, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* TCP 82 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x50, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
/* Outer IPv4 + Outer UDP + GTP + Inner IPv4 + Inner UDP */
static const struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv4_udp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_GTP, 42 },
{ ICE_IPV4_IL, 62 },
{ ICE_UDP_ILOS, 82 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv4_gtpu_ipv4_udp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* Ethernet 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00,
0x45, 0x00, 0x00, 0x4c, /* IP 14 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x08, 0x68, /* UDP 34 */
0x00, 0x38, 0x00, 0x00,
0x34, 0xff, 0x00, 0x28, /* GTP-U Header 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x85,
0x02, 0x00, 0x00, 0x00, /* GTP_PDUSession_ExtensionHeader 54 */
0x00, 0x00, 0x00, 0x00,
0x45, 0x00, 0x00, 0x1c, /* IP 62 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* UDP 82 */
0x00, 0x08, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
/* Outer IPv6 + Outer UDP + GTP + Inner IPv4 + Inner TCP */
static const struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv6_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_GTP, 42 },
{ ICE_IPV6_IL, 62 },
{ ICE_TCP_IL, 102 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv4_gtpu_ipv6_tcp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* Ethernet 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00,
0x45, 0x00, 0x00, 0x6c, /* IP 14 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x08, 0x68, /* UDP 34 */
0x00, 0x58, 0x00, 0x00,
0x34, 0xff, 0x00, 0x48, /* GTP-U Header 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x85,
0x02, 0x00, 0x00, 0x00, /* GTP_PDUSession_ExtensionHeader 54 */
0x00, 0x00, 0x00, 0x00,
0x60, 0x00, 0x00, 0x00, /* IPv6 62 */
0x00, 0x14, 0x06, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* TCP 102 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x50, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
static const struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv6_udp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_GTP, 42 },
{ ICE_IPV6_IL, 62 },
{ ICE_UDP_ILOS, 102 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv4_gtpu_ipv6_udp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* Ethernet 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00,
0x45, 0x00, 0x00, 0x60, /* IP 14 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x08, 0x68, /* UDP 34 */
0x00, 0x4c, 0x00, 0x00,
0x34, 0xff, 0x00, 0x3c, /* GTP-U Header 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x85,
0x02, 0x00, 0x00, 0x00, /* GTP_PDUSession_ExtensionHeader 54 */
0x00, 0x00, 0x00, 0x00,
0x60, 0x00, 0x00, 0x00, /* IPv6 62 */
0x00, 0x08, 0x11, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* UDP 102 */
0x00, 0x08, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
static const struct ice_dummy_pkt_offsets dummy_ipv6_gtpu_ipv4_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV6_OFOS, 14 },
{ ICE_UDP_OF, 54 },
{ ICE_GTP, 62 },
{ ICE_IPV4_IL, 82 },
{ ICE_TCP_IL, 102 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv6_gtpu_ipv4_tcp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* Ethernet 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xdd,
0x60, 0x00, 0x00, 0x00, /* IPv6 14 */
0x00, 0x44, 0x11, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x08, 0x68, /* UDP 54 */
0x00, 0x44, 0x00, 0x00,
0x34, 0xff, 0x00, 0x34, /* GTP-U Header 62 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x85,
0x02, 0x00, 0x00, 0x00, /* GTP_PDUSession_ExtensionHeader 74 */
0x00, 0x00, 0x00, 0x00,
0x45, 0x00, 0x00, 0x28, /* IP 82 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x06, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* TCP 102 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x50, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
static const struct ice_dummy_pkt_offsets dummy_ipv6_gtpu_ipv4_udp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV6_OFOS, 14 },
{ ICE_UDP_OF, 54 },
{ ICE_GTP, 62 },
{ ICE_IPV4_IL, 82 },
{ ICE_UDP_ILOS, 102 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv6_gtpu_ipv4_udp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* Ethernet 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xdd,
0x60, 0x00, 0x00, 0x00, /* IPv6 14 */
0x00, 0x38, 0x11, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x08, 0x68, /* UDP 54 */
0x00, 0x38, 0x00, 0x00,
0x34, 0xff, 0x00, 0x28, /* GTP-U Header 62 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x85,
0x02, 0x00, 0x00, 0x00, /* GTP_PDUSession_ExtensionHeader 74 */
0x00, 0x00, 0x00, 0x00,
0x45, 0x00, 0x00, 0x1c, /* IP 82 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* UDP 102 */
0x00, 0x08, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
static const struct ice_dummy_pkt_offsets dummy_ipv6_gtpu_ipv6_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV6_OFOS, 14 },
{ ICE_UDP_OF, 54 },
{ ICE_GTP, 62 },
{ ICE_IPV6_IL, 82 },
{ ICE_TCP_IL, 122 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv6_gtpu_ipv6_tcp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* Ethernet 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xdd,
0x60, 0x00, 0x00, 0x00, /* IPv6 14 */
0x00, 0x58, 0x11, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x08, 0x68, /* UDP 54 */
0x00, 0x58, 0x00, 0x00,
0x34, 0xff, 0x00, 0x48, /* GTP-U Header 62 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x85,
0x02, 0x00, 0x00, 0x00, /* GTP_PDUSession_ExtensionHeader 74 */
0x00, 0x00, 0x00, 0x00,
0x60, 0x00, 0x00, 0x00, /* IPv6 82 */
0x00, 0x14, 0x06, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* TCP 122 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x50, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
static const struct ice_dummy_pkt_offsets dummy_ipv6_gtpu_ipv6_udp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV6_OFOS, 14 },
{ ICE_UDP_OF, 54 },
{ ICE_GTP, 62 },
{ ICE_IPV6_IL, 82 },
{ ICE_UDP_ILOS, 122 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv6_gtpu_ipv6_udp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* Ethernet 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xdd,
0x60, 0x00, 0x00, 0x00, /* IPv6 14 */
0x00, 0x4c, 0x11, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x08, 0x68, /* UDP 54 */
0x00, 0x4c, 0x00, 0x00,
0x34, 0xff, 0x00, 0x3c, /* GTP-U Header 62 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x85,
0x02, 0x00, 0x00, 0x00, /* GTP_PDUSession_ExtensionHeader 74 */
0x00, 0x00, 0x00, 0x00,
0x60, 0x00, 0x00, 0x00, /* IPv6 82 */
0x00, 0x08, 0x11, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* UDP 122 */
0x00, 0x08, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
static const u8 dummy_ipv4_gtpu_ipv4_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00,
0x45, 0x00, 0x00, 0x44, /* ICE_IPV4_OFOS 14 */
0x00, 0x00, 0x40, 0x00,
0x40, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x68, 0x08, 0x68, /* ICE_UDP_OF 34 */
0x00, 0x00, 0x00, 0x00,
0x34, 0xff, 0x00, 0x28, /* ICE_GTP 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x85,
0x02, 0x00, 0x00, 0x00, /* PDU Session extension header */
0x00, 0x00, 0x00, 0x00,
0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 62 */
0x00, 0x00, 0x40, 0x00,
0x40, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00,
};
static const struct
ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv4_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_GTP, 42 },
{ ICE_IPV4_IL, 62 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv6_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_GTP, 42 },
{ ICE_IPV6_IL, 62 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv4_gtpu_ipv6_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00,
0x45, 0x00, 0x00, 0x58, /* ICE_IPV4_OFOS 14 */
0x00, 0x00, 0x40, 0x00,
0x40, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x68, 0x08, 0x68, /* ICE_UDP_OF 34 */
0x00, 0x00, 0x00, 0x00,
0x34, 0xff, 0x00, 0x28, /* ICE_GTP 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x85,
0x02, 0x00, 0x00, 0x00, /* PDU Session extension header */
0x00, 0x00, 0x00, 0x00,
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_IL 62 */
0x00, 0x00, 0x3b, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00,
};
static const struct ice_dummy_pkt_offsets dummy_ipv6_gtpu_ipv4_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV6_OFOS, 14 },
{ ICE_UDP_OF, 54 },
{ ICE_GTP, 62 },
{ ICE_IPV4_IL, 82 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv6_gtpu_ipv4_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xdd,
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 14 */
0x00, 0x58, 0x11, 0x00, /* Next header UDP*/
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x68, 0x08, 0x68, /* ICE_UDP_OF 54 */
0x00, 0x00, 0x00, 0x00,
0x34, 0xff, 0x00, 0x28, /* ICE_GTP 62 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x85,
0x02, 0x00, 0x00, 0x00, /* PDU Session extension header */
0x00, 0x00, 0x00, 0x00,
0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 82 */
0x00, 0x00, 0x40, 0x00,
0x40, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00,
};
static const struct ice_dummy_pkt_offsets dummy_ipv6_gtpu_ipv6_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV6_OFOS, 14 },
{ ICE_UDP_OF, 54 },
{ ICE_GTP, 62 },
{ ICE_IPV6_IL, 82 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv6_gtpu_ipv6_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xdd,
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 14 */
0x00, 0x6c, 0x11, 0x00, /* Next header UDP*/
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x68, 0x08, 0x68, /* ICE_UDP_OF 54 */
0x00, 0x00, 0x00, 0x00,
0x34, 0xff, 0x00, 0x28, /* ICE_GTP 62 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x85,
0x02, 0x00, 0x00, 0x00, /* PDU Session extension header */
0x00, 0x00, 0x00, 0x00,
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFIL 82 */
0x00, 0x00, 0x3b, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00,
};
static const
struct ice_dummy_pkt_offsets dummy_ipv4_gtp_no_pay_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_GTP_NO_PAY, 42 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const
struct ice_dummy_pkt_offsets dummy_ipv6_gtp_no_pay_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV6_OFOS, 14 },
{ ICE_UDP_OF, 54 },
{ ICE_GTP_NO_PAY, 62 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv6_gtp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xdd,
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 14 */
0x00, 0x6c, 0x11, 0x00, /* Next header UDP*/
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x68, 0x08, 0x68, /* ICE_UDP_OF 54 */
0x00, 0x00, 0x00, 0x00,
0x30, 0x00, 0x00, 0x28, /* ICE_GTP 62 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00,
};
static const struct ice_dummy_pkt_offsets dummy_qinq_ipv4_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_EX, 12 },
{ ICE_VLAN_IN, 16 },
{ ICE_ETYPE_OL, 20 },
{ ICE_IPV4_OFOS, 22 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_qinq_ipv4_pkt[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
0x08, 0x00, /* ICE_ETYPE_OL 20 */
0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_OFOS 22 */
0x00, 0x01, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
static const
struct ice_dummy_pkt_offsets dummy_qinq_ipv4_udp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_EX, 12 },
{ ICE_VLAN_IN, 16 },
{ ICE_ETYPE_OL, 20 },
{ ICE_IPV4_OFOS, 22 },
{ ICE_UDP_ILOS, 42 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_qinq_ipv4_udp_pkt[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
0x08, 0x00, /* ICE_ETYPE_OL 20 */
0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_OFOS 22 */
0x00, 0x01, 0x00, 0x00,
0x00, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 42 */
0x00, 0x08, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
static const
struct ice_dummy_pkt_offsets dummy_qinq_ipv4_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_EX, 12 },
{ ICE_VLAN_IN, 16 },
{ ICE_ETYPE_OL, 20 },
{ ICE_IPV4_OFOS, 22 },
{ ICE_TCP_IL, 42 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_qinq_ipv4_tcp_pkt[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
0x08, 0x00, /* ICE_ETYPE_OL 20 */
0x45, 0x00, 0x00, 0x28, /* ICE_IPV4_OFOS 22 */
0x00, 0x01, 0x00, 0x00,
0x00, 0x06, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x50, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
static const struct ice_dummy_pkt_offsets dummy_qinq_ipv6_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_EX, 12 },
{ ICE_VLAN_IN, 16 },
{ ICE_ETYPE_OL, 20 },
{ ICE_IPV6_OFOS, 22 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_qinq_ipv6_pkt[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
0x86, 0xDD, /* ICE_ETYPE_OL 20 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 22 */
0x00, 0x00, 0x3b, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
static const
struct ice_dummy_pkt_offsets dummy_qinq_ipv6_udp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_EX, 12 },
{ ICE_VLAN_IN, 16 },
{ ICE_ETYPE_OL, 20 },
{ ICE_IPV6_OFOS, 22 },
{ ICE_UDP_ILOS, 62 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_qinq_ipv6_udp_pkt[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
0x86, 0xDD, /* ICE_ETYPE_OL 20 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 22 */
0x00, 0x08, 0x11, 0x00, /* Next header UDP */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 62 */
0x00, 0x08, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
static const
struct ice_dummy_pkt_offsets dummy_qinq_ipv6_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_EX, 12 },
{ ICE_VLAN_IN, 16 },
{ ICE_ETYPE_OL, 20 },
{ ICE_IPV6_OFOS, 22 },
{ ICE_TCP_IL, 62 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_qinq_ipv6_tcp_pkt[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
0x86, 0xDD, /* ICE_ETYPE_OL 20 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 22 */
0x00, 0x14, 0x06, 0x00, /* Next header TCP */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 62 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x50, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
/* offset info for MAC + MPLS dummy packet */
static const struct ice_dummy_pkt_offsets dummy_mpls_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_ETYPE_OL, 12 },
{ ICE_PROTOCOL_LAST, 0 },
};
/* Dummy packet for MAC + MPLS */
static const u8 dummy_mpls_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x88, 0x47, /* ICE_ETYPE_OL 12 */
0x00, 0x00, 0x01, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
static const struct ice_dummy_pkt_offsets dummy_udp_gtp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_GTP, 42 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_udp_gtp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00,
0x45, 0x00, 0x00, 0x30, /* ICE_IPV4_OFOS 14 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x08, 0x68, /* ICE_UDP_OF 34 */
0x00, 0x1c, 0x00, 0x00,
0x34, 0xff, 0x00, 0x0c, /* ICE_GTP 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x85,
0x02, 0x00, 0x00, 0x00, /* PDU Session extension header */
0x00, 0x00, 0x00, 0x00,
};
static const struct ice_dummy_pkt_offsets dummy_pppoe_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_OFOS, 12 },
{ ICE_ETYPE_OL, 16 },
{ ICE_PPPOE, 18 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const struct ice_dummy_pkt_offsets dummy_pppoe_packet_ipv4_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_OFOS, 12 },
{ ICE_ETYPE_OL, 16 },
{ ICE_PPPOE, 18 },
{ ICE_IPV4_OFOS, 26 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_pppoe_ipv4_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
0x88, 0x64, /* ICE_ETYPE_OL 16 */
0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */
0x00, 0x16,
0x00, 0x21, /* PPP Link Layer 24 */
0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 26 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 bytes alignment */
};
static const struct ice_dummy_pkt_offsets dummy_pppoe_packet_ipv6_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_OFOS, 12 },
{ ICE_ETYPE_OL, 16 },
{ ICE_PPPOE, 18 },
{ ICE_IPV6_OFOS, 26 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_pppoe_ipv6_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
0x88, 0x64, /* ICE_ETYPE_OL 16 */
0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */
0x00, 0x2a,
0x00, 0x57, /* PPP Link Layer 24 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 26 */
0x00, 0x00, 0x3b, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 bytes alignment */
};
static const struct ice_dummy_pkt_offsets dummy_ipv4_esp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_ESP, 34 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv4_esp_pkt[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00,
0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_IL 14 */
0x00, 0x00, 0x40, 0x00,
0x40, 0x32, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_ESP 34 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 bytes alignment */
};
static const struct ice_dummy_pkt_offsets dummy_ipv6_esp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV6_OFOS, 14 },
{ ICE_ESP, 54 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv6_esp_pkt[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xDD,
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 14 */
0x00, 0x08, 0x32, 0x00, /* Next header ESP */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_ESP 54 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 bytes alignment */
};
static const struct ice_dummy_pkt_offsets dummy_ipv4_ah_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_AH, 34 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv4_ah_pkt[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00,
0x45, 0x00, 0x00, 0x20, /* ICE_IPV4_IL 14 */
0x00, 0x00, 0x40, 0x00,
0x40, 0x33, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_AH 34 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 bytes alignment */
};
static const struct ice_dummy_pkt_offsets dummy_ipv6_ah_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV6_OFOS, 14 },
{ ICE_AH, 54 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv6_ah_pkt[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xDD,
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 14 */
0x00, 0x0c, 0x33, 0x00, /* Next header AH */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_AH 54 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 bytes alignment */
};
static const struct ice_dummy_pkt_offsets dummy_ipv4_nat_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_ILOS, 34 },
{ ICE_NAT_T, 42 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv4_nat_pkt[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00,
0x45, 0x00, 0x00, 0x24, /* ICE_IPV4_IL 14 */
0x00, 0x00, 0x40, 0x00,
0x40, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x11, 0x94, /* ICE_NAT_T 34 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 bytes alignment */
};
static const struct ice_dummy_pkt_offsets dummy_ipv6_nat_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV6_OFOS, 14 },
{ ICE_UDP_ILOS, 54 },
{ ICE_NAT_T, 62 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv6_nat_pkt[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xDD,
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 14 */
0x00, 0x10, 0x11, 0x00, /* Next header NAT_T */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x11, 0x94, /* ICE_NAT_T 54 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 bytes alignment */
};
static const struct ice_dummy_pkt_offsets dummy_qinq_pppoe_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_EX, 12 },
{ ICE_VLAN_IN, 16 },
{ ICE_ETYPE_OL, 20 },
{ ICE_PPPOE, 22 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const
struct ice_dummy_pkt_offsets dummy_qinq_pppoe_ipv4_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_EX, 12 },
{ ICE_VLAN_IN, 16 },
{ ICE_ETYPE_OL, 20 },
{ ICE_PPPOE, 22 },
{ ICE_IPV4_OFOS, 30 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_qinq_pppoe_ipv4_pkt[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
0x88, 0x64, /* ICE_ETYPE_OL 20 */
0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 22 */
0x00, 0x16,
0x00, 0x21, /* PPP Link Layer 28 */
0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_OFOS 30 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
static const
struct ice_dummy_pkt_offsets dummy_qinq_pppoe_packet_ipv6_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_EX, 12 },
{ ICE_VLAN_IN, 16 },
{ ICE_ETYPE_OL, 20 },
{ ICE_PPPOE, 22 },
{ ICE_IPV6_OFOS, 30 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_qinq_pppoe_ipv6_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
0x88, 0x64, /* ICE_ETYPE_OL 20 */
0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 22 */
0x00, 0x2a,
0x00, 0x57, /* PPP Link Layer 28*/
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 30 */
0x00, 0x00, 0x3b, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 bytes alignment */
};
static const struct ice_dummy_pkt_offsets dummy_ipv4_l2tpv3_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_ETYPE_OL, 12 },
{ ICE_IPV4_OFOS, 14 },
{ ICE_L2TPV3, 34 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv4_l2tpv3_pkt[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x08, 0x00, /* ICE_ETYPE_OL 12 */
0x45, 0x00, 0x00, 0x20, /* ICE_IPV4_IL 14 */
0x00, 0x00, 0x40, 0x00,
0x40, 0x73, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_L2TPV3 34 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 bytes alignment */
};
static const struct ice_dummy_pkt_offsets dummy_ipv6_l2tpv3_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_ETYPE_OL, 12 },
{ ICE_IPV6_OFOS, 14 },
{ ICE_L2TPV3, 54 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_ipv6_l2tpv3_pkt[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x86, 0xDD, /* ICE_ETYPE_OL 12 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_IL 14 */
0x00, 0x0c, 0x73, 0x40,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_L2TPV3 54 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 bytes alignment */
};
static const
struct ice_dummy_pkt_offsets dummy_pppoe_ipv4_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_OFOS, 12 },
{ ICE_ETYPE_OL, 16 },
{ ICE_PPPOE, 18 },
{ ICE_IPV4_OFOS, 26 },
{ ICE_TCP_IL, 46 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_pppoe_ipv4_tcp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
0x88, 0x64, /* ICE_ETYPE_OL 16 */
0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */
0x00, 0x16,
0x00, 0x21, /* PPP Link Layer 24 */
0x45, 0x00, 0x00, 0x28, /* ICE_IPV4_OFOS 26 */
0x00, 0x01, 0x00, 0x00,
0x00, 0x06, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 46 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x50, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 bytes alignment */
};
static const
struct ice_dummy_pkt_offsets dummy_pppoe_ipv4_udp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_OFOS, 12 },
{ ICE_ETYPE_OL, 16 },
{ ICE_PPPOE, 18 },
{ ICE_IPV4_OFOS, 26 },
{ ICE_UDP_ILOS, 46 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_pppoe_ipv4_udp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
0x88, 0x64, /* ICE_ETYPE_OL 16 */
0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */
0x00, 0x16,
0x00, 0x21, /* PPP Link Layer 24 */
0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_OFOS 26 */
0x00, 0x01, 0x00, 0x00,
0x00, 0x11, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 46 */
0x00, 0x08, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 bytes alignment */
};
static const
struct ice_dummy_pkt_offsets dummy_pppoe_ipv6_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_OFOS, 12 },
{ ICE_ETYPE_OL, 16 },
{ ICE_PPPOE, 18 },
{ ICE_IPV6_OFOS, 26 },
{ ICE_TCP_IL, 66 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_pppoe_ipv6_tcp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
0x88, 0x64, /* ICE_ETYPE_OL 16 */
0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */
0x00, 0x2a,
0x00, 0x57, /* PPP Link Layer 24 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 26 */
0x00, 0x14, 0x06, 0x00, /* Next header is TCP */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 66 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x50, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 bytes alignment */
};
static const
struct ice_dummy_pkt_offsets dummy_pppoe_ipv6_udp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_OFOS, 12 },
{ ICE_ETYPE_OL, 16 },
{ ICE_PPPOE, 18 },
{ ICE_IPV6_OFOS, 26 },
{ ICE_UDP_ILOS, 66 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const u8 dummy_pppoe_ipv6_udp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
0x88, 0x64, /* ICE_ETYPE_OL 16 */
0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */
0x00, 0x2a,
0x00, 0x57, /* PPP Link Layer 24 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 26 */
0x00, 0x08, 0x11, 0x00, /* Next header UDP*/
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 66 */
0x00, 0x08, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 bytes alignment */
};
/* this is a recipe to profile association bitmap */
static ice_declare_bitmap(recipe_to_profile[ICE_MAX_NUM_RECIPES],
ICE_MAX_NUM_PROFILES);
/* this is a profile to recipe association bitmap */
static ice_declare_bitmap(profile_to_recipe[ICE_MAX_NUM_PROFILES],
ICE_MAX_NUM_RECIPES);
static void ice_get_recp_to_prof_map(struct ice_hw *hw);
/**
* ice_collect_result_idx - copy result index values
* @buf: buffer that contains the result index
* @recp: the recipe struct to copy data into
*/
static void ice_collect_result_idx(struct ice_aqc_recipe_data_elem *buf,
struct ice_sw_recipe *recp)
{
if (buf->content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
ice_set_bit(buf->content.result_indx &
~ICE_AQ_RECIPE_RESULT_EN, recp->res_idxs);
}
static struct ice_prof_type_entry ice_prof_type_tbl[ICE_GTPU_PROFILE] = {
{ ICE_PROFID_IPV4_GTPU_IPV4_OTHER, ICE_SW_TUN_IPV4_GTPU_IPV4},
{ ICE_PROFID_IPV4_GTPU_IPV4_UDP, ICE_SW_TUN_IPV4_GTPU_IPV4_UDP},
{ ICE_PROFID_IPV4_GTPU_IPV4_TCP, ICE_SW_TUN_IPV4_GTPU_IPV4_TCP},
{ ICE_PROFID_IPV4_GTPU_EH_IPV4_OTHER, ICE_SW_TUN_IPV4_GTPU_EH_IPV4},
{ ICE_PROFID_IPV4_GTPU_EH_IPV4_UDP, ICE_SW_TUN_IPV4_GTPU_EH_IPV4_UDP},
{ ICE_PROFID_IPV4_GTPU_EH_IPV4_TCP, ICE_SW_TUN_IPV4_GTPU_EH_IPV4_TCP},
{ ICE_PROFID_IPV4_GTPU_IPV6_OTHER, ICE_SW_TUN_IPV4_GTPU_IPV6},
{ ICE_PROFID_IPV4_GTPU_IPV6_UDP, ICE_SW_TUN_IPV4_GTPU_IPV6_UDP},
{ ICE_PROFID_IPV4_GTPU_IPV6_TCP, ICE_SW_TUN_IPV4_GTPU_IPV6_TCP},
{ ICE_PROFID_IPV4_GTPU_EH_IPV6_OTHER, ICE_SW_TUN_IPV4_GTPU_EH_IPV6},
{ ICE_PROFID_IPV4_GTPU_EH_IPV6_UDP, ICE_SW_TUN_IPV4_GTPU_EH_IPV6_UDP},
{ ICE_PROFID_IPV4_GTPU_EH_IPV6_TCP, ICE_SW_TUN_IPV4_GTPU_EH_IPV6_TCP},
{ ICE_PROFID_IPV6_GTPU_IPV4_OTHER, ICE_SW_TUN_IPV6_GTPU_IPV4},
{ ICE_PROFID_IPV6_GTPU_IPV4_UDP, ICE_SW_TUN_IPV6_GTPU_IPV4_UDP},
{ ICE_PROFID_IPV6_GTPU_IPV4_TCP, ICE_SW_TUN_IPV6_GTPU_IPV4_TCP},
{ ICE_PROFID_IPV6_GTPU_EH_IPV4_OTHER, ICE_SW_TUN_IPV6_GTPU_EH_IPV4},
{ ICE_PROFID_IPV6_GTPU_EH_IPV4_UDP, ICE_SW_TUN_IPV6_GTPU_EH_IPV4_UDP},
{ ICE_PROFID_IPV6_GTPU_EH_IPV4_TCP, ICE_SW_TUN_IPV6_GTPU_EH_IPV4_TCP},
{ ICE_PROFID_IPV6_GTPU_IPV6_OTHER, ICE_SW_TUN_IPV6_GTPU_IPV6},
{ ICE_PROFID_IPV6_GTPU_IPV6_UDP, ICE_SW_TUN_IPV6_GTPU_IPV6_UDP},
{ ICE_PROFID_IPV6_GTPU_IPV6_TCP, ICE_SW_TUN_IPV6_GTPU_IPV6_TCP},
{ ICE_PROFID_IPV6_GTPU_EH_IPV6_OTHER, ICE_SW_TUN_IPV6_GTPU_EH_IPV6},
{ ICE_PROFID_IPV6_GTPU_EH_IPV6_UDP, ICE_SW_TUN_IPV6_GTPU_EH_IPV6_UDP},
{ ICE_PROFID_IPV6_GTPU_EH_IPV6_TCP, ICE_SW_TUN_IPV6_GTPU_EH_IPV6_TCP},
};
/**
* ice_get_tun_type_for_recipe - get tunnel type for the recipe
* @rid: recipe ID that we are populating
* @vlan: flag of vlan protocol
*/
static enum ice_sw_tunnel_type ice_get_tun_type_for_recipe(u8 rid, bool vlan)
{
u8 udp_tun_profile[12] = {10, 11, 12, 16, 17, 18, 22, 23, 24, 25, 26,
27};
u8 gre_profile[12] = {13, 14, 15, 19, 20, 21, 28, 29, 30, 31, 32, 33};
u8 pppoe_profile[7] = {34, 35, 36, 37, 38, 39, 40};
u8 non_tun_profile[6] = {4, 5, 6, 7, 8, 9};
enum ice_sw_tunnel_type tun_type;
u16 i, j, profile_num = 0;
u16 k;
bool udp_tun_valid = false;
bool non_tun_valid = false;
bool pppoe_valid = false;
bool gre_valid = false;
bool gtp_valid = false;
bool flag_valid = false;
for (j = 0; j < ICE_MAX_NUM_PROFILES; j++) {
if (!ice_is_bit_set(recipe_to_profile[rid], j))
continue;
else
profile_num++;
for (i = 0; i < 12; i++) {
if (gre_profile[i] == j)
gre_valid = true;
}
for (i = 0; i < 12; i++) {
if (udp_tun_profile[i] == j)
udp_tun_valid = true;
}
for (i = 0; i < 7; i++) {
if (pppoe_profile[i] == j)
pppoe_valid = true;
}
for (i = 0; i < 6; i++) {
if (non_tun_profile[i] == j)
non_tun_valid = true;
}
if (j >= ICE_PROFID_IPV4_GTPU_EH_IPV4_OTHER &&
j <= ICE_PROFID_IPV6_GTPU_IPV6_TCP)
gtp_valid = true;
if ((j >= ICE_PROFID_IPV4_ESP &&
j <= ICE_PROFID_IPV6_PFCP_SESSION) ||
(j >= ICE_PROFID_IPV4_GTPC_TEID &&
j <= ICE_PROFID_IPV6_GTPU_TEID))
flag_valid = true;
}
if (!non_tun_valid && udp_tun_valid)
tun_type = ICE_SW_TUN_UDP;
else if (!non_tun_valid && gre_valid)
tun_type = ICE_SW_TUN_NVGRE;
else if (!non_tun_valid && pppoe_valid)
tun_type = ICE_SW_TUN_PPPOE;
else if (!non_tun_valid && gtp_valid)
tun_type = ICE_SW_TUN_GTP;
else if (non_tun_valid &&
(udp_tun_valid || gre_valid || gtp_valid || pppoe_valid))
tun_type = ICE_SW_TUN_AND_NON_TUN;
else if (non_tun_valid && !udp_tun_valid && !gre_valid && !gtp_valid &&
!pppoe_valid)
tun_type = ICE_NON_TUN;
else
tun_type = ICE_NON_TUN;
if (profile_num > 1 && tun_type == ICE_SW_TUN_PPPOE) {
i = ice_is_bit_set(recipe_to_profile[rid],
ICE_PROFID_PPPOE_IPV4_OTHER);
j = ice_is_bit_set(recipe_to_profile[rid],
ICE_PROFID_PPPOE_IPV6_OTHER);
if (i && !j)
tun_type = ICE_SW_TUN_PPPOE_IPV4;
else if (!i && j)
tun_type = ICE_SW_TUN_PPPOE_IPV6;
}
if (tun_type == ICE_SW_TUN_GTP) {
for (k = 0; k < ARRAY_SIZE(ice_prof_type_tbl); k++)
if (ice_is_bit_set(recipe_to_profile[rid],
ice_prof_type_tbl[k].prof_id)) {
tun_type = ice_prof_type_tbl[k].type;
break;
}
}
if (profile_num == 1 && (flag_valid || non_tun_valid || pppoe_valid)) {
for (j = 0; j < ICE_MAX_NUM_PROFILES; j++) {
if (ice_is_bit_set(recipe_to_profile[rid], j)) {
switch (j) {
case ICE_PROFID_IPV4_TCP:
tun_type = ICE_SW_IPV4_TCP;
break;
case ICE_PROFID_IPV4_UDP:
tun_type = ICE_SW_IPV4_UDP;
break;
case ICE_PROFID_IPV6_TCP:
tun_type = ICE_SW_IPV6_TCP;
break;
case ICE_PROFID_IPV6_UDP:
tun_type = ICE_SW_IPV6_UDP;
break;
case ICE_PROFID_PPPOE_PAY:
tun_type = ICE_SW_TUN_PPPOE_PAY;
break;
case ICE_PROFID_PPPOE_IPV4_TCP:
tun_type = ICE_SW_TUN_PPPOE_IPV4_TCP;
break;
case ICE_PROFID_PPPOE_IPV4_UDP:
tun_type = ICE_SW_TUN_PPPOE_IPV4_UDP;
break;
case ICE_PROFID_PPPOE_IPV4_OTHER:
tun_type = ICE_SW_TUN_PPPOE_IPV4;
break;
case ICE_PROFID_PPPOE_IPV6_TCP:
tun_type = ICE_SW_TUN_PPPOE_IPV6_TCP;
break;
case ICE_PROFID_PPPOE_IPV6_UDP:
tun_type = ICE_SW_TUN_PPPOE_IPV6_UDP;
break;
case ICE_PROFID_PPPOE_IPV6_OTHER:
tun_type = ICE_SW_TUN_PPPOE_IPV6;
break;
case ICE_PROFID_IPV4_ESP:
tun_type = ICE_SW_TUN_IPV4_ESP;
break;
case ICE_PROFID_IPV6_ESP:
tun_type = ICE_SW_TUN_IPV6_ESP;
break;
case ICE_PROFID_IPV4_AH:
tun_type = ICE_SW_TUN_IPV4_AH;
break;
case ICE_PROFID_IPV6_AH:
tun_type = ICE_SW_TUN_IPV6_AH;
break;
case ICE_PROFID_IPV4_NAT_T:
tun_type = ICE_SW_TUN_IPV4_NAT_T;
break;
case ICE_PROFID_IPV6_NAT_T:
tun_type = ICE_SW_TUN_IPV6_NAT_T;
break;
case ICE_PROFID_IPV4_PFCP_NODE:
tun_type =
ICE_SW_TUN_PROFID_IPV4_PFCP_NODE;
break;
case ICE_PROFID_IPV6_PFCP_NODE:
tun_type =
ICE_SW_TUN_PROFID_IPV6_PFCP_NODE;
break;
case ICE_PROFID_IPV4_PFCP_SESSION:
tun_type =
ICE_SW_TUN_PROFID_IPV4_PFCP_SESSION;
break;
case ICE_PROFID_IPV6_PFCP_SESSION:
tun_type =
ICE_SW_TUN_PROFID_IPV6_PFCP_SESSION;
break;
case ICE_PROFID_MAC_IPV4_L2TPV3:
tun_type = ICE_SW_TUN_IPV4_L2TPV3;
break;
case ICE_PROFID_MAC_IPV6_L2TPV3:
tun_type = ICE_SW_TUN_IPV6_L2TPV3;
break;
case ICE_PROFID_IPV4_GTPU_TEID:
tun_type = ICE_SW_TUN_IPV4_GTPU_NO_PAY;
break;
case ICE_PROFID_IPV6_GTPU_TEID:
tun_type = ICE_SW_TUN_IPV6_GTPU_NO_PAY;
break;
default:
break;
}
return tun_type;
}
}
}
if (vlan && tun_type == ICE_SW_TUN_PPPOE)
tun_type = ICE_SW_TUN_PPPOE_QINQ;
else if (vlan && tun_type == ICE_SW_TUN_PPPOE_IPV6)
tun_type = ICE_SW_TUN_PPPOE_IPV6_QINQ;
else if (vlan && tun_type == ICE_SW_TUN_PPPOE_IPV4)
tun_type = ICE_SW_TUN_PPPOE_IPV4_QINQ;
else if (vlan && tun_type == ICE_SW_TUN_PPPOE_PAY)
tun_type = ICE_SW_TUN_PPPOE_PAY_QINQ;
else if (vlan && tun_type == ICE_SW_TUN_AND_NON_TUN)
tun_type = ICE_SW_TUN_AND_NON_TUN_QINQ;
else if (vlan && tun_type == ICE_NON_TUN)
tun_type = ICE_NON_TUN_QINQ;
return tun_type;
}
/**
* ice_get_recp_frm_fw - update SW bookkeeping from FW recipe entries
* @hw: pointer to hardware structure
* @recps: struct that we need to populate
* @rid: recipe ID that we are populating
* @refresh_required: true if we should get recipe to profile mapping from FW
*
* This function is used to populate all the necessary entries into our
* bookkeeping so that we have a current list of all the recipes that are
* programmed in the firmware.
*/
static int
ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
bool *refresh_required)
{
ice_declare_bitmap(result_bm, ICE_MAX_FV_WORDS);
struct ice_recp_grp_entry *rg, *tmprg_entry;
struct ice_aqc_recipe_data_elem *tmp;
u16 num_recps = ICE_MAX_NUM_RECIPES;
struct ice_prot_lkup_ext *lkup_exts;
u8 fv_word_idx = 0;
bool vlan = false;
u16 sub_recps;
int status;
ice_zero_bitmap(result_bm, ICE_MAX_FV_WORDS);
/* we need a buffer big enough to accommodate all the recipes */
tmp = (struct ice_aqc_recipe_data_elem *)ice_calloc(hw,
ICE_MAX_NUM_RECIPES, sizeof(*tmp));
if (!tmp)
return ICE_ERR_NO_MEMORY;
tmp[0].recipe_indx = rid;
status = ice_aq_get_recipe(hw, tmp, &num_recps, rid, NULL);
/* non-zero status meaning recipe doesn't exist */
if (status)
goto err_unroll;
if (!num_recps) {
status = ICE_ERR_PARAM;
goto err_unroll;
}
/* Get recipe to profile map so that we can get the fv from lkups that
* we read for a recipe from FW. Since we want to minimize the number of
* times we make this FW call, just make one call and cache the copy
* until a new recipe is added. This operation is only required the
* first time to get the changes from FW. Then to search existing
* entries we don't need to update the cache again until another recipe
* gets added.
*/
if (*refresh_required) {
ice_get_recp_to_prof_map(hw);
*refresh_required = false;
}
/* Start populating all the entries for recps[rid] based on lkups from
* firmware. Note that we are only creating the root recipe in our
* database.
*/
lkup_exts = &recps[rid].lkup_exts;
/* Remove duplicate entries */
LIST_FOR_EACH_ENTRY_SAFE(rg, tmprg_entry, &recps[rid].rg_list,
ice_recp_grp_entry, l_entry) {
if (rg->rid == rid) {
LIST_DEL(&rg->l_entry);
ice_free(hw, rg);
}
}
for (sub_recps = 0; sub_recps < num_recps; sub_recps++) {
struct ice_aqc_recipe_data_elem root_bufs = tmp[sub_recps];
struct ice_recp_grp_entry *rg_entry;
u8 i, prof, idx, prot = 0;
bool is_root;
u16 off = 0;
rg_entry = (struct ice_recp_grp_entry *)
ice_malloc(hw, sizeof(*rg_entry));
if (!rg_entry) {
status = ICE_ERR_NO_MEMORY;
goto err_unroll;
}
idx = root_bufs.recipe_indx;
is_root = root_bufs.content.rid & ICE_AQ_RECIPE_ID_IS_ROOT;
/* Mark all result indices in this chain */
if (root_bufs.content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
ice_set_bit(root_bufs.content.result_indx &
~ICE_AQ_RECIPE_RESULT_EN, result_bm);
/* get the first profile that is associated with rid */
prof = (u8)ice_find_first_bit(recipe_to_profile[idx],
ICE_MAX_NUM_PROFILES);
for (i = 0; i < ICE_NUM_WORDS_RECIPE; i++) {
u8 lkup_indx = root_bufs.content.lkup_indx[i + 1];
rg_entry->fv_idx[i] = lkup_indx;
rg_entry->fv_mask[i] =
LE16_TO_CPU(root_bufs.content.mask[i + 1]);
/* If the recipe is a chained recipe then all its
* child recipe's result will have a result index.
* To fill fv_words we should not use those result
* index, we only need the protocol ids and offsets.
* We will skip all the fv_idx which stores result
* index in them. We also need to skip any fv_idx which
* has ICE_AQ_RECIPE_LKUP_IGNORE or 0 since it isn't a
* valid offset value.
*/
if (ice_is_bit_set(hw->switch_info->prof_res_bm[prof],
rg_entry->fv_idx[i]) ||
rg_entry->fv_idx[i] & ICE_AQ_RECIPE_LKUP_IGNORE ||
rg_entry->fv_idx[i] == 0)
continue;
ice_find_prot_off(hw, ICE_BLK_SW, prof,
rg_entry->fv_idx[i], &prot, &off);
lkup_exts->fv_words[fv_word_idx].prot_id = prot;
lkup_exts->fv_words[fv_word_idx].off = off;
lkup_exts->field_mask[fv_word_idx] =
rg_entry->fv_mask[i];
if (prot == ICE_META_DATA_ID_HW &&
off == ICE_TUN_FLAG_MDID_OFF(1))
vlan = true;
fv_word_idx++;
}
/* populate rg_list with the data from the child entry of this
* recipe
*/
LIST_ADD(&rg_entry->l_entry, &recps[rid].rg_list);
/* Propagate some data to the recipe database */
recps[idx].is_root = is_root;
recps[idx].priority = root_bufs.content.act_ctrl_fwd_priority;
ice_zero_bitmap(recps[idx].res_idxs, ICE_MAX_FV_WORDS);
if (root_bufs.content.result_indx & ICE_AQ_RECIPE_RESULT_EN) {
recps[idx].chain_idx = root_bufs.content.result_indx &
~ICE_AQ_RECIPE_RESULT_EN;
ice_set_bit(recps[idx].chain_idx, recps[idx].res_idxs);
} else {
recps[idx].chain_idx = ICE_INVAL_CHAIN_IND;
}
if (!is_root)
continue;
/* Only do the following for root recipes entries */
ice_memcpy(recps[idx].r_bitmap, root_bufs.recipe_bitmap,
sizeof(recps[idx].r_bitmap), ICE_NONDMA_TO_NONDMA);
recps[idx].root_rid = root_bufs.content.rid &
~ICE_AQ_RECIPE_ID_IS_ROOT;
recps[idx].priority = root_bufs.content.act_ctrl_fwd_priority;
}
/* Complete initialization of the root recipe entry */
lkup_exts->n_val_words = fv_word_idx;
recps[rid].big_recp = (num_recps > 1);
recps[rid].n_grp_count = (u8)num_recps;
recps[rid].tun_type = ice_get_tun_type_for_recipe(rid, vlan);
if (recps[rid].root_buf)
ice_free(hw, recps[rid].root_buf);
recps[rid].root_buf = (struct ice_aqc_recipe_data_elem *)
ice_memdup(hw, tmp, recps[rid].n_grp_count *
sizeof(*recps[rid].root_buf), ICE_NONDMA_TO_NONDMA);
if (!recps[rid].root_buf)
goto err_unroll;
/* Copy result indexes */
ice_cp_bitmap(recps[rid].res_idxs, result_bm, ICE_MAX_FV_WORDS);
recps[rid].recp_created = true;
err_unroll:
ice_free(hw, tmp);
return status;
}
/**
* ice_get_recp_to_prof_map - updates recipe to profile mapping
* @hw: pointer to hardware structure
*
* This function is used to populate recipe_to_profile matrix where index to
* this array is the recipe ID and the element is the mapping of which profiles
* is this recipe mapped to.
*/
static void ice_get_recp_to_prof_map(struct ice_hw *hw)
{
ice_declare_bitmap(r_bitmap, ICE_MAX_NUM_RECIPES);
u16 i;
for (i = 0; i < hw->switch_info->max_used_prof_index + 1; i++) {
u16 j;
ice_zero_bitmap(profile_to_recipe[i], ICE_MAX_NUM_RECIPES);
ice_zero_bitmap(r_bitmap, ICE_MAX_NUM_RECIPES);
if (ice_aq_get_recipe_to_profile(hw, i, (u8 *)r_bitmap, NULL))
continue;
ice_cp_bitmap(profile_to_recipe[i], r_bitmap,
ICE_MAX_NUM_RECIPES);
ice_for_each_set_bit(j, r_bitmap, ICE_MAX_NUM_RECIPES)
ice_set_bit(i, recipe_to_profile[j]);
}
}
static bool
ice_vsi_uses_fltr(struct ice_fltr_mgmt_list_entry *fm_entry, u16 vsi_handle);
/**
* ice_init_def_sw_recp - initialize the recipe book keeping tables
* @hw: pointer to the HW struct
* @recp_list: pointer to sw recipe list
*
* Allocate memory for the entire recipe table and initialize the structures/
* entries corresponding to basic recipes.
*/
int
ice_init_def_sw_recp(struct ice_hw *hw, struct ice_sw_recipe **recp_list)
{
struct ice_sw_recipe *recps;
u8 i;
recps = (struct ice_sw_recipe *)
ice_calloc(hw, ICE_MAX_NUM_RECIPES, sizeof(*recps));
if (!recps)
return ICE_ERR_NO_MEMORY;
for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
recps[i].root_rid = i;
INIT_LIST_HEAD(&recps[i].filt_rules);
INIT_LIST_HEAD(&recps[i].filt_replay_rules);
INIT_LIST_HEAD(&recps[i].rg_list);
ice_init_lock(&recps[i].filt_rule_lock);
}
*recp_list = recps;
return 0;
}
/**
* ice_aq_get_sw_cfg - get switch configuration
* @hw: pointer to the hardware structure
* @buf: pointer to the result buffer
* @buf_size: length of the buffer available for response
* @req_desc: pointer to requested descriptor
* @num_elems: pointer to number of elements
* @cd: pointer to command details structure or NULL
*
* Get switch configuration (0x0200) to be placed in buf.
* This admin command returns information such as initial VSI/port number
* and switch ID it belongs to.
*
* NOTE: *req_desc is both an input/output parameter.
* The caller of this function first calls this function with *request_desc set
* to 0. If the response from f/w has *req_desc set to 0, all the switch
* configuration information has been returned; if non-zero (meaning not all
* the information was returned), the caller should call this function again
* with *req_desc set to the previous value returned by f/w to get the
* next block of switch configuration information.
*
* *num_elems is output only parameter. This reflects the number of elements
* in response buffer. The caller of this function to use *num_elems while
* parsing the response buffer.
*/
static int
ice_aq_get_sw_cfg(struct ice_hw *hw, struct ice_aqc_get_sw_cfg_resp_elem *buf,
u16 buf_size, u16 *req_desc, u16 *num_elems,
struct ice_sq_cd *cd)
{
struct ice_aqc_get_sw_cfg *cmd;
struct ice_aq_desc desc;
int status;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sw_cfg);
cmd = &desc.params.get_sw_conf;
cmd->element = CPU_TO_LE16(*req_desc);
status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
if (!status) {
*req_desc = LE16_TO_CPU(cmd->element);
*num_elems = LE16_TO_CPU(cmd->num_elems);
}
return status;
}
/**
* ice_alloc_rss_global_lut - allocate a RSS global LUT
* @hw: pointer to the HW struct
* @shared_res: true to allocate as a shared resource and false to allocate as a dedicated resource
* @global_lut_id: output parameter for the RSS global LUT's ID
*/
int ice_alloc_rss_global_lut(struct ice_hw *hw, bool shared_res, u16 *global_lut_id)
{
struct ice_aqc_alloc_free_res_elem *sw_buf;
int status;
u16 buf_len;
buf_len = ice_struct_size(sw_buf, elem, 1);
sw_buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
if (!sw_buf)
return ICE_ERR_NO_MEMORY;
sw_buf->num_elems = CPU_TO_LE16(1);
sw_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH |
(shared_res ? ICE_AQC_RES_TYPE_FLAG_SHARED :
ICE_AQC_RES_TYPE_FLAG_DEDICATED));
status = ice_aq_alloc_free_res(hw, 1, sw_buf, buf_len, ice_aqc_opc_alloc_res, NULL);
if (status) {
ice_debug(hw, ICE_DBG_RES, "Failed to allocate %s RSS global LUT, status %d\n",
shared_res ? "shared" : "dedicated", status);
goto ice_alloc_global_lut_exit;
}
*global_lut_id = LE16_TO_CPU(sw_buf->elem[0].e.sw_resp);
ice_alloc_global_lut_exit:
ice_free(hw, sw_buf);
return status;
}
/**
* ice_free_sw_marker_lg - free a switch marker large action
* @hw: pointer to the HW struct
* @marker_lg_id: ID of the marker large action to free
* @sw_marker: sw marker to tag the Rx descriptor with
*/
static int
ice_free_sw_marker_lg(struct ice_hw *hw, u16 marker_lg_id, u32 sw_marker)
{
struct ice_aqc_alloc_free_res_elem *sw_buf;
u16 buf_len, num_elems = 1;
int status;
buf_len = ice_struct_size(sw_buf, elem, num_elems);
sw_buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
if (!sw_buf)
return ICE_ERR_NO_MEMORY;
sw_buf->num_elems = CPU_TO_LE16(num_elems);
if (sw_marker <= 0xFFFF)
sw_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_WIDE_TABLE_1);
else
sw_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_WIDE_TABLE_2);
sw_buf->elem[0].e.sw_resp = CPU_TO_LE16(marker_lg_id);
status = ice_aq_alloc_free_res(hw, num_elems, sw_buf, buf_len,
ice_aqc_opc_free_res, NULL);
if (status)
ice_debug(hw, ICE_DBG_RES, "Failed to free sw marker lg %d, status %d\n",
marker_lg_id, status);
ice_free(hw, sw_buf);
return status;
}
/**
* ice_free_rss_global_lut - free a RSS global LUT
* @hw: pointer to the HW struct
* @global_lut_id: ID of the RSS global LUT to free
*/
int ice_free_rss_global_lut(struct ice_hw *hw, u16 global_lut_id)
{
struct ice_aqc_alloc_free_res_elem *sw_buf;
u16 buf_len, num_elems = 1;
int status;
buf_len = ice_struct_size(sw_buf, elem, num_elems);
sw_buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
if (!sw_buf)
return ICE_ERR_NO_MEMORY;
sw_buf->num_elems = CPU_TO_LE16(num_elems);
sw_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH);
sw_buf->elem[0].e.sw_resp = CPU_TO_LE16(global_lut_id);
status = ice_aq_alloc_free_res(hw, num_elems, sw_buf, buf_len, ice_aqc_opc_free_res, NULL);
if (status)
ice_debug(hw, ICE_DBG_RES, "Failed to free RSS global LUT %d, status %d\n",
global_lut_id, status);
ice_free(hw, sw_buf);
return status;
}
/**
* ice_alloc_sw - allocate resources specific to switch
* @hw: pointer to the HW struct
* @ena_stats: true to turn on VEB stats
* @shared_res: true for shared resource, false for dedicated resource
* @sw_id: switch ID returned
* @counter_id: VEB counter ID returned
*
* allocates switch resources (SWID and VEB counter) (0x0208)
*/
int
ice_alloc_sw(struct ice_hw *hw, bool ena_stats, bool shared_res, u16 *sw_id,
u16 *counter_id)
{
struct ice_aqc_alloc_free_res_elem *sw_buf;
struct ice_aqc_res_elem *sw_ele;
u16 buf_len;
int status;
buf_len = ice_struct_size(sw_buf, elem, 1);
sw_buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
if (!sw_buf)
return ICE_ERR_NO_MEMORY;
/* Prepare buffer for switch ID.
* The number of resource entries in buffer is passed as 1 since only a
* single switch/VEB instance is allocated, and hence a single sw_id
* is requested.
*/
sw_buf->num_elems = CPU_TO_LE16(1);
sw_buf->res_type =
CPU_TO_LE16(ICE_AQC_RES_TYPE_SWID |
(shared_res ? ICE_AQC_RES_TYPE_FLAG_SHARED :
ICE_AQC_RES_TYPE_FLAG_DEDICATED));
status = ice_aq_alloc_free_res(hw, 1, sw_buf, buf_len,
ice_aqc_opc_alloc_res, NULL);
if (status)
goto ice_alloc_sw_exit;
sw_ele = &sw_buf->elem[0];
*sw_id = LE16_TO_CPU(sw_ele->e.sw_resp);
if (ena_stats) {
/* Prepare buffer for VEB Counter */
enum ice_adminq_opc opc = ice_aqc_opc_alloc_res;
struct ice_aqc_alloc_free_res_elem *counter_buf;
struct ice_aqc_res_elem *counter_ele;
counter_buf = (struct ice_aqc_alloc_free_res_elem *)
ice_malloc(hw, buf_len);
if (!counter_buf) {
status = ICE_ERR_NO_MEMORY;
goto ice_alloc_sw_exit;
}
/* The number of resource entries in buffer is passed as 1 since
* only a single switch/VEB instance is allocated, and hence a
* single VEB counter is requested.
*/
counter_buf->num_elems = CPU_TO_LE16(1);
counter_buf->res_type =
CPU_TO_LE16(ICE_AQC_RES_TYPE_VEB_COUNTER |
ICE_AQC_RES_TYPE_FLAG_DEDICATED);
status = ice_aq_alloc_free_res(hw, 1, counter_buf, buf_len,
opc, NULL);
if (status) {
ice_free(hw, counter_buf);
goto ice_alloc_sw_exit;
}
counter_ele = &counter_buf->elem[0];
*counter_id = LE16_TO_CPU(counter_ele->e.sw_resp);
ice_free(hw, counter_buf);
}
ice_alloc_sw_exit:
ice_free(hw, sw_buf);
return status;
}
/**
* ice_free_sw - free resources specific to switch
* @hw: pointer to the HW struct
* @sw_id: switch ID returned
* @counter_id: VEB counter ID returned
*
* free switch resources (SWID and VEB counter) (0x0209)
*
* NOTE: This function frees multiple resources. It continues
* releasing other resources even after it encounters error.
* The error code returned is the last error it encountered.
*/
int ice_free_sw(struct ice_hw *hw, u16 sw_id, u16 counter_id)
{
struct ice_aqc_alloc_free_res_elem *sw_buf, *counter_buf;
int status, ret_status;
u16 buf_len;
buf_len = ice_struct_size(sw_buf, elem, 1);
sw_buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
if (!sw_buf)
return ICE_ERR_NO_MEMORY;
/* Prepare buffer to free for switch ID res.
* The number of resource entries in buffer is passed as 1 since only a
* single switch/VEB instance is freed, and hence a single sw_id
* is released.
*/
sw_buf->num_elems = CPU_TO_LE16(1);
sw_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_SWID);
sw_buf->elem[0].e.sw_resp = CPU_TO_LE16(sw_id);
ret_status = ice_aq_alloc_free_res(hw, 1, sw_buf, buf_len,
ice_aqc_opc_free_res, NULL);
if (ret_status)
ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
/* Prepare buffer to free for VEB Counter resource */
counter_buf = (struct ice_aqc_alloc_free_res_elem *)
ice_malloc(hw, buf_len);
if (!counter_buf) {
ice_free(hw, sw_buf);
return ICE_ERR_NO_MEMORY;
}
/* The number of resource entries in buffer is passed as 1 since only a
* single switch/VEB instance is freed, and hence a single VEB counter
* is released
*/
counter_buf->num_elems = CPU_TO_LE16(1);
counter_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_VEB_COUNTER);
counter_buf->elem[0].e.sw_resp = CPU_TO_LE16(counter_id);
status = ice_aq_alloc_free_res(hw, 1, counter_buf, buf_len,
ice_aqc_opc_free_res, NULL);
if (status) {
ice_debug(hw, ICE_DBG_SW, "VEB counter resource could not be freed\n");
ret_status = status;
}
ice_free(hw, counter_buf);
ice_free(hw, sw_buf);
return ret_status;
}
/**
* ice_aq_add_vsi
* @hw: pointer to the HW struct
* @vsi_ctx: pointer to a VSI context struct
* @cd: pointer to command details structure or NULL
*
* Add a VSI context to the hardware (0x0210)
*/
int
ice_aq_add_vsi(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,
struct ice_sq_cd *cd)
{
struct ice_aqc_add_update_free_vsi_resp *res;
struct ice_aqc_add_get_update_free_vsi *cmd;
struct ice_aq_desc desc;
int status;
cmd = &desc.params.vsi_cmd;
res = &desc.params.add_update_free_vsi_res;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_vsi);
if (!vsi_ctx->alloc_from_pool)
cmd->vsi_num = CPU_TO_LE16(vsi_ctx->vsi_num |
ICE_AQ_VSI_IS_VALID);
cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
status = ice_aq_send_cmd(hw, &desc, &vsi_ctx->info,
sizeof(vsi_ctx->info), cd);
if (!status) {
vsi_ctx->vsi_num = LE16_TO_CPU(res->vsi_num) & ICE_AQ_VSI_NUM_M;
vsi_ctx->vsis_allocd = LE16_TO_CPU(res->vsi_used);
vsi_ctx->vsis_unallocated = LE16_TO_CPU(res->vsi_free);
}
return status;
}
/**
* ice_aq_free_vsi
* @hw: pointer to the HW struct
* @vsi_ctx: pointer to a VSI context struct
* @keep_vsi_alloc: keep VSI allocation as part of this PF's resources
* @cd: pointer to command details structure or NULL
*
* Free VSI context info from hardware (0x0213)
*/
int
ice_aq_free_vsi(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,
bool keep_vsi_alloc, struct ice_sq_cd *cd)
{
struct ice_aqc_add_update_free_vsi_resp *resp;
struct ice_aqc_add_get_update_free_vsi *cmd;
struct ice_aq_desc desc;
int status;
cmd = &desc.params.vsi_cmd;
resp = &desc.params.add_update_free_vsi_res;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_free_vsi);
cmd->vsi_num = CPU_TO_LE16(vsi_ctx->vsi_num | ICE_AQ_VSI_IS_VALID);
if (keep_vsi_alloc)
cmd->cmd_flags = CPU_TO_LE16(ICE_AQ_VSI_KEEP_ALLOC);
status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
if (!status) {
vsi_ctx->vsis_allocd = LE16_TO_CPU(resp->vsi_used);
vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
}
return status;
}
/**
* ice_aq_update_vsi
* @hw: pointer to the HW struct
* @vsi_ctx: pointer to a VSI context struct
* @cd: pointer to command details structure or NULL
*
* Update VSI context in the hardware (0x0211)
*/
int
ice_aq_update_vsi(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,
struct ice_sq_cd *cd)
{
struct ice_aqc_add_update_free_vsi_resp *resp;
struct ice_aqc_add_get_update_free_vsi *cmd;
struct ice_aq_desc desc;
int status;
cmd = &desc.params.vsi_cmd;
resp = &desc.params.add_update_free_vsi_res;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_update_vsi);
cmd->vsi_num = CPU_TO_LE16(vsi_ctx->vsi_num | ICE_AQ_VSI_IS_VALID);
desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
status = ice_aq_send_cmd(hw, &desc, &vsi_ctx->info,
sizeof(vsi_ctx->info), cd);
if (!status) {
vsi_ctx->vsis_allocd = LE16_TO_CPU(resp->vsi_used);
vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
}
return status;
}
/**
* ice_is_vsi_valid - check whether the VSI is valid or not
* @hw: pointer to the HW struct
* @vsi_handle: VSI handle
*
* check whether the VSI is valid or not
*/
bool ice_is_vsi_valid(struct ice_hw *hw, u16 vsi_handle)
{
return vsi_handle < ICE_MAX_VSI && hw->vsi_ctx[vsi_handle];
}
/**
* ice_get_hw_vsi_num - return the HW VSI number
* @hw: pointer to the HW struct
* @vsi_handle: VSI handle
*
* return the HW VSI number
* Caution: call this function only if VSI is valid (ice_is_vsi_valid)
*/
u16 ice_get_hw_vsi_num(struct ice_hw *hw, u16 vsi_handle)
{
return hw->vsi_ctx[vsi_handle]->vsi_num;
}
/**
* ice_get_vsi_ctx - return the VSI context entry for a given VSI handle
* @hw: pointer to the HW struct
* @vsi_handle: VSI handle
*
* return the VSI context entry for a given VSI handle
*/
struct ice_vsi_ctx *ice_get_vsi_ctx(struct ice_hw *hw, u16 vsi_handle)
{
return (vsi_handle >= ICE_MAX_VSI) ? NULL : hw->vsi_ctx[vsi_handle];
}
/**
* ice_save_vsi_ctx - save the VSI context for a given VSI handle
* @hw: pointer to the HW struct
* @vsi_handle: VSI handle
* @vsi: VSI context pointer
*
* save the VSI context entry for a given VSI handle
*/
static void
ice_save_vsi_ctx(struct ice_hw *hw, u16 vsi_handle, struct ice_vsi_ctx *vsi)
{
hw->vsi_ctx[vsi_handle] = vsi;
}
/**
* ice_clear_vsi_q_ctx - clear VSI queue contexts for all TCs
* @hw: pointer to the HW struct
* @vsi_handle: VSI handle
*/
void ice_clear_vsi_q_ctx(struct ice_hw *hw, u16 vsi_handle)
{
struct ice_vsi_ctx *vsi;
u8 i;
vsi = ice_get_vsi_ctx(hw, vsi_handle);
if (!vsi)
return;
ice_for_each_traffic_class(i) {
if (vsi->lan_q_ctx[i]) {
ice_free(hw, vsi->lan_q_ctx[i]);
vsi->lan_q_ctx[i] = NULL;
}
}
}
/**
* ice_clear_vsi_ctx - clear the VSI context entry
* @hw: pointer to the HW struct
* @vsi_handle: VSI handle
*
* clear the VSI context entry
*/
static void ice_clear_vsi_ctx(struct ice_hw *hw, u16 vsi_handle)
{
struct ice_vsi_ctx *vsi;
vsi = ice_get_vsi_ctx(hw, vsi_handle);
if (vsi) {
ice_clear_vsi_q_ctx(hw, vsi_handle);
ice_free(hw, vsi);
hw->vsi_ctx[vsi_handle] = NULL;
}
}
/**
* ice_clear_all_vsi_ctx - clear all the VSI context entries
* @hw: pointer to the HW struct
*/
void ice_clear_all_vsi_ctx(struct ice_hw *hw)
{
u16 i;
for (i = 0; i < ICE_MAX_VSI; i++)
ice_clear_vsi_ctx(hw, i);
}
/**
* ice_add_vsi - add VSI context to the hardware and VSI handle list
* @hw: pointer to the HW struct
* @vsi_handle: unique VSI handle provided by drivers
* @vsi_ctx: pointer to a VSI context struct
* @cd: pointer to command details structure or NULL
*
* Add a VSI context to the hardware also add it into the VSI handle list.
* If this function gets called after reset for existing VSIs then update
* with the new HW VSI number in the corresponding VSI handle list entry.
*/
int
ice_add_vsi(struct ice_hw *hw, u16 vsi_handle, struct ice_vsi_ctx *vsi_ctx,
struct ice_sq_cd *cd)
{
struct ice_vsi_ctx *tmp_vsi_ctx;
int status;
if (vsi_handle >= ICE_MAX_VSI)
return ICE_ERR_PARAM;
status = ice_aq_add_vsi(hw, vsi_ctx, cd);
if (status)
return status;
tmp_vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle);
if (!tmp_vsi_ctx) {
/* Create a new VSI context */
tmp_vsi_ctx = (struct ice_vsi_ctx *)
ice_malloc(hw, sizeof(*tmp_vsi_ctx));
if (!tmp_vsi_ctx) {
ice_aq_free_vsi(hw, vsi_ctx, false, cd);
return ICE_ERR_NO_MEMORY;
}
*tmp_vsi_ctx = *vsi_ctx;
ice_save_vsi_ctx(hw, vsi_handle, tmp_vsi_ctx);
} else {
/* update with new HW VSI num */
tmp_vsi_ctx->vsi_num = vsi_ctx->vsi_num;
}
return 0;
}
/**
* ice_free_vsi- free VSI context from hardware and VSI handle list
* @hw: pointer to the HW struct
* @vsi_handle: unique VSI handle
* @vsi_ctx: pointer to a VSI context struct
* @keep_vsi_alloc: keep VSI allocation as part of this PF's resources
* @cd: pointer to command details structure or NULL
*
* Free VSI context info from hardware as well as from VSI handle list
*/
int
ice_free_vsi(struct ice_hw *hw, u16 vsi_handle, struct ice_vsi_ctx *vsi_ctx,
bool keep_vsi_alloc, struct ice_sq_cd *cd)
{
int status;
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
vsi_ctx->vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
status = ice_aq_free_vsi(hw, vsi_ctx, keep_vsi_alloc, cd);
if (!status)
ice_clear_vsi_ctx(hw, vsi_handle);
return status;
}
/**
* ice_update_vsi
* @hw: pointer to the HW struct
* @vsi_handle: unique VSI handle
* @vsi_ctx: pointer to a VSI context struct
* @cd: pointer to command details structure or NULL
*
* Update VSI context in the hardware
*/
int
ice_update_vsi(struct ice_hw *hw, u16 vsi_handle, struct ice_vsi_ctx *vsi_ctx,
struct ice_sq_cd *cd)
{
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
vsi_ctx->vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
return ice_aq_update_vsi(hw, vsi_ctx, cd);
}
/**
* ice_aq_get_vsi_params
* @hw: pointer to the HW struct
* @vsi_ctx: pointer to a VSI context struct
* @cd: pointer to command details structure or NULL
*
* Get VSI context info from hardware (0x0212)
*/
int
ice_aq_get_vsi_params(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,
struct ice_sq_cd *cd)
{
struct ice_aqc_add_get_update_free_vsi *cmd;
struct ice_aqc_get_vsi_resp *resp;
struct ice_aq_desc desc;
int status;
cmd = &desc.params.vsi_cmd;
resp = &desc.params.get_vsi_resp;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_vsi_params);
cmd->vsi_num = CPU_TO_LE16(vsi_ctx->vsi_num | ICE_AQ_VSI_IS_VALID);
status = ice_aq_send_cmd(hw, &desc, &vsi_ctx->info,
sizeof(vsi_ctx->info), cd);
if (!status) {
vsi_ctx->vsi_num = LE16_TO_CPU(resp->vsi_num) &
ICE_AQ_VSI_NUM_M;
vsi_ctx->vsis_allocd = LE16_TO_CPU(resp->vsi_used);
vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
}
return status;
}
/**
* ice_aq_add_update_mir_rule - add/update a mirror rule
* @hw: pointer to the HW struct
* @rule_type: Rule Type
* @dest_vsi: VSI number to which packets will be mirrored
* @count: length of the list
* @mr_buf: buffer for list of mirrored VSI numbers
* @cd: pointer to command details structure or NULL
* @rule_id: Rule ID
*
* Add/Update Mirror Rule (0x260).
*/
int
ice_aq_add_update_mir_rule(struct ice_hw *hw, u16 rule_type, u16 dest_vsi,
u16 count, struct ice_mir_rule_buf *mr_buf,
struct ice_sq_cd *cd, u16 *rule_id)
{
struct ice_aqc_add_update_mir_rule *cmd;
struct ice_aq_desc desc;
__le16 *mr_list = NULL;
u16 buf_size = 0;
int status;
switch (rule_type) {
case ICE_AQC_RULE_TYPE_VPORT_INGRESS:
case ICE_AQC_RULE_TYPE_VPORT_EGRESS:
/* Make sure count and mr_buf are set for these rule_types */
if (!(count && mr_buf))
return ICE_ERR_PARAM;
buf_size = count * sizeof(__le16);
mr_list = (_FORCE_ __le16 *)ice_malloc(hw, buf_size);
if (!mr_list)
return ICE_ERR_NO_MEMORY;
break;
case ICE_AQC_RULE_TYPE_PPORT_INGRESS:
case ICE_AQC_RULE_TYPE_PPORT_EGRESS:
/* Make sure count and mr_buf are not set for these
* rule_types
*/
if (count || mr_buf)
return ICE_ERR_PARAM;
break;
default:
ice_debug(hw, ICE_DBG_SW, "Error due to unsupported rule_type %u\n", rule_type);
return ICE_ERR_OUT_OF_RANGE;
}
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_update_mir_rule);
/* Pre-process 'mr_buf' items for add/update of virtual port
* ingress/egress mirroring (but not physical port ingress/egress
* mirroring)
*/
if (mr_buf) {
int i;
for (i = 0; i < count; i++) {
u16 id;
id = mr_buf[i].vsi_idx & ICE_AQC_RULE_MIRRORED_VSI_M;
/* Validate specified VSI number, make sure it is less
* than ICE_MAX_VSI, if not return with error.
*/
if (id >= ICE_MAX_VSI) {
ice_debug(hw, ICE_DBG_SW, "Error VSI index (%u) out-of-range\n",
id);
ice_free(hw, mr_list);
return ICE_ERR_OUT_OF_RANGE;
}
/* add VSI to mirror rule */
if (mr_buf[i].add)
mr_list[i] =
CPU_TO_LE16(id | ICE_AQC_RULE_ACT_M);
else /* remove VSI from mirror rule */
mr_list[i] = CPU_TO_LE16(id);
}
desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
}
cmd = &desc.params.add_update_rule;
if ((*rule_id) != ICE_INVAL_MIRROR_RULE_ID)
cmd->rule_id = CPU_TO_LE16(((*rule_id) & ICE_AQC_RULE_ID_M) |
ICE_AQC_RULE_ID_VALID_M);
cmd->rule_type = CPU_TO_LE16(rule_type & ICE_AQC_RULE_TYPE_M);
cmd->num_entries = CPU_TO_LE16(count);
cmd->dest = CPU_TO_LE16(dest_vsi);
status = ice_aq_send_cmd(hw, &desc, mr_list, buf_size, cd);
if (!status)
*rule_id = LE16_TO_CPU(cmd->rule_id) & ICE_AQC_RULE_ID_M;
ice_free(hw, mr_list);
return status;
}
/**
* ice_aq_delete_mir_rule - delete a mirror rule
* @hw: pointer to the HW struct
* @rule_id: Mirror rule ID (to be deleted)
* @keep_allocd: if set, the VSI stays part of the PF allocated res,
* otherwise it is returned to the shared pool
* @cd: pointer to command details structure or NULL
*
* Delete Mirror Rule (0x261).
*/
int
ice_aq_delete_mir_rule(struct ice_hw *hw, u16 rule_id, bool keep_allocd,
struct ice_sq_cd *cd)
{
struct ice_aqc_delete_mir_rule *cmd;
struct ice_aq_desc desc;
/* rule_id should be in the range 0...63 */
if (rule_id >= ICE_MAX_NUM_MIRROR_RULES)
return ICE_ERR_OUT_OF_RANGE;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_del_mir_rule);
cmd = &desc.params.del_rule;
rule_id |= ICE_AQC_RULE_ID_VALID_M;
cmd->rule_id = CPU_TO_LE16(rule_id);
if (keep_allocd)
cmd->flags = CPU_TO_LE16(ICE_AQC_FLAG_KEEP_ALLOCD_M);
return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
}
/**
* ice_aq_alloc_free_vsi_list
* @hw: pointer to the HW struct
* @vsi_list_id: VSI list ID returned or used for lookup
* @lkup_type: switch rule filter lookup type
* @opc: switch rules population command type - pass in the command opcode
*
* allocates or free a VSI list resource
*/
static int
ice_aq_alloc_free_vsi_list(struct ice_hw *hw, u16 *vsi_list_id,
enum ice_sw_lkup_type lkup_type,
enum ice_adminq_opc opc)
{
struct ice_aqc_alloc_free_res_elem *sw_buf;
struct ice_aqc_res_elem *vsi_ele;
u16 buf_len;
int status;
buf_len = ice_struct_size(sw_buf, elem, 1);
sw_buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
if (!sw_buf)
return ICE_ERR_NO_MEMORY;
sw_buf->num_elems = CPU_TO_LE16(1);
if (lkup_type == ICE_SW_LKUP_MAC ||
lkup_type == ICE_SW_LKUP_MAC_VLAN ||
lkup_type == ICE_SW_LKUP_ETHERTYPE ||
lkup_type == ICE_SW_LKUP_ETHERTYPE_MAC ||
lkup_type == ICE_SW_LKUP_PROMISC ||
lkup_type == ICE_SW_LKUP_PROMISC_VLAN ||
lkup_type == ICE_SW_LKUP_DFLT ||
lkup_type == ICE_SW_LKUP_LAST) {
sw_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_VSI_LIST_REP);
} else if (lkup_type == ICE_SW_LKUP_VLAN) {
sw_buf->res_type =
CPU_TO_LE16(ICE_AQC_RES_TYPE_VSI_LIST_PRUNE);
} else {
status = ICE_ERR_PARAM;
goto ice_aq_alloc_free_vsi_list_exit;
}
if (opc == ice_aqc_opc_free_res)
sw_buf->elem[0].e.sw_resp = CPU_TO_LE16(*vsi_list_id);
status = ice_aq_alloc_free_res(hw, 1, sw_buf, buf_len, opc, NULL);
if (status)
goto ice_aq_alloc_free_vsi_list_exit;
if (opc == ice_aqc_opc_alloc_res) {
vsi_ele = &sw_buf->elem[0];
*vsi_list_id = LE16_TO_CPU(vsi_ele->e.sw_resp);
}
ice_aq_alloc_free_vsi_list_exit:
ice_free(hw, sw_buf);
return status;
}
/**
* ice_aq_set_storm_ctrl - Sets storm control configuration
* @hw: pointer to the HW struct
* @bcast_thresh: represents the upper threshold for broadcast storm control
* @mcast_thresh: represents the upper threshold for multicast storm control
* @ctl_bitmask: storm control knobs
*
* Sets the storm control configuration (0x0280)
*/
int
ice_aq_set_storm_ctrl(struct ice_hw *hw, u32 bcast_thresh, u32 mcast_thresh,
u32 ctl_bitmask)
{
struct ice_aqc_storm_cfg *cmd;
struct ice_aq_desc desc;
cmd = &desc.params.storm_conf;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_storm_cfg);
cmd->bcast_thresh_size = CPU_TO_LE32(bcast_thresh & ICE_AQ_THRESHOLD_M);
cmd->mcast_thresh_size = CPU_TO_LE32(mcast_thresh & ICE_AQ_THRESHOLD_M);
cmd->storm_ctrl_ctrl = CPU_TO_LE32(ctl_bitmask);
return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
}
/**
* ice_aq_get_storm_ctrl - gets storm control configuration
* @hw: pointer to the HW struct
* @bcast_thresh: represents the upper threshold for broadcast storm control
* @mcast_thresh: represents the upper threshold for multicast storm control
* @ctl_bitmask: storm control knobs
*
* Gets the storm control configuration (0x0281)
*/
int
ice_aq_get_storm_ctrl(struct ice_hw *hw, u32 *bcast_thresh, u32 *mcast_thresh,
u32 *ctl_bitmask)
{
struct ice_aq_desc desc;
int status;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_storm_cfg);
status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
if (!status) {
struct ice_aqc_storm_cfg *resp = &desc.params.storm_conf;
if (bcast_thresh)
*bcast_thresh = LE32_TO_CPU(resp->bcast_thresh_size) &
ICE_AQ_THRESHOLD_M;
if (mcast_thresh)
*mcast_thresh = LE32_TO_CPU(resp->mcast_thresh_size) &
ICE_AQ_THRESHOLD_M;
if (ctl_bitmask)
*ctl_bitmask = LE32_TO_CPU(resp->storm_ctrl_ctrl);
}
return status;
}
/**
* ice_aq_sw_rules - add/update/remove switch rules
* @hw: pointer to the HW struct
* @rule_list: pointer to switch rule population list
* @rule_list_sz: total size of the rule list in bytes
* @num_rules: number of switch rules in the rule_list
* @opc: switch rules population command type - pass in the command opcode
* @cd: pointer to command details structure or NULL
*
* Add(0x02a0)/Update(0x02a1)/Remove(0x02a2) switch rules commands to firmware
*/
static int
ice_aq_sw_rules(struct ice_hw *hw, void *rule_list, u16 rule_list_sz,
u8 num_rules, enum ice_adminq_opc opc, struct ice_sq_cd *cd)
{
struct ice_aq_desc desc;
int status;
ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
if (opc != ice_aqc_opc_add_sw_rules &&
opc != ice_aqc_opc_update_sw_rules &&
opc != ice_aqc_opc_remove_sw_rules)
return ICE_ERR_PARAM;
ice_fill_dflt_direct_cmd_desc(&desc, opc);
desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
desc.params.sw_rules.num_rules_fltr_entry_index =
CPU_TO_LE16(num_rules);
status = ice_aq_send_cmd(hw, &desc, rule_list, rule_list_sz, cd);
if (opc != ice_aqc_opc_add_sw_rules &&
hw->adminq.sq_last_status == ICE_AQ_RC_ENOENT)
status = ICE_ERR_DOES_NOT_EXIST;
return status;
}
/**
* ice_aq_add_recipe - add switch recipe
* @hw: pointer to the HW struct
* @s_recipe_list: pointer to switch rule population list
* @num_recipes: number of switch recipes in the list
* @cd: pointer to command details structure or NULL
*
* Add(0x0290)
*/
int
ice_aq_add_recipe(struct ice_hw *hw,
struct ice_aqc_recipe_data_elem *s_recipe_list,
u16 num_recipes, struct ice_sq_cd *cd)
{
struct ice_aqc_add_get_recipe *cmd;
struct ice_aq_desc desc;
u16 buf_size;
ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
cmd = &desc.params.add_get_recipe;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_recipe);
cmd->num_sub_recipes = CPU_TO_LE16(num_recipes);
desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
buf_size = num_recipes * sizeof(*s_recipe_list);
return ice_aq_send_cmd(hw, &desc, s_recipe_list, buf_size, cd);
}
/**
* ice_aq_get_recipe - get switch recipe
* @hw: pointer to the HW struct
* @s_recipe_list: pointer to switch rule population list
* @num_recipes: pointer to the number of recipes (input and output)
* @recipe_root: root recipe number of recipe(s) to retrieve
* @cd: pointer to command details structure or NULL
*
* Get(0x0292)
*
* On input, *num_recipes should equal the number of entries in s_recipe_list.
* On output, *num_recipes will equal the number of entries returned in
* s_recipe_list.
*
* The caller must supply enough space in s_recipe_list to hold all possible
* recipes and *num_recipes must equal ICE_MAX_NUM_RECIPES.
*/
int
ice_aq_get_recipe(struct ice_hw *hw,
struct ice_aqc_recipe_data_elem *s_recipe_list,
u16 *num_recipes, u16 recipe_root, struct ice_sq_cd *cd)
{
struct ice_aqc_add_get_recipe *cmd;
struct ice_aq_desc desc;
u16 buf_size;
int status;
if (*num_recipes != ICE_MAX_NUM_RECIPES)
return ICE_ERR_PARAM;
ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
cmd = &desc.params.add_get_recipe;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_recipe);
cmd->return_index = CPU_TO_LE16(recipe_root);
cmd->num_sub_recipes = 0;
buf_size = *num_recipes * sizeof(*s_recipe_list);
status = ice_aq_send_cmd(hw, &desc, s_recipe_list, buf_size, cd);
*num_recipes = LE16_TO_CPU(cmd->num_sub_recipes);
return status;
}
/**
* ice_update_recipe_lkup_idx - update a default recipe based on the lkup_idx
* @hw: pointer to the HW struct
* @params: parameters used to update the default recipe
*
* This function only supports updating default recipes and it only supports
* updating a single recipe based on the lkup_idx at a time.
*
* This is done as a read-modify-write operation. First, get the current recipe
* contents based on the recipe's ID. Then modify the field vector index and
* mask if it's valid at the lkup_idx. Finally, use the add recipe AQ to update
* the pre-existing recipe with the modifications.
*/
int
ice_update_recipe_lkup_idx(struct ice_hw *hw,
struct ice_update_recipe_lkup_idx_params *params)
{
struct ice_aqc_recipe_data_elem *rcp_list;
u16 num_recps = ICE_MAX_NUM_RECIPES;
int status;
rcp_list = (struct ice_aqc_recipe_data_elem *)ice_malloc(hw, num_recps * sizeof(*rcp_list));
if (!rcp_list)
return ICE_ERR_NO_MEMORY;
/* read current recipe list from firmware */
rcp_list->recipe_indx = params->rid;
status = ice_aq_get_recipe(hw, rcp_list, &num_recps, params->rid, NULL);
if (status) {
ice_debug(hw, ICE_DBG_SW, "Failed to get recipe %d, status %d\n",
params->rid, status);
goto error_out;
}
/* only modify existing recipe's lkup_idx and mask if valid, while
* leaving all other fields the same, then update the recipe firmware
*/
rcp_list->content.lkup_indx[params->lkup_idx] = params->fv_idx;
if (params->mask_valid)
rcp_list->content.mask[params->lkup_idx] =
CPU_TO_LE16(params->mask);
if (params->ignore_valid)
rcp_list->content.lkup_indx[params->lkup_idx] |=
ICE_AQ_RECIPE_LKUP_IGNORE;
status = ice_aq_add_recipe(hw, &rcp_list[0], 1, NULL);
if (status)
ice_debug(hw, ICE_DBG_SW, "Failed to update recipe %d lkup_idx %d fv_idx %d mask %d mask_valid %s, status %d\n",
params->rid, params->lkup_idx, params->fv_idx,
params->mask, params->mask_valid ? "true" : "false",
status);
error_out:
ice_free(hw, rcp_list);
return status;
}
/**
* ice_aq_map_recipe_to_profile - Map recipe to packet profile
* @hw: pointer to the HW struct
* @profile_id: package profile ID to associate the recipe with
* @r_bitmap: Recipe bitmap filled in and need to be returned as response
* @cd: pointer to command details structure or NULL
* Recipe to profile association (0x0291)
*/
int
ice_aq_map_recipe_to_profile(struct ice_hw *hw, u32 profile_id, u8 *r_bitmap,
struct ice_sq_cd *cd)
{
struct ice_aqc_recipe_to_profile *cmd;
struct ice_aq_desc desc;
ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
cmd = &desc.params.recipe_to_profile;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_recipe_to_profile);
cmd->profile_id = CPU_TO_LE16(profile_id);
/* Set the recipe ID bit in the bitmask to let the device know which
* profile we are associating the recipe to
*/
ice_memcpy(cmd->recipe_assoc, r_bitmap, sizeof(cmd->recipe_assoc),
ICE_NONDMA_TO_NONDMA);
return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
}
/**
* ice_aq_get_recipe_to_profile - Map recipe to packet profile
* @hw: pointer to the HW struct
* @profile_id: package profile ID to associate the recipe with
* @r_bitmap: Recipe bitmap filled in and need to be returned as response
* @cd: pointer to command details structure or NULL
* Associate profile ID with given recipe (0x0293)
*/
int
ice_aq_get_recipe_to_profile(struct ice_hw *hw, u32 profile_id, u8 *r_bitmap,
struct ice_sq_cd *cd)
{
struct ice_aqc_recipe_to_profile *cmd;
struct ice_aq_desc desc;
int status;
ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
cmd = &desc.params.recipe_to_profile;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_recipe_to_profile);
cmd->profile_id = CPU_TO_LE16(profile_id);
status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
if (!status)
ice_memcpy(r_bitmap, cmd->recipe_assoc,
sizeof(cmd->recipe_assoc), ICE_NONDMA_TO_NONDMA);
return status;
}
/**
* ice_alloc_recipe - add recipe resource
* @hw: pointer to the hardware structure
* @rid: recipe ID returned as response to AQ call
*/
int ice_alloc_recipe(struct ice_hw *hw, u16 *rid)
{
struct ice_aqc_alloc_free_res_elem *sw_buf;
u16 buf_len;
int status;
buf_len = ice_struct_size(sw_buf, elem, 1);
sw_buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
if (!sw_buf)
return ICE_ERR_NO_MEMORY;
sw_buf->num_elems = CPU_TO_LE16(1);
sw_buf->res_type = CPU_TO_LE16((ICE_AQC_RES_TYPE_RECIPE <<
ICE_AQC_RES_TYPE_S) |
ICE_AQC_RES_TYPE_FLAG_SHARED);
status = ice_aq_alloc_free_res(hw, 1, sw_buf, buf_len,
ice_aqc_opc_alloc_res, NULL);
if (!status)
*rid = LE16_TO_CPU(sw_buf->elem[0].e.sw_resp);
ice_free(hw, sw_buf);
return status;
}
/* ice_init_port_info - Initialize port_info with switch configuration data
* @pi: pointer to port_info
* @vsi_port_num: VSI number or port number
* @type: Type of switch element (port or VSI)
* @swid: switch ID of the switch the element is attached to
* @pf_vf_num: PF or VF number
* @is_vf: true if the element is a VF, false otherwise
*/
static void
ice_init_port_info(struct ice_port_info *pi, u16 vsi_port_num, u8 type,
u16 swid, u16 pf_vf_num, bool is_vf)
{
switch (type) {
case ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT:
pi->lport = (u8)(vsi_port_num & ICE_LPORT_MASK);
pi->sw_id = swid;
pi->pf_vf_num = pf_vf_num;
pi->is_vf = is_vf;
break;
default:
ice_debug(pi->hw, ICE_DBG_SW, "incorrect VSI/port type received\n");
break;
}
}
/* ice_get_initial_sw_cfg - Get initial port and default VSI data
* @hw: pointer to the hardware structure
*/
int ice_get_initial_sw_cfg(struct ice_hw *hw)
{
struct ice_aqc_get_sw_cfg_resp_elem *rbuf;
u8 num_total_ports;
u16 req_desc = 0;
u16 num_elems;
int status;
u8 j = 0;
u16 i;
num_total_ports = 1;
rbuf = (struct ice_aqc_get_sw_cfg_resp_elem *)
ice_malloc(hw, ICE_SW_CFG_MAX_BUF_LEN);
if (!rbuf)
return ICE_ERR_NO_MEMORY;
/* Multiple calls to ice_aq_get_sw_cfg may be required
* to get all the switch configuration information. The need
* for additional calls is indicated by ice_aq_get_sw_cfg
* writing a non-zero value in req_desc
*/
do {
struct ice_aqc_get_sw_cfg_resp_elem *ele;
status = ice_aq_get_sw_cfg(hw, rbuf, ICE_SW_CFG_MAX_BUF_LEN,
&req_desc, &num_elems, NULL);
if (status)
break;
for (i = 0, ele = rbuf; i < num_elems; i++, ele++) {
u16 pf_vf_num, swid, vsi_port_num;
bool is_vf = false;
u8 res_type;
vsi_port_num = LE16_TO_CPU(ele->vsi_port_num) &
ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M;
pf_vf_num = LE16_TO_CPU(ele->pf_vf_num) &
ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M;
swid = LE16_TO_CPU(ele->swid);
if (LE16_TO_CPU(ele->pf_vf_num) &
ICE_AQC_GET_SW_CONF_RESP_IS_VF)
is_vf = true;
res_type = (u8)(LE16_TO_CPU(ele->vsi_port_num) >>
ICE_AQC_GET_SW_CONF_RESP_TYPE_S);
switch (res_type) {
case ICE_AQC_GET_SW_CONF_RESP_VSI:
if (hw->fw_vsi_num != ICE_DFLT_VSI_INVAL)
ice_debug(hw, ICE_DBG_SW, "fw_vsi_num %d -> %d\n",
hw->fw_vsi_num, vsi_port_num);
hw->fw_vsi_num = vsi_port_num;
if (hw->dcf_enabled && !is_vf)
hw->pf_id = pf_vf_num;
break;
case ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT:
case ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT:
if (j == num_total_ports) {
ice_debug(hw, ICE_DBG_SW, "more ports than expected\n");
status = ICE_ERR_CFG;
goto out;
}
ice_init_port_info(hw->port_info,
vsi_port_num, res_type, swid,
pf_vf_num, is_vf);
j++;
break;
default:
break;
}
}
} while (req_desc && !status);
out:
ice_free(hw, rbuf);
return status;
}
/**
* ice_fill_sw_info - Helper function to populate lb_en and lan_en
* @hw: pointer to the hardware structure
* @fi: filter info structure to fill/update
*
* This helper function populates the lb_en and lan_en elements of the provided
* ice_fltr_info struct using the switch's type and characteristics of the
* switch rule being configured.
*/
static void ice_fill_sw_info(struct ice_hw *hw, struct ice_fltr_info *fi)
{
if ((fi->flag & ICE_FLTR_RX) &&
(fi->fltr_act == ICE_FWD_TO_VSI ||
fi->fltr_act == ICE_FWD_TO_VSI_LIST) &&
fi->lkup_type == ICE_SW_LKUP_LAST)
fi->lan_en = true;
fi->lb_en = false;
fi->lan_en = false;
if ((fi->flag & ICE_FLTR_TX) &&
(fi->fltr_act == ICE_FWD_TO_VSI ||
fi->fltr_act == ICE_FWD_TO_VSI_LIST ||
fi->fltr_act == ICE_FWD_TO_Q ||
fi->fltr_act == ICE_FWD_TO_QGRP)) {
/* Setting LB for prune actions will result in replicated
* packets to the internal switch that will be dropped.
*/
if (fi->lkup_type != ICE_SW_LKUP_VLAN)
fi->lb_en = true;
/* Set lan_en to TRUE if
* 1. The switch is a VEB AND
* 2
* 2.1 The lookup is a directional lookup like ethertype,
* promiscuous, ethertype-MAC, promiscuous-VLAN
* and default-port OR
* 2.2 The lookup is VLAN, OR
* 2.3 The lookup is MAC with mcast or bcast addr for MAC, OR
* 2.4 The lookup is MAC_VLAN with mcast or bcast addr for MAC.
*
* OR
*
* The switch is a VEPA.
*
* In all other cases, the LAN enable has to be set to false.
*/
if (hw->evb_veb) {
if (fi->lkup_type == ICE_SW_LKUP_ETHERTYPE ||
fi->lkup_type == ICE_SW_LKUP_PROMISC ||
fi->lkup_type == ICE_SW_LKUP_ETHERTYPE_MAC ||
fi->lkup_type == ICE_SW_LKUP_PROMISC_VLAN ||
fi->lkup_type == ICE_SW_LKUP_DFLT ||
fi->lkup_type == ICE_SW_LKUP_VLAN ||
(fi->lkup_type == ICE_SW_LKUP_MAC &&
!IS_UNICAST_ETHER_ADDR(fi->l_data.mac.mac_addr)) ||
(fi->lkup_type == ICE_SW_LKUP_MAC_VLAN &&
!IS_UNICAST_ETHER_ADDR(fi->l_data.mac.mac_addr))) {
if (!fi->fltVeb_en)
fi->lan_en = true;
}
} else {
fi->lan_en = true;
}
}
/* To be able to receive packets coming from the VF on the same PF,
* unicast filter needs to be added without LB_EN bit
*/
if (fi->flag & ICE_FLTR_RX_LB) {
fi->lb_en = false;
fi->lan_en = true;
}
}
/**
* ice_fill_sw_rule - Helper function to fill switch rule structure
* @hw: pointer to the hardware structure
* @f_info: entry containing packet forwarding information
* @s_rule: switch rule structure to be filled in based on mac_entry
* @opc: switch rules population command type - pass in the command opcode
*/
static void
ice_fill_sw_rule(struct ice_hw *hw, struct ice_fltr_info *f_info,
struct ice_sw_rule_lkup_rx_tx *s_rule,
enum ice_adminq_opc opc)
{
u16 vlan_id = ICE_MAX_VLAN_ID + 1;
u16 vlan_tpid = ICE_ETH_P_8021Q;
void *daddr = NULL;
u16 eth_hdr_sz;
u8 *eth_hdr;
u32 act = 0;
__be16 *off;
u8 q_rgn;
if (opc == ice_aqc_opc_remove_sw_rules) {
s_rule->act = 0;
s_rule->index = CPU_TO_LE16(f_info->fltr_rule_id);
s_rule->hdr_len = 0;
return;
}
eth_hdr_sz = sizeof(dummy_eth_header);
eth_hdr = s_rule->hdr_data;
/* initialize the ether header with a dummy header */
ice_memcpy(eth_hdr, dummy_eth_header, eth_hdr_sz, ICE_NONDMA_TO_NONDMA);
ice_fill_sw_info(hw, f_info);
switch (f_info->fltr_act) {
case ICE_FWD_TO_VSI:
act |= (f_info->fwd_id.hw_vsi_id << ICE_SINGLE_ACT_VSI_ID_S) &
ICE_SINGLE_ACT_VSI_ID_M;
if (f_info->lkup_type != ICE_SW_LKUP_VLAN)
act |= ICE_SINGLE_ACT_VSI_FORWARDING |
ICE_SINGLE_ACT_VALID_BIT;
break;
case ICE_FWD_TO_VSI_LIST:
act |= ICE_SINGLE_ACT_VSI_LIST;
act |= (f_info->fwd_id.vsi_list_id <<
ICE_SINGLE_ACT_VSI_LIST_ID_S) &
ICE_SINGLE_ACT_VSI_LIST_ID_M;
if (f_info->lkup_type != ICE_SW_LKUP_VLAN)
act |= ICE_SINGLE_ACT_VSI_FORWARDING |
ICE_SINGLE_ACT_VALID_BIT;
break;
case ICE_FWD_TO_Q:
act |= ICE_SINGLE_ACT_TO_Q;
act |= (f_info->fwd_id.q_id << ICE_SINGLE_ACT_Q_INDEX_S) &
ICE_SINGLE_ACT_Q_INDEX_M;
break;
case ICE_DROP_PACKET:
act |= ICE_SINGLE_ACT_VSI_FORWARDING | ICE_SINGLE_ACT_DROP |
ICE_SINGLE_ACT_VALID_BIT;
break;
case ICE_FWD_TO_QGRP:
q_rgn = f_info->qgrp_size > 0 ?
(u8)ice_ilog2(f_info->qgrp_size) : 0;
act |= ICE_SINGLE_ACT_TO_Q;
act |= (f_info->fwd_id.q_id << ICE_SINGLE_ACT_Q_INDEX_S) &
ICE_SINGLE_ACT_Q_INDEX_M;
act |= (q_rgn << ICE_SINGLE_ACT_Q_REGION_S) &
ICE_SINGLE_ACT_Q_REGION_M;
break;
default:
return;
}
if (f_info->lb_en)
act |= ICE_SINGLE_ACT_LB_ENABLE;
if (f_info->lan_en)
act |= ICE_SINGLE_ACT_LAN_ENABLE;
switch (f_info->lkup_type) {
case ICE_SW_LKUP_MAC:
daddr = f_info->l_data.mac.mac_addr;
break;
case ICE_SW_LKUP_VLAN:
vlan_id = f_info->l_data.vlan.vlan_id;
if (f_info->l_data.vlan.tpid_valid)
vlan_tpid = f_info->l_data.vlan.tpid;
if (f_info->fltr_act == ICE_FWD_TO_VSI ||
f_info->fltr_act == ICE_FWD_TO_VSI_LIST) {
act |= ICE_SINGLE_ACT_PRUNE;
act |= ICE_SINGLE_ACT_EGRESS | ICE_SINGLE_ACT_INGRESS;
}
break;
case ICE_SW_LKUP_ETHERTYPE_MAC:
daddr = f_info->l_data.ethertype_mac.mac_addr;
/* fall-through */
case ICE_SW_LKUP_ETHERTYPE:
off = (_FORCE_ __be16 *)(eth_hdr + ICE_ETH_ETHTYPE_OFFSET);
*off = CPU_TO_BE16(f_info->l_data.ethertype_mac.ethertype);
break;
case ICE_SW_LKUP_MAC_VLAN:
daddr = f_info->l_data.mac_vlan.mac_addr;
vlan_id = f_info->l_data.mac_vlan.vlan_id;
break;
case ICE_SW_LKUP_PROMISC_VLAN:
vlan_id = f_info->l_data.mac_vlan.vlan_id;
/* fall-through */
case ICE_SW_LKUP_PROMISC:
daddr = f_info->l_data.mac_vlan.mac_addr;
break;
default:
break;
}
s_rule->hdr.type = (f_info->flag & ICE_FLTR_RX) ?
CPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_RX) :
CPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_TX);
/* Recipe set depending on lookup type */
if (f_info->rid_override) {
s_rule->recipe_id = CPU_TO_LE16(f_info->rid);
} else {
s_rule->recipe_id = CPU_TO_LE16(f_info->lkup_type);
}
s_rule->src = CPU_TO_LE16(f_info->src);
s_rule->act = CPU_TO_LE32(act);
if (daddr)
ice_memcpy(eth_hdr + ICE_ETH_DA_OFFSET, daddr, ETH_ALEN,
ICE_NONDMA_TO_NONDMA);
if (!(vlan_id > ICE_MAX_VLAN_ID)) {
off = (_FORCE_ __be16 *)(eth_hdr + ICE_ETH_VLAN_TCI_OFFSET);
*off = CPU_TO_BE16(vlan_id);
off = (_FORCE_ __be16 *)(eth_hdr + ICE_ETH_ETHTYPE_OFFSET);
*off = CPU_TO_BE16(vlan_tpid);
}
/* Create the switch rule with the final dummy Ethernet header */
if (opc != ice_aqc_opc_update_sw_rules)
s_rule->hdr_len = CPU_TO_LE16(eth_hdr_sz);
}
/**
* ice_add_marker_act
* @hw: pointer to the hardware structure
* @m_ent: the management entry for which sw marker needs to be added
* @sw_marker: sw marker to tag the Rx descriptor with
* @l_id: large action resource ID
*
* Create a large action to hold software marker and update the switch rule
* entry pointed by m_ent with newly created large action
*/
static int
ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,
u16 sw_marker, u16 l_id)
{
struct ice_sw_rule_lkup_rx_tx *rx_tx;
struct ice_sw_rule_lg_act *lg_act;
/* For software marker we need 3 large actions
* 1. FWD action: FWD TO VSI or VSI LIST
* 2. GENERIC VALUE action to hold the profile ID
* 3. GENERIC VALUE action to hold the software marker ID
*/
const u16 num_lg_acts = 3;
u16 lg_act_size;
u16 rules_size;
int status;
u32 act;
u16 id;
if (m_ent->fltr_info.lkup_type != ICE_SW_LKUP_MAC)
return ICE_ERR_PARAM;
/* Create two back-to-back switch rules and submit them to the HW using
* one memory buffer:
* 1. Large Action
* 2. Look up Tx Rx
*/
lg_act_size = (u16)ice_struct_size(lg_act, act, num_lg_acts);
rules_size = lg_act_size +
ice_struct_size(rx_tx, hdr_data, DUMMY_ETH_HDR_LEN);
lg_act = (struct ice_sw_rule_lg_act *)ice_malloc(hw, rules_size);
if (!lg_act)
return ICE_ERR_NO_MEMORY;
rx_tx = (struct ice_sw_rule_lkup_rx_tx *)((u8 *)lg_act + lg_act_size);
/* Fill in the first switch rule i.e. large action */
lg_act->hdr.type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT);
lg_act->index = CPU_TO_LE16(l_id);
lg_act->size = CPU_TO_LE16(num_lg_acts);
/* First action VSI forwarding or VSI list forwarding depending on how
* many VSIs
*/
id = (m_ent->vsi_count > 1) ? m_ent->fltr_info.fwd_id.vsi_list_id :
m_ent->fltr_info.fwd_id.hw_vsi_id;
act = ICE_LG_ACT_VSI_FORWARDING | ICE_LG_ACT_VALID_BIT;
act |= (id << ICE_LG_ACT_VSI_LIST_ID_S) & ICE_LG_ACT_VSI_LIST_ID_M;
if (m_ent->vsi_count > 1)
act |= ICE_LG_ACT_VSI_LIST;
lg_act->act[0] = CPU_TO_LE32(act);
/* Second action descriptor type */
act = ICE_LG_ACT_GENERIC;
act |= (1 << ICE_LG_ACT_GENERIC_VALUE_S) & ICE_LG_ACT_GENERIC_VALUE_M;
lg_act->act[1] = CPU_TO_LE32(act);
act = (ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX <<
ICE_LG_ACT_GENERIC_OFFSET_S) & ICE_LG_ACT_GENERIC_OFFSET_M;
/* Third action Marker value */
act |= ICE_LG_ACT_GENERIC;
act |= (sw_marker << ICE_LG_ACT_GENERIC_VALUE_S) &
ICE_LG_ACT_GENERIC_VALUE_M;
lg_act->act[2] = CPU_TO_LE32(act);
/* call the fill switch rule to fill the lookup Tx Rx structure */
ice_fill_sw_rule(hw, &m_ent->fltr_info, rx_tx,
ice_aqc_opc_update_sw_rules);
/* Update the action to point to the large action ID */
rx_tx->act = CPU_TO_LE32(ICE_SINGLE_ACT_PTR |
((l_id << ICE_SINGLE_ACT_PTR_VAL_S) &
ICE_SINGLE_ACT_PTR_VAL_M));
/* Use the filter rule ID of the previously created rule with single
* act. Once the update happens, hardware will treat this as large
* action
*/
rx_tx->index = CPU_TO_LE16(m_ent->fltr_info.fltr_rule_id);
status = ice_aq_sw_rules(hw, lg_act, rules_size, 2,
ice_aqc_opc_update_sw_rules, NULL);
if (!status) {
m_ent->lg_act_idx = l_id;
m_ent->sw_marker_id = sw_marker;
}
ice_free(hw, lg_act);
return status;
}
/**
* ice_add_counter_act - add/update filter rule with counter action
* @hw: pointer to the hardware structure
* @m_ent: the management entry for which counter needs to be added
* @counter_id: VLAN counter ID returned as part of allocate resource
* @l_id: large action resource ID
*/
static int
ice_add_counter_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,
u16 counter_id, u16 l_id)
{
struct ice_sw_rule_lkup_rx_tx *rx_tx;
struct ice_sw_rule_lg_act *lg_act;
/* 2 actions will be added while adding a large action counter */
const int num_acts = 2;
u16 lg_act_size;
u16 rules_size;
u16 f_rule_id;
u32 act;
int status;
u16 id;
if (m_ent->fltr_info.lkup_type != ICE_SW_LKUP_MAC)
return ICE_ERR_PARAM;
/* Create two back-to-back switch rules and submit them to the HW using
* one memory buffer:
* 1. Large Action
* 2. Look up Tx Rx
*/
lg_act_size = (u16)ice_struct_size(lg_act, act, num_acts);
rules_size = lg_act_size +
ice_struct_size(rx_tx, hdr_data, DUMMY_ETH_HDR_LEN);
lg_act = (struct ice_sw_rule_lg_act *)ice_malloc(hw, rules_size);
if (!lg_act)
return ICE_ERR_NO_MEMORY;
rx_tx = (struct ice_sw_rule_lkup_rx_tx *)((u8 *)lg_act +
lg_act_size);
/* Fill in the first switch rule i.e. large action */
lg_act->hdr.type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT);
lg_act->index = CPU_TO_LE16(l_id);
lg_act->size = CPU_TO_LE16(num_acts);
/* First action VSI forwarding or VSI list forwarding depending on how
* many VSIs
*/
id = (m_ent->vsi_count > 1) ? m_ent->fltr_info.fwd_id.vsi_list_id :
m_ent->fltr_info.fwd_id.hw_vsi_id;
act = ICE_LG_ACT_VSI_FORWARDING | ICE_LG_ACT_VALID_BIT;
act |= (id << ICE_LG_ACT_VSI_LIST_ID_S) &
ICE_LG_ACT_VSI_LIST_ID_M;
if (m_ent->vsi_count > 1)
act |= ICE_LG_ACT_VSI_LIST;
lg_act->act[0] = CPU_TO_LE32(act);
/* Second action counter ID */
act = ICE_LG_ACT_STAT_COUNT;
act |= (counter_id << ICE_LG_ACT_STAT_COUNT_S) &
ICE_LG_ACT_STAT_COUNT_M;
lg_act->act[1] = CPU_TO_LE32(act);
/* call the fill switch rule to fill the lookup Tx Rx structure */
ice_fill_sw_rule(hw, &m_ent->fltr_info, rx_tx,
ice_aqc_opc_update_sw_rules);
act = ICE_SINGLE_ACT_PTR;
act |= (l_id << ICE_SINGLE_ACT_PTR_VAL_S) & ICE_SINGLE_ACT_PTR_VAL_M;
rx_tx->act = CPU_TO_LE32(act);
/* Use the filter rule ID of the previously created rule with single
* act. Once the update happens, hardware will treat this as large
* action
*/
f_rule_id = m_ent->fltr_info.fltr_rule_id;
rx_tx->index = CPU_TO_LE16(f_rule_id);
status = ice_aq_sw_rules(hw, lg_act, rules_size, 2,
ice_aqc_opc_update_sw_rules, NULL);
if (!status) {
m_ent->lg_act_idx = l_id;
m_ent->counter_index = (u8)counter_id;
}
ice_free(hw, lg_act);
return status;
}
/**
* ice_create_vsi_list_map
* @hw: pointer to the hardware structure
* @vsi_handle_arr: array of VSI handles to set in the VSI mapping
* @num_vsi: number of VSI handles in the array
* @vsi_list_id: VSI list ID generated as part of allocate resource
*
* Helper function to create a new entry of VSI list ID to VSI mapping
* using the given VSI list ID
*/
static struct ice_vsi_list_map_info *
ice_create_vsi_list_map(struct ice_hw *hw, u16 *vsi_handle_arr, u16 num_vsi,
u16 vsi_list_id)
{
struct ice_switch_info *sw = hw->switch_info;
struct ice_vsi_list_map_info *v_map;
int i;
v_map = (struct ice_vsi_list_map_info *)ice_malloc(hw, sizeof(*v_map));
if (!v_map)
return NULL;
v_map->vsi_list_id = vsi_list_id;
v_map->ref_cnt = 1;
for (i = 0; i < num_vsi; i++)
ice_set_bit(vsi_handle_arr[i], v_map->vsi_map);
LIST_ADD(&v_map->list_entry, &sw->vsi_list_map_head);
return v_map;
}
/**
* ice_update_vsi_list_rule
* @hw: pointer to the hardware structure
* @vsi_handle_arr: array of VSI handles to form a VSI list
* @num_vsi: number of VSI handles in the array
* @vsi_list_id: VSI list ID generated as part of allocate resource
* @remove: Boolean value to indicate if this is a remove action
* @opc: switch rules population command type - pass in the command opcode
* @lkup_type: lookup type of the filter
*
* Call AQ command to add a new switch rule or update existing switch rule
* using the given VSI list ID
*/
static int
ice_update_vsi_list_rule(struct ice_hw *hw, u16 *vsi_handle_arr, u16 num_vsi,
u16 vsi_list_id, bool remove, enum ice_adminq_opc opc,
enum ice_sw_lkup_type lkup_type)
{
struct ice_sw_rule_vsi_list *s_rule;
u16 s_rule_size;
u16 rule_type;
int status;
int i;
if (!num_vsi)
return ICE_ERR_PARAM;
if (lkup_type == ICE_SW_LKUP_MAC ||
lkup_type == ICE_SW_LKUP_MAC_VLAN ||
lkup_type == ICE_SW_LKUP_ETHERTYPE ||
lkup_type == ICE_SW_LKUP_ETHERTYPE_MAC ||
lkup_type == ICE_SW_LKUP_PROMISC ||
lkup_type == ICE_SW_LKUP_PROMISC_VLAN ||
lkup_type == ICE_SW_LKUP_DFLT ||
lkup_type == ICE_SW_LKUP_LAST)
rule_type = remove ? ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR :
ICE_AQC_SW_RULES_T_VSI_LIST_SET;
else if (lkup_type == ICE_SW_LKUP_VLAN)
rule_type = remove ? ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR :
ICE_AQC_SW_RULES_T_PRUNE_LIST_SET;
else
return ICE_ERR_PARAM;
s_rule_size = (u16)ice_struct_size(s_rule, vsi, num_vsi);
s_rule = (struct ice_sw_rule_vsi_list *)ice_malloc(hw, s_rule_size);
if (!s_rule)
return ICE_ERR_NO_MEMORY;
for (i = 0; i < num_vsi; i++) {
if (!ice_is_vsi_valid(hw, vsi_handle_arr[i])) {
status = ICE_ERR_PARAM;
goto exit;
}
/* AQ call requires hw_vsi_id(s) */
s_rule->vsi[i] =
CPU_TO_LE16(ice_get_hw_vsi_num(hw, vsi_handle_arr[i]));
}
s_rule->hdr.type = CPU_TO_LE16(rule_type);
s_rule->number_vsi = CPU_TO_LE16(num_vsi);
s_rule->index = CPU_TO_LE16(vsi_list_id);
status = ice_aq_sw_rules(hw, s_rule, s_rule_size, 1, opc, NULL);
exit:
ice_free(hw, s_rule);
return status;
}
/**
* ice_create_vsi_list_rule - Creates and populates a VSI list rule
* @hw: pointer to the HW struct
* @vsi_handle_arr: array of VSI handles to form a VSI list
* @num_vsi: number of VSI handles in the array
* @vsi_list_id: stores the ID of the VSI list to be created
* @lkup_type: switch rule filter's lookup type
*/
static int
ice_create_vsi_list_rule(struct ice_hw *hw, u16 *vsi_handle_arr, u16 num_vsi,
u16 *vsi_list_id, enum ice_sw_lkup_type lkup_type)
{
int status;
status = ice_aq_alloc_free_vsi_list(hw, vsi_list_id, lkup_type,
ice_aqc_opc_alloc_res);
if (status)
return status;
/* Update the newly created VSI list to include the specified VSIs */
return ice_update_vsi_list_rule(hw, vsi_handle_arr, num_vsi,
*vsi_list_id, false,
ice_aqc_opc_add_sw_rules, lkup_type);
}
/**
* ice_create_pkt_fwd_rule
* @hw: pointer to the hardware structure
* @recp_list: corresponding filter management list
* @f_entry: entry containing packet forwarding information
*
* Create switch rule with given filter information and add an entry
* to the corresponding filter management list to track this switch rule
* and VSI mapping
*/
static int
ice_create_pkt_fwd_rule(struct ice_hw *hw, struct ice_sw_recipe *recp_list,
struct ice_fltr_list_entry *f_entry)
{
struct ice_fltr_mgmt_list_entry *fm_entry;
struct ice_sw_rule_lkup_rx_tx *s_rule;
int status;
s_rule = (struct ice_sw_rule_lkup_rx_tx *)
ice_malloc(hw, ice_struct_size(s_rule, hdr_data,
DUMMY_ETH_HDR_LEN));
if (!s_rule)
return ICE_ERR_NO_MEMORY;
fm_entry = (struct ice_fltr_mgmt_list_entry *)
ice_malloc(hw, sizeof(*fm_entry));
if (!fm_entry) {
status = ICE_ERR_NO_MEMORY;
goto ice_create_pkt_fwd_rule_exit;
}
fm_entry->fltr_info = f_entry->fltr_info;
/* Initialize all the fields for the management entry */
fm_entry->vsi_count = 1;
fm_entry->lg_act_idx = ICE_INVAL_LG_ACT_INDEX;
fm_entry->sw_marker_id = ICE_INVAL_SW_MARKER_ID;
fm_entry->counter_index = ICE_INVAL_COUNTER_ID;
ice_fill_sw_rule(hw, &fm_entry->fltr_info, s_rule,
ice_aqc_opc_add_sw_rules);
status = ice_aq_sw_rules(hw, s_rule,
ice_struct_size(s_rule, hdr_data,
DUMMY_ETH_HDR_LEN),
1, ice_aqc_opc_add_sw_rules, NULL);
if (status) {
ice_free(hw, fm_entry);
goto ice_create_pkt_fwd_rule_exit;
}
f_entry->fltr_info.fltr_rule_id = LE16_TO_CPU(s_rule->index);
fm_entry->fltr_info.fltr_rule_id = LE16_TO_CPU(s_rule->index);
/* The book keeping entries will get removed when base driver
* calls remove filter AQ command
*/
LIST_ADD(&fm_entry->list_entry, &recp_list->filt_rules);
ice_create_pkt_fwd_rule_exit:
ice_free(hw, s_rule);
return status;
}
/**
* ice_update_pkt_fwd_rule
* @hw: pointer to the hardware structure
* @f_info: filter information for switch rule
*
* Call AQ command to update a previously created switch rule with a
* VSI list ID
*/
static int
ice_update_pkt_fwd_rule(struct ice_hw *hw, struct ice_fltr_info *f_info)
{
struct ice_sw_rule_lkup_rx_tx *s_rule;
int status;
s_rule = (struct ice_sw_rule_lkup_rx_tx *)
ice_malloc(hw, ice_struct_size(s_rule, hdr_data,
DUMMY_ETH_HDR_LEN));
if (!s_rule)
return ICE_ERR_NO_MEMORY;
ice_fill_sw_rule(hw, f_info, s_rule, ice_aqc_opc_update_sw_rules);
s_rule->index = CPU_TO_LE16(f_info->fltr_rule_id);
/* Update switch rule with new rule set to forward VSI list */
status = ice_aq_sw_rules(hw, s_rule,
ice_struct_size(s_rule, hdr_data,
DUMMY_ETH_HDR_LEN),
1, ice_aqc_opc_update_sw_rules, NULL);
ice_free(hw, s_rule);
return status;
}
/**
* ice_update_sw_rule_bridge_mode
* @hw: pointer to the HW struct
*
* Updates unicast switch filter rules based on VEB/VEPA mode
*/
int ice_update_sw_rule_bridge_mode(struct ice_hw *hw)
{
struct ice_fltr_mgmt_list_entry *fm_entry;
struct LIST_HEAD_TYPE *rule_head;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
struct ice_switch_info *sw;
int status = 0;
sw = hw->switch_info;
rule_lock = &sw->recp_list[ICE_SW_LKUP_MAC].filt_rule_lock;
rule_head = &sw->recp_list[ICE_SW_LKUP_MAC].filt_rules;
ice_acquire_lock(rule_lock);
LIST_FOR_EACH_ENTRY(fm_entry, rule_head, ice_fltr_mgmt_list_entry,
list_entry) {
struct ice_fltr_info *fi = &fm_entry->fltr_info;
u8 *addr = fi->l_data.mac.mac_addr;
/* Update unicast Tx rules to reflect the selected
* VEB/VEPA mode
*/
if ((fi->flag & ICE_FLTR_TX) && IS_UNICAST_ETHER_ADDR(addr) &&
(fi->fltr_act == ICE_FWD_TO_VSI ||
fi->fltr_act == ICE_FWD_TO_VSI_LIST ||
fi->fltr_act == ICE_FWD_TO_Q ||
fi->fltr_act == ICE_FWD_TO_QGRP)) {
status = ice_update_pkt_fwd_rule(hw, fi);
if (status)
break;
}
}
ice_release_lock(rule_lock);
return status;
}
/**
* ice_add_update_vsi_list
* @hw: pointer to the hardware structure
* @m_entry: pointer to current filter management list entry
* @cur_fltr: filter information from the book keeping entry
* @new_fltr: filter information with the new VSI to be added
*
* Call AQ command to add or update previously created VSI list with new VSI.
*
* Helper function to do book keeping associated with adding filter information
* The algorithm to do the book keeping is described below :
* When a VSI needs to subscribe to a given filter (MAC/VLAN/Ethtype etc.)
* if only one VSI has been added till now
* Allocate a new VSI list and add two VSIs
* to this list using switch rule command
* Update the previously created switch rule with the
* newly created VSI list ID
* if a VSI list was previously created
* Add the new VSI to the previously created VSI list set
* using the update switch rule command
*/
static int
ice_add_update_vsi_list(struct ice_hw *hw,
struct ice_fltr_mgmt_list_entry *m_entry,
struct ice_fltr_info *cur_fltr,
struct ice_fltr_info *new_fltr)
{
u16 vsi_list_id = 0;
int status = 0;
if ((cur_fltr->fltr_act == ICE_FWD_TO_Q ||
cur_fltr->fltr_act == ICE_FWD_TO_QGRP))
return ICE_ERR_NOT_IMPL;
if ((new_fltr->fltr_act == ICE_FWD_TO_Q ||
new_fltr->fltr_act == ICE_FWD_TO_QGRP) &&
(cur_fltr->fltr_act == ICE_FWD_TO_VSI ||
cur_fltr->fltr_act == ICE_FWD_TO_VSI_LIST))
return ICE_ERR_NOT_IMPL;
if (m_entry->vsi_count < 2 && !m_entry->vsi_list_info) {
/* Only one entry existed in the mapping and it was not already
* a part of a VSI list. So, create a VSI list with the old and
* new VSIs.
*/
struct ice_fltr_info tmp_fltr;
u16 vsi_handle_arr[2];
/* A rule already exists with the new VSI being added */
if (cur_fltr->vsi_handle == new_fltr->vsi_handle)
return ICE_ERR_ALREADY_EXISTS;
vsi_handle_arr[0] = cur_fltr->vsi_handle;
vsi_handle_arr[1] = new_fltr->vsi_handle;
status = ice_create_vsi_list_rule(hw, &vsi_handle_arr[0], 2,
&vsi_list_id,
new_fltr->lkup_type);
if (status)
return status;
tmp_fltr = *new_fltr;
tmp_fltr.fltr_rule_id = cur_fltr->fltr_rule_id;
tmp_fltr.fltr_act = ICE_FWD_TO_VSI_LIST;
tmp_fltr.fwd_id.vsi_list_id = vsi_list_id;
/* Update the previous switch rule of "MAC forward to VSI" to
* "MAC fwd to VSI list"
*/
status = ice_update_pkt_fwd_rule(hw, &tmp_fltr);
if (status)
return status;
cur_fltr->fwd_id.vsi_list_id = vsi_list_id;
cur_fltr->fltr_act = ICE_FWD_TO_VSI_LIST;
m_entry->vsi_list_info =
ice_create_vsi_list_map(hw, &vsi_handle_arr[0], 2,
vsi_list_id);
if (!m_entry->vsi_list_info)
return ICE_ERR_NO_MEMORY;
/* If this entry was large action then the large action needs
* to be updated to point to FWD to VSI list
*/
if (m_entry->sw_marker_id != ICE_INVAL_SW_MARKER_ID)
status =
ice_add_marker_act(hw, m_entry,
m_entry->sw_marker_id,
m_entry->lg_act_idx);
} else {
u16 vsi_handle = new_fltr->vsi_handle;
enum ice_adminq_opc opcode;
if (!m_entry->vsi_list_info)
return ICE_ERR_CFG;
/* A rule already exists with the new VSI being added */
if (ice_is_bit_set(m_entry->vsi_list_info->vsi_map, vsi_handle))
return ICE_ERR_ALREADY_EXISTS;
/* Update the previously created VSI list set with
* the new VSI ID passed in
*/
vsi_list_id = cur_fltr->fwd_id.vsi_list_id;
opcode = ice_aqc_opc_update_sw_rules;
status = ice_update_vsi_list_rule(hw, &vsi_handle, 1,
vsi_list_id, false, opcode,
new_fltr->lkup_type);
/* update VSI list mapping info with new VSI ID */
if (!status)
ice_set_bit(vsi_handle,
m_entry->vsi_list_info->vsi_map);
}
if (!status)
m_entry->vsi_count++;
return status;
}
/**
* ice_find_rule_entry - Search a rule entry
* @list_head: head of rule list
* @f_info: rule information
*
* Helper function to search for a given rule entry
* Returns pointer to entry storing the rule if found
*/
static struct ice_fltr_mgmt_list_entry *
ice_find_rule_entry(struct LIST_HEAD_TYPE *list_head,
struct ice_fltr_info *f_info)
{
struct ice_fltr_mgmt_list_entry *list_itr, *ret = NULL;
LIST_FOR_EACH_ENTRY(list_itr, list_head, ice_fltr_mgmt_list_entry,
list_entry) {
if (!memcmp(&f_info->l_data, &list_itr->fltr_info.l_data,
sizeof(f_info->l_data)) &&
f_info->flag == list_itr->fltr_info.flag) {
ret = list_itr;
break;
}
}
return ret;
}
/**
* ice_find_vsi_list_entry - Search VSI list map with VSI count 1
* @recp_list: VSI lists needs to be searched
* @vsi_handle: VSI handle to be found in VSI list
* @vsi_list_id: VSI list ID found containing vsi_handle
*
* Helper function to search a VSI list with single entry containing given VSI
* handle element. This can be extended further to search VSI list with more
* than 1 vsi_count. Returns pointer to VSI list entry if found.
*/
struct ice_vsi_list_map_info *
ice_find_vsi_list_entry(struct ice_sw_recipe *recp_list, u16 vsi_handle,
u16 *vsi_list_id)
{
struct ice_vsi_list_map_info *map_info = NULL;
struct LIST_HEAD_TYPE *list_head;
list_head = &recp_list->filt_rules;
if (recp_list->adv_rule) {
struct ice_adv_fltr_mgmt_list_entry *list_itr;
LIST_FOR_EACH_ENTRY(list_itr, list_head,
ice_adv_fltr_mgmt_list_entry,
list_entry) {
if (list_itr->vsi_list_info) {
map_info = list_itr->vsi_list_info;
if (ice_is_bit_set(map_info->vsi_map,
vsi_handle)) {
*vsi_list_id = map_info->vsi_list_id;
return map_info;
}
}
}
} else {
struct ice_fltr_mgmt_list_entry *list_itr;
LIST_FOR_EACH_ENTRY(list_itr, list_head,
ice_fltr_mgmt_list_entry,
list_entry) {
if (list_itr->vsi_count == 1 &&
list_itr->vsi_list_info) {
map_info = list_itr->vsi_list_info;
if (ice_is_bit_set(map_info->vsi_map,
vsi_handle)) {
*vsi_list_id = map_info->vsi_list_id;
return map_info;
}
}
}
}
return NULL;
}
/**
* ice_add_rule_internal - add rule for a given lookup type
* @hw: pointer to the hardware structure
* @recp_list: recipe list for which rule has to be added
* @lport: logic port number on which function add rule
* @f_entry: structure containing MAC forwarding information
*
* Adds or updates the rule lists for a given recipe
*/
static int
ice_add_rule_internal(struct ice_hw *hw, struct ice_sw_recipe *recp_list,
u8 lport, struct ice_fltr_list_entry *f_entry)
{
struct ice_fltr_info *new_fltr, *cur_fltr;
struct ice_fltr_mgmt_list_entry *m_entry;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
int status = 0;
if (!ice_is_vsi_valid(hw, f_entry->fltr_info.vsi_handle))
return ICE_ERR_PARAM;
/* Load the hw_vsi_id only if the fwd action is fwd to VSI */
if (f_entry->fltr_info.fltr_act == ICE_FWD_TO_VSI)
f_entry->fltr_info.fwd_id.hw_vsi_id =
ice_get_hw_vsi_num(hw, f_entry->fltr_info.vsi_handle);
rule_lock = &recp_list->filt_rule_lock;
ice_acquire_lock(rule_lock);
new_fltr = &f_entry->fltr_info;
if (new_fltr->flag & ICE_FLTR_RX)
new_fltr->src = lport;
else if (new_fltr->flag & (ICE_FLTR_TX | ICE_FLTR_RX_LB))
new_fltr->src =
ice_get_hw_vsi_num(hw, f_entry->fltr_info.vsi_handle);
m_entry = ice_find_rule_entry(&recp_list->filt_rules, new_fltr);
if (!m_entry) {
status = ice_create_pkt_fwd_rule(hw, recp_list, f_entry);
goto exit_add_rule_internal;
}
cur_fltr = &m_entry->fltr_info;
status = ice_add_update_vsi_list(hw, m_entry, cur_fltr, new_fltr);
exit_add_rule_internal:
ice_release_lock(rule_lock);
return status;
}
/**
* ice_remove_vsi_list_rule
* @hw: pointer to the hardware structure
* @vsi_list_id: VSI list ID generated as part of allocate resource
* @lkup_type: switch rule filter lookup type
*
* The VSI list should be emptied before this function is called to remove the
* VSI list.
*/
static int
ice_remove_vsi_list_rule(struct ice_hw *hw, u16 vsi_list_id,
enum ice_sw_lkup_type lkup_type)
{
/* Free the vsi_list resource that we allocated. It is assumed that the
* list is empty at this point.
*/
return ice_aq_alloc_free_vsi_list(hw, &vsi_list_id, lkup_type,
ice_aqc_opc_free_res);
}
/**
* ice_rem_update_vsi_list
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle of the VSI to remove
* @fm_list: filter management entry for which the VSI list management needs to
* be done
*/
static int
ice_rem_update_vsi_list(struct ice_hw *hw, u16 vsi_handle,
struct ice_fltr_mgmt_list_entry *fm_list)
{
enum ice_sw_lkup_type lkup_type;
u16 vsi_list_id;
int status = 0;
if (fm_list->fltr_info.fltr_act != ICE_FWD_TO_VSI_LIST ||
fm_list->vsi_count == 0)
return ICE_ERR_PARAM;
/* A rule with the VSI being removed does not exist */
if (!ice_is_bit_set(fm_list->vsi_list_info->vsi_map, vsi_handle))
return ICE_ERR_DOES_NOT_EXIST;
lkup_type = fm_list->fltr_info.lkup_type;
vsi_list_id = fm_list->fltr_info.fwd_id.vsi_list_id;
status = ice_update_vsi_list_rule(hw, &vsi_handle, 1, vsi_list_id, true,
ice_aqc_opc_update_sw_rules,
lkup_type);
if (status)
return status;
fm_list->vsi_count--;
ice_clear_bit(vsi_handle, fm_list->vsi_list_info->vsi_map);
if (fm_list->vsi_count == 1 && lkup_type != ICE_SW_LKUP_VLAN) {
struct ice_fltr_info tmp_fltr_info = fm_list->fltr_info;
struct ice_vsi_list_map_info *vsi_list_info =
fm_list->vsi_list_info;
u16 rem_vsi_handle;
rem_vsi_handle = ice_find_first_bit(vsi_list_info->vsi_map,
ICE_MAX_VSI);
if (!ice_is_vsi_valid(hw, rem_vsi_handle))
return ICE_ERR_OUT_OF_RANGE;
/* Make sure VSI list is empty before removing it below */
status = ice_update_vsi_list_rule(hw, &rem_vsi_handle, 1,
vsi_list_id, true,
ice_aqc_opc_update_sw_rules,
lkup_type);
if (status)
return status;
tmp_fltr_info.fltr_act = ICE_FWD_TO_VSI;
tmp_fltr_info.fwd_id.hw_vsi_id =
ice_get_hw_vsi_num(hw, rem_vsi_handle);
tmp_fltr_info.vsi_handle = rem_vsi_handle;
status = ice_update_pkt_fwd_rule(hw, &tmp_fltr_info);
if (status) {
ice_debug(hw, ICE_DBG_SW, "Failed to update pkt fwd rule to FWD_TO_VSI on HW VSI %d, error %d\n",
tmp_fltr_info.fwd_id.hw_vsi_id, status);
return status;
}
fm_list->fltr_info = tmp_fltr_info;
}
if ((fm_list->vsi_count == 1 && lkup_type != ICE_SW_LKUP_VLAN) ||
(fm_list->vsi_count == 0 && lkup_type == ICE_SW_LKUP_VLAN)) {
struct ice_vsi_list_map_info *vsi_list_info =
fm_list->vsi_list_info;
/* Remove the VSI list since it is no longer used */
status = ice_remove_vsi_list_rule(hw, vsi_list_id, lkup_type);
if (status) {
ice_debug(hw, ICE_DBG_SW, "Failed to remove VSI list %d, error %d\n",
vsi_list_id, status);
return status;
}
LIST_DEL(&vsi_list_info->list_entry);
ice_free(hw, vsi_list_info);
fm_list->vsi_list_info = NULL;
}
return status;
}
/**
* ice_remove_rule_internal - Remove a filter rule of a given type
* @hw: pointer to the hardware structure
* @recp_list: recipe list for which the rule needs to removed
* @f_entry: rule entry containing filter information
*/
static int
ice_remove_rule_internal(struct ice_hw *hw, struct ice_sw_recipe *recp_list,
struct ice_fltr_list_entry *f_entry)
{
struct ice_fltr_mgmt_list_entry *list_elem;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
bool remove_rule = false;
int status = 0;
u16 vsi_handle;
if (!ice_is_vsi_valid(hw, f_entry->fltr_info.vsi_handle))
return ICE_ERR_PARAM;
f_entry->fltr_info.fwd_id.hw_vsi_id =
ice_get_hw_vsi_num(hw, f_entry->fltr_info.vsi_handle);
rule_lock = &recp_list->filt_rule_lock;
ice_acquire_lock(rule_lock);
list_elem = ice_find_rule_entry(&recp_list->filt_rules,
&f_entry->fltr_info);
if (!list_elem) {
status = ICE_ERR_DOES_NOT_EXIST;
goto exit;
}
if (list_elem->fltr_info.fltr_act != ICE_FWD_TO_VSI_LIST) {
remove_rule = true;
} else if (!list_elem->vsi_list_info) {
status = ICE_ERR_DOES_NOT_EXIST;
goto exit;
} else if (list_elem->vsi_list_info->ref_cnt > 1) {
/* a ref_cnt > 1 indicates that the vsi_list is being
* shared by multiple rules. Decrement the ref_cnt and
* remove this rule, but do not modify the list, as it
* is in-use by other rules.
*/
list_elem->vsi_list_info->ref_cnt--;
remove_rule = true;
} else {
/* a ref_cnt of 1 indicates the vsi_list is only used
* by one rule. However, the original removal request is only
* for a single VSI. Update the vsi_list first, and only
* remove the rule if there are no further VSIs in this list.
*/
vsi_handle = f_entry->fltr_info.vsi_handle;
status = ice_rem_update_vsi_list(hw, vsi_handle, list_elem);
if (status)
goto exit;
/* if VSI count goes to zero after updating the VSI list */
if (list_elem->vsi_count == 0)
remove_rule = true;
}
if (remove_rule) {
/* Remove the lookup rule */
struct ice_sw_rule_lkup_rx_tx *s_rule;
s_rule = (struct ice_sw_rule_lkup_rx_tx *)
ice_malloc(hw, ice_struct_size(s_rule, hdr_data, 0));
if (!s_rule) {
status = ICE_ERR_NO_MEMORY;
goto exit;
}
ice_fill_sw_rule(hw, &list_elem->fltr_info, s_rule,
ice_aqc_opc_remove_sw_rules);
status = ice_aq_sw_rules(hw, s_rule,
ice_struct_size(s_rule, hdr_data, 0),
1, ice_aqc_opc_remove_sw_rules, NULL);
/* Remove a book keeping from the list */
ice_free(hw, s_rule);
if (status)
goto exit;
LIST_DEL(&list_elem->list_entry);
ice_free(hw, list_elem);
}
exit:
ice_release_lock(rule_lock);
return status;
}
/**
* ice_aq_get_res_alloc - get allocated resources
* @hw: pointer to the HW struct
* @num_entries: pointer to u16 to store the number of resource entries returned
* @buf: pointer to buffer
* @buf_size: size of buf
* @cd: pointer to command details structure or NULL
*
* The caller-supplied buffer must be large enough to store the resource
* information for all resource types. Each resource type is an
* ice_aqc_get_res_resp_elem structure.
*/
int
ice_aq_get_res_alloc(struct ice_hw *hw, u16 *num_entries,
struct ice_aqc_get_res_resp_elem *buf, u16 buf_size,
struct ice_sq_cd *cd)
{
struct ice_aqc_get_res_alloc *resp;
struct ice_aq_desc desc;
int status;
if (!buf)
return ICE_ERR_BAD_PTR;
if (buf_size < ICE_AQ_GET_RES_ALLOC_BUF_LEN)
return ICE_ERR_INVAL_SIZE;
resp = &desc.params.get_res;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_res_alloc);
status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
if (!status && num_entries)
*num_entries = LE16_TO_CPU(resp->resp_elem_num);
return status;
}
/**
* ice_aq_get_res_descs - get allocated resource descriptors
* @hw: pointer to the hardware structure
* @num_entries: number of resource entries in buffer
* @buf: structure to hold response data buffer
* @buf_size: size of buffer
* @res_type: resource type
* @res_shared: is resource shared
* @desc_id: input - first desc ID to start; output - next desc ID
* @cd: pointer to command details structure or NULL
*/
int
ice_aq_get_res_descs(struct ice_hw *hw, u16 num_entries,
struct ice_aqc_res_elem *buf, u16 buf_size, u16 res_type,
bool res_shared, u16 *desc_id, struct ice_sq_cd *cd)
{
struct ice_aqc_get_allocd_res_desc *cmd;
struct ice_aq_desc desc;
int status;
ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
cmd = &desc.params.get_res_desc;
if (!buf)
return ICE_ERR_PARAM;
if (buf_size != (num_entries * sizeof(*buf)))
return ICE_ERR_PARAM;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_allocd_res_desc);
cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
ICE_AQC_RES_TYPE_M) | (res_shared ?
ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
cmd->ops.cmd.first_desc = CPU_TO_LE16(*desc_id);
status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
if (!status)
*desc_id = LE16_TO_CPU(cmd->ops.resp.next_desc);
return status;
}
/**
* ice_add_mac_rule_with_fltr_flag - Add a MAC address based filter rule
* @hw: pointer to the hardware structure
* @m_list: list of MAC addresses and forwarding information
* @sw: pointer to switch info struct for which function add rule
* @lport: logic port number on which function add rule
* @flag: filter flag
*
* IMPORTANT: When the umac_shared flag is set to false and m_list has
* multiple unicast addresses, the function assumes that all the
* addresses are unique in a given add_mac call. It doesn't
* check for duplicates in this case, removing duplicates from a given
* list should be taken care of in the caller of this function.
*/
static int
ice_add_mac_rule_with_fltr_flag(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list,
struct ice_switch_info *sw, u8 lport, u16 flag)
{
struct ice_sw_recipe *recp_list = &sw->recp_list[ICE_SW_LKUP_MAC];
struct ice_sw_rule_lkup_rx_tx *s_rule, *r_iter;
struct ice_fltr_list_entry *m_list_itr;
struct LIST_HEAD_TYPE *rule_head;
u16 total_elem_left, s_rule_size;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
u16 num_unicast = 0;
int status = 0;
u8 elem_sent;
s_rule = NULL;
rule_lock = &recp_list->filt_rule_lock;
rule_head = &recp_list->filt_rules;
LIST_FOR_EACH_ENTRY(m_list_itr, m_list, ice_fltr_list_entry,
list_entry) {
u8 *add = &m_list_itr->fltr_info.l_data.mac.mac_addr[0];
u16 vsi_handle;
u16 hw_vsi_id;
m_list_itr->fltr_info.flag = flag;
vsi_handle = m_list_itr->fltr_info.vsi_handle;
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
hw_vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
if (m_list_itr->fltr_info.fltr_act == ICE_FWD_TO_VSI)
m_list_itr->fltr_info.fwd_id.hw_vsi_id = hw_vsi_id;
/* update the src in case it is VSI num */
if (m_list_itr->fltr_info.src_id != ICE_SRC_ID_VSI)
return ICE_ERR_PARAM;
m_list_itr->fltr_info.src = hw_vsi_id;
if (m_list_itr->fltr_info.lkup_type != ICE_SW_LKUP_MAC ||
IS_ZERO_ETHER_ADDR(add))
return ICE_ERR_PARAM;
if (IS_UNICAST_ETHER_ADDR(add) && !hw->umac_shared) {
/* Don't overwrite the unicast address */
ice_acquire_lock(rule_lock);
if (ice_find_rule_entry(rule_head,
&m_list_itr->fltr_info)) {
ice_release_lock(rule_lock);
continue;
}
ice_release_lock(rule_lock);
num_unicast++;
} else if (IS_MULTICAST_ETHER_ADDR(add) ||
(IS_UNICAST_ETHER_ADDR(add) && hw->umac_shared)) {
m_list_itr->status =
ice_add_rule_internal(hw, recp_list, lport,
m_list_itr);
if (m_list_itr->status)
return m_list_itr->status;
}
}
ice_acquire_lock(rule_lock);
/* Exit if no suitable entries were found for adding bulk switch rule */
if (!num_unicast) {
status = 0;
goto ice_add_mac_exit;
}
/* Allocate switch rule buffer for the bulk update for unicast */
s_rule_size = ice_struct_size(s_rule, hdr_data, DUMMY_ETH_HDR_LEN);
s_rule = (struct ice_sw_rule_lkup_rx_tx *)
ice_calloc(hw, num_unicast, s_rule_size);
if (!s_rule) {
status = ICE_ERR_NO_MEMORY;
goto ice_add_mac_exit;
}
r_iter = s_rule;
LIST_FOR_EACH_ENTRY(m_list_itr, m_list, ice_fltr_list_entry,
list_entry) {
struct ice_fltr_info *f_info = &m_list_itr->fltr_info;
u8 *mac_addr = &f_info->l_data.mac.mac_addr[0];
if (IS_UNICAST_ETHER_ADDR(mac_addr)) {
ice_fill_sw_rule(hw, &m_list_itr->fltr_info, r_iter,
ice_aqc_opc_add_sw_rules);
r_iter = (struct ice_sw_rule_lkup_rx_tx *)
((u8 *)r_iter + s_rule_size);
}
}
/* Call AQ bulk switch rule update for all unicast addresses */
r_iter = s_rule;
/* Call AQ switch rule in AQ_MAX chunk */
for (total_elem_left = num_unicast; total_elem_left > 0;
total_elem_left -= elem_sent) {
struct ice_sw_rule_lkup_rx_tx *entry = r_iter;
elem_sent = MIN_T(u8, total_elem_left,
(ICE_AQ_MAX_BUF_LEN / s_rule_size));
status = ice_aq_sw_rules(hw, entry, elem_sent * s_rule_size,
elem_sent, ice_aqc_opc_add_sw_rules,
NULL);
if (status)
goto ice_add_mac_exit;
r_iter = (struct ice_sw_rule_lkup_rx_tx *)
((u8 *)r_iter + (elem_sent * s_rule_size));
}
/* Fill up rule ID based on the value returned from FW */
r_iter = s_rule;
LIST_FOR_EACH_ENTRY(m_list_itr, m_list, ice_fltr_list_entry,
list_entry) {
struct ice_fltr_info *f_info = &m_list_itr->fltr_info;
u8 *mac_addr = &f_info->l_data.mac.mac_addr[0];
struct ice_fltr_mgmt_list_entry *fm_entry;
if (IS_UNICAST_ETHER_ADDR(mac_addr)) {
f_info->fltr_rule_id =
LE16_TO_CPU(r_iter->index);
f_info->fltr_act = ICE_FWD_TO_VSI;
/* Create an entry to track this MAC address */
fm_entry = (struct ice_fltr_mgmt_list_entry *)
ice_malloc(hw, sizeof(*fm_entry));
if (!fm_entry) {
status = ICE_ERR_NO_MEMORY;
goto ice_add_mac_exit;
}
fm_entry->fltr_info = *f_info;
fm_entry->vsi_count = 1;
/* The book keeping entries will get removed when
* base driver calls remove filter AQ command
*/
LIST_ADD(&fm_entry->list_entry, rule_head);
r_iter = (struct ice_sw_rule_lkup_rx_tx *)
((u8 *)r_iter + s_rule_size);
}
}
ice_add_mac_exit:
ice_release_lock(rule_lock);
if (s_rule)
ice_free(hw, s_rule);
return status;
}
/**
* ice_add_mac_rule - Add a MAC address based filter rule
* @hw: pointer to the hardware structure
* @m_list: list of MAC addresses and forwarding information
* @sw: pointer to switch info struct for which function add rule
* @lport: logic port number on which function add rule
*
* IMPORTANT: When the umac_shared flag is set to false and m_list has
* multiple unicast addresses, the function assumes that all the
* addresses are unique in a given add_mac call. It doesn't
* check for duplicates in this case, removing duplicates from a given
* list should be taken care of in the caller of this function.
*/
static int
ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list,
struct ice_switch_info *sw, u8 lport)
{
return ice_add_mac_rule_with_fltr_flag(hw, m_list, sw, lport, ICE_FLTR_TX);
}
/**
* ice_add_mac - Add a MAC address based filter rule
* @hw: pointer to the hardware structure
* @m_list: list of MAC addresses and forwarding information
*
* Function add MAC rule for logical port from HW struct
*/
int ice_add_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list)
{
if (!m_list || !hw)
return ICE_ERR_PARAM;
return ice_add_mac_rule(hw, m_list, hw->switch_info,
hw->port_info->lport);
}
/**
* ice_add_mac_with_fltr_flag - Add a MAC address based filter rule
* @hw: pointer to the hardware structure
* @m_list: list of MAC addresses and forwarding information
* @flag: filter flag
*
* Function add MAC rule for logical port from HW struct
*/
int ice_add_mac_with_fltr_flag(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list, u16 flag)
{
if (!m_list || !hw)
return ICE_ERR_PARAM;
return ice_add_mac_rule_with_fltr_flag(hw, m_list, hw->switch_info,
hw->port_info->lport, flag);
}
/**
* ice_add_vlan_internal - Add one VLAN based filter rule
* @hw: pointer to the hardware structure
* @recp_list: recipe list for which rule has to be added
* @f_entry: filter entry containing one VLAN information
*/
static int
ice_add_vlan_internal(struct ice_hw *hw, struct ice_sw_recipe *recp_list,
struct ice_fltr_list_entry *f_entry)
{
struct ice_fltr_mgmt_list_entry *v_list_itr;
struct ice_fltr_info *new_fltr, *cur_fltr;
enum ice_sw_lkup_type lkup_type;
u16 vsi_list_id = 0, vsi_handle;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
int status = 0;
if (!ice_is_vsi_valid(hw, f_entry->fltr_info.vsi_handle))
return ICE_ERR_PARAM;
f_entry->fltr_info.fwd_id.hw_vsi_id =
ice_get_hw_vsi_num(hw, f_entry->fltr_info.vsi_handle);
new_fltr = &f_entry->fltr_info;
/* VLAN ID should only be 12 bits */
if (new_fltr->l_data.vlan.vlan_id > ICE_MAX_VLAN_ID)
return ICE_ERR_PARAM;
if (new_fltr->src_id != ICE_SRC_ID_VSI)
return ICE_ERR_PARAM;
new_fltr->src = new_fltr->fwd_id.hw_vsi_id;
lkup_type = new_fltr->lkup_type;
vsi_handle = new_fltr->vsi_handle;
rule_lock = &recp_list->filt_rule_lock;
ice_acquire_lock(rule_lock);
v_list_itr = ice_find_rule_entry(&recp_list->filt_rules, new_fltr);
if (!v_list_itr) {
struct ice_vsi_list_map_info *map_info = NULL;
if (new_fltr->fltr_act == ICE_FWD_TO_VSI) {
/* All VLAN pruning rules use a VSI list. Check if
* there is already a VSI list containing VSI that we
* want to add. If found, use the same vsi_list_id for
* this new VLAN rule or else create a new list.
*/
map_info = ice_find_vsi_list_entry(recp_list,
vsi_handle,
&vsi_list_id);
if (!map_info) {
status = ice_create_vsi_list_rule(hw,
&vsi_handle,
1,
&vsi_list_id,
lkup_type);
if (status)
goto exit;
}
/* Convert the action to forwarding to a VSI list. */
new_fltr->fltr_act = ICE_FWD_TO_VSI_LIST;
new_fltr->fwd_id.vsi_list_id = vsi_list_id;
}
status = ice_create_pkt_fwd_rule(hw, recp_list, f_entry);
if (!status) {
v_list_itr = ice_find_rule_entry(&recp_list->filt_rules,
new_fltr);
if (!v_list_itr) {
status = ICE_ERR_DOES_NOT_EXIST;
goto exit;
}
/* reuse VSI list for new rule and increment ref_cnt */
if (map_info) {
v_list_itr->vsi_list_info = map_info;
map_info->ref_cnt++;
} else {
v_list_itr->vsi_list_info =
ice_create_vsi_list_map(hw, &vsi_handle,
1, vsi_list_id);
}
}
} else if (v_list_itr->vsi_list_info->ref_cnt == 1) {
/* Update existing VSI list to add new VSI ID only if it used
* by one VLAN rule.
*/
cur_fltr = &v_list_itr->fltr_info;
status = ice_add_update_vsi_list(hw, v_list_itr, cur_fltr,
new_fltr);
} else {
/* If VLAN rule exists and VSI list being used by this rule is
* referenced by more than 1 VLAN rule. Then create a new VSI
* list appending previous VSI with new VSI and update existing
* VLAN rule to point to new VSI list ID
*/
struct ice_fltr_info tmp_fltr;
u16 vsi_handle_arr[2];
u16 cur_handle;
/* Current implementation only supports reusing VSI list with
* one VSI count. We should never hit below condition
*/
if (v_list_itr->vsi_count > 1 &&
v_list_itr->vsi_list_info->ref_cnt > 1) {
ice_debug(hw, ICE_DBG_SW, "Invalid configuration: Optimization to reuse VSI list with more than one VSI is not being done yet\n");
status = ICE_ERR_CFG;
goto exit;
}
cur_handle =
ice_find_first_bit(v_list_itr->vsi_list_info->vsi_map,
ICE_MAX_VSI);
/* A rule already exists with the new VSI being added */
if (cur_handle == vsi_handle) {
status = ICE_ERR_ALREADY_EXISTS;
goto exit;
}
vsi_handle_arr[0] = cur_handle;
vsi_handle_arr[1] = vsi_handle;
status = ice_create_vsi_list_rule(hw, &vsi_handle_arr[0], 2,
&vsi_list_id, lkup_type);
if (status)
goto exit;
tmp_fltr = v_list_itr->fltr_info;
tmp_fltr.fltr_rule_id = v_list_itr->fltr_info.fltr_rule_id;
tmp_fltr.fwd_id.vsi_list_id = vsi_list_id;
tmp_fltr.fltr_act = ICE_FWD_TO_VSI_LIST;
/* Update the previous switch rule to a new VSI list which
* includes current VSI that is requested
*/
status = ice_update_pkt_fwd_rule(hw, &tmp_fltr);
if (status)
goto exit;
/* before overriding VSI list map info. decrement ref_cnt of
* previous VSI list
*/
v_list_itr->vsi_list_info->ref_cnt--;
/* now update to newly created list */
v_list_itr->fltr_info.fwd_id.vsi_list_id = vsi_list_id;
v_list_itr->vsi_list_info =
ice_create_vsi_list_map(hw, &vsi_handle_arr[0], 2,
vsi_list_id);
v_list_itr->vsi_count++;
}
exit:
ice_release_lock(rule_lock);
return status;
}
/**
* ice_add_vlan_rule - Add VLAN based filter rule
* @hw: pointer to the hardware structure
* @v_list: list of VLAN entries and forwarding information
* @sw: pointer to switch info struct for which function add rule
*/
static int
ice_add_vlan_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list,
struct ice_switch_info *sw)
{
struct ice_fltr_list_entry *v_list_itr;
struct ice_sw_recipe *recp_list;
recp_list = &sw->recp_list[ICE_SW_LKUP_VLAN];
LIST_FOR_EACH_ENTRY(v_list_itr, v_list, ice_fltr_list_entry,
list_entry) {
if (v_list_itr->fltr_info.lkup_type != ICE_SW_LKUP_VLAN)
return ICE_ERR_PARAM;
v_list_itr->fltr_info.flag = ICE_FLTR_TX;
v_list_itr->status = ice_add_vlan_internal(hw, recp_list,
v_list_itr);
if (v_list_itr->status)
return v_list_itr->status;
}
return 0;
}
/**
* ice_add_vlan - Add a VLAN based filter rule
* @hw: pointer to the hardware structure
* @v_list: list of VLAN and forwarding information
*
* Function add VLAN rule for logical port from HW struct
*/
int ice_add_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list)
{
if (!v_list || !hw)
return ICE_ERR_PARAM;
return ice_add_vlan_rule(hw, v_list, hw->switch_info);
}
/**
* ice_add_mac_vlan_rule - Add MAC and VLAN pair based filter rule
* @hw: pointer to the hardware structure
* @mv_list: list of MAC and VLAN filters
* @sw: pointer to switch info struct for which function add rule
* @lport: logic port number on which function add rule
*
* If the VSI on which the MAC-VLAN pair has to be added has Rx and Tx VLAN
* pruning bits enabled, then it is the responsibility of the caller to make
* sure to add a VLAN only filter on the same VSI. Packets belonging to that
* VLAN won't be received on that VSI otherwise.
*/
static int
ice_add_mac_vlan_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *mv_list,
struct ice_switch_info *sw, u8 lport)
{
struct ice_fltr_list_entry *mv_list_itr;
struct ice_sw_recipe *recp_list;
if (!mv_list || !hw)
return ICE_ERR_PARAM;
recp_list = &sw->recp_list[ICE_SW_LKUP_MAC_VLAN];
LIST_FOR_EACH_ENTRY(mv_list_itr, mv_list, ice_fltr_list_entry,
list_entry) {
enum ice_sw_lkup_type l_type =
mv_list_itr->fltr_info.lkup_type;
if (l_type != ICE_SW_LKUP_MAC_VLAN)
return ICE_ERR_PARAM;
mv_list_itr->fltr_info.flag = ICE_FLTR_TX;
mv_list_itr->status =
ice_add_rule_internal(hw, recp_list, lport,
mv_list_itr);
if (mv_list_itr->status)
return mv_list_itr->status;
}
return 0;
}
/**
* ice_add_mac_vlan - Add a MAC VLAN address based filter rule
* @hw: pointer to the hardware structure
* @mv_list: list of MAC VLAN addresses and forwarding information
*
* Function add MAC VLAN rule for logical port from HW struct
*/
int
ice_add_mac_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *mv_list)
{
if (!mv_list || !hw)
return ICE_ERR_PARAM;
return ice_add_mac_vlan_rule(hw, mv_list, hw->switch_info,
hw->port_info->lport);
}
/**
* ice_add_eth_mac_rule - Add ethertype and MAC based filter rule
* @hw: pointer to the hardware structure
* @em_list: list of ether type MAC filter, MAC is optional
* @sw: pointer to switch info struct for which function add rule
* @lport: logic port number on which function add rule
*
* This function requires the caller to populate the entries in
* the filter list with the necessary fields (including flags to
* indicate Tx or Rx rules).
*/
static int
ice_add_eth_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *em_list,
struct ice_switch_info *sw, u8 lport)
{
struct ice_fltr_list_entry *em_list_itr;
LIST_FOR_EACH_ENTRY(em_list_itr, em_list, ice_fltr_list_entry,
list_entry) {
struct ice_sw_recipe *recp_list;
enum ice_sw_lkup_type l_type;
l_type = em_list_itr->fltr_info.lkup_type;
recp_list = &sw->recp_list[l_type];
if (l_type != ICE_SW_LKUP_ETHERTYPE_MAC &&
l_type != ICE_SW_LKUP_ETHERTYPE)
return ICE_ERR_PARAM;
em_list_itr->status = ice_add_rule_internal(hw, recp_list,
lport,
em_list_itr);
if (em_list_itr->status)
return em_list_itr->status;
}
return 0;
}
/**
* ice_add_eth_mac - Add a ethertype based filter rule
* @hw: pointer to the hardware structure
* @em_list: list of ethertype and forwarding information
*
* Function add ethertype rule for logical port from HW struct
*/
int
ice_add_eth_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *em_list)
{
if (!em_list || !hw)
return ICE_ERR_PARAM;
return ice_add_eth_mac_rule(hw, em_list, hw->switch_info,
hw->port_info->lport);
}
/**
* ice_remove_eth_mac_rule - Remove an ethertype (or MAC) based filter rule
* @hw: pointer to the hardware structure
* @em_list: list of ethertype or ethertype MAC entries
* @sw: pointer to switch info struct for which function add rule
*/
static int
ice_remove_eth_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *em_list,
struct ice_switch_info *sw)
{
struct ice_fltr_list_entry *em_list_itr, *tmp;
LIST_FOR_EACH_ENTRY_SAFE(em_list_itr, tmp, em_list, ice_fltr_list_entry,
list_entry) {
struct ice_sw_recipe *recp_list;
enum ice_sw_lkup_type l_type;
l_type = em_list_itr->fltr_info.lkup_type;
if (l_type != ICE_SW_LKUP_ETHERTYPE_MAC &&
l_type != ICE_SW_LKUP_ETHERTYPE)
return ICE_ERR_PARAM;
recp_list = &sw->recp_list[l_type];
em_list_itr->status = ice_remove_rule_internal(hw, recp_list,
em_list_itr);
if (em_list_itr->status)
return em_list_itr->status;
}
return 0;
}
/**
* ice_remove_eth_mac - remove a ethertype based filter rule
* @hw: pointer to the hardware structure
* @em_list: list of ethertype and forwarding information
*
*/
int
ice_remove_eth_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *em_list)
{
if (!em_list || !hw)
return ICE_ERR_PARAM;
return ice_remove_eth_mac_rule(hw, em_list, hw->switch_info);
}
/**
* ice_get_lg_act_aqc_res_type - get resource type for a large action
* @res_type: resource type to be filled in case of function success
* @num_acts: number of actions to hold with a large action entry
*
* Get resource type for a large action depending on the number
* of single actions that it contains.
*/
static int
ice_get_lg_act_aqc_res_type(u16 *res_type, int num_acts)
{
if (!res_type)
return ICE_ERR_BAD_PTR;
/* If num_acts is 1, use ICE_AQC_RES_TYPE_WIDE_TABLE_1.
* If num_acts is 2, use ICE_AQC_RES_TYPE_WIDE_TABLE_3.
* If num_acts is greater than 2, then use
* ICE_AQC_RES_TYPE_WIDE_TABLE_4.
* The num_acts cannot be equal to 0 or greater than 4.
*/
switch (num_acts) {
case 1:
*res_type = ICE_AQC_RES_TYPE_WIDE_TABLE_1;
break;
case 2:
*res_type = ICE_AQC_RES_TYPE_WIDE_TABLE_2;
break;
case 3:
case 4:
*res_type = ICE_AQC_RES_TYPE_WIDE_TABLE_4;
break;
default:
return ICE_ERR_PARAM;
}
return 0;
}
/**
* ice_alloc_res_lg_act - add large action resource
* @hw: pointer to the hardware structure
* @l_id: large action ID to fill it in
* @num_acts: number of actions to hold with a large action entry
*/
static int
ice_alloc_res_lg_act(struct ice_hw *hw, u16 *l_id, u16 num_acts)
{
struct ice_aqc_alloc_free_res_elem *sw_buf;
u16 buf_len, res_type;
int status;
if (!l_id)
return ICE_ERR_BAD_PTR;
status = ice_get_lg_act_aqc_res_type(&res_type, num_acts);
if (status)
return status;
/* Allocate resource for large action */
buf_len = ice_struct_size(sw_buf, elem, 1);
sw_buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
if (!sw_buf)
return ICE_ERR_NO_MEMORY;
sw_buf->res_type = CPU_TO_LE16(res_type);
sw_buf->num_elems = CPU_TO_LE16(1);
status = ice_aq_alloc_free_res(hw, 1, sw_buf, buf_len,
ice_aqc_opc_alloc_res, NULL);
if (!status)
*l_id = LE16_TO_CPU(sw_buf->elem[0].e.sw_resp);
ice_free(hw, sw_buf);
return status;
}
/**
* ice_rem_sw_rule_info
* @hw: pointer to the hardware structure
* @rule_head: pointer to the switch list structure that we want to delete
*/
static void
ice_rem_sw_rule_info(struct ice_hw *hw, struct LIST_HEAD_TYPE *rule_head)
{
if (!LIST_EMPTY(rule_head)) {
struct ice_fltr_mgmt_list_entry *entry;
struct ice_fltr_mgmt_list_entry *tmp;
LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, rule_head,
ice_fltr_mgmt_list_entry, list_entry) {
LIST_DEL(&entry->list_entry);
ice_free(hw, entry);
}
}
}
/**
* ice_rem_adv_rule_info
* @hw: pointer to the hardware structure
* @rule_head: pointer to the switch list structure that we want to delete
*/
static void
ice_rem_adv_rule_info(struct ice_hw *hw, struct LIST_HEAD_TYPE *rule_head)
{
struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
struct ice_adv_fltr_mgmt_list_entry *lst_itr;
if (LIST_EMPTY(rule_head))
return;
LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, rule_head,
ice_adv_fltr_mgmt_list_entry, list_entry) {
LIST_DEL(&lst_itr->list_entry);
ice_free(hw, lst_itr->lkups);
ice_free(hw, lst_itr);
}
}
/**
* ice_rem_all_sw_rules_info
* @hw: pointer to the hardware structure
*/
void ice_rem_all_sw_rules_info(struct ice_hw *hw)
{
struct ice_switch_info *sw = hw->switch_info;
u8 i;
for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
struct LIST_HEAD_TYPE *rule_head;
rule_head = &sw->recp_list[i].filt_rules;
if (!sw->recp_list[i].adv_rule)
ice_rem_sw_rule_info(hw, rule_head);
else
ice_rem_adv_rule_info(hw, rule_head);
if (sw->recp_list[i].adv_rule &&
LIST_EMPTY(&sw->recp_list[i].filt_rules))
sw->recp_list[i].adv_rule = false;
}
}
/**
* ice_cfg_dflt_vsi - change state of VSI to set/clear default
* @pi: pointer to the port_info structure
* @vsi_handle: VSI handle to set as default
* @set: true to add the above mentioned switch rule, false to remove it
* @direction: ICE_FLTR_RX or ICE_FLTR_TX
*
* add filter rule to set/unset given VSI as default VSI for the switch
* (represented by swid)
*/
int
ice_cfg_dflt_vsi(struct ice_port_info *pi, u16 vsi_handle, bool set,
u8 direction)
{
struct ice_fltr_list_entry f_list_entry;
struct ice_sw_recipe *recp_list = NULL;
struct ice_fltr_info f_info;
struct ice_hw *hw = pi->hw;
u8 lport = pi->lport;
u16 hw_vsi_id;
int status;
recp_list = &pi->hw->switch_info->recp_list[ICE_SW_LKUP_DFLT];
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
hw_vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
ice_memset(&f_info, 0, sizeof(f_info), ICE_NONDMA_MEM);
f_info.lkup_type = ICE_SW_LKUP_DFLT;
f_info.flag = direction;
f_info.fltr_act = ICE_FWD_TO_VSI;
f_info.fwd_id.hw_vsi_id = hw_vsi_id;
f_info.vsi_handle = vsi_handle;
if (f_info.flag & ICE_FLTR_RX) {
f_info.src = pi->lport;
f_info.src_id = ICE_SRC_ID_LPORT;
} else if (f_info.flag & ICE_FLTR_TX) {
f_info.src_id = ICE_SRC_ID_VSI;
f_info.src = hw_vsi_id;
}
f_list_entry.fltr_info = f_info;
if (set)
status = ice_add_rule_internal(hw, recp_list, lport,
&f_list_entry);
else
status = ice_remove_rule_internal(hw, recp_list,
&f_list_entry);
return status;
}
/**
* ice_check_if_dflt_vsi - check if VSI is default VSI
* @pi: pointer to the port_info structure
* @vsi_handle: vsi handle to check for in filter list
* @rule_exists: indicates if there are any VSI's in the rule list
*
* checks if the VSI is in a default VSI list, and also indicates
* if the default VSI list is empty
*/
bool ice_check_if_dflt_vsi(struct ice_port_info *pi, u16 vsi_handle,
bool *rule_exists)
{
struct ice_fltr_mgmt_list_entry *fm_entry;
struct LIST_HEAD_TYPE *rule_head;
struct ice_sw_recipe *recp_list;
struct ice_lock *rule_lock;
bool ret = false;
recp_list = &pi->hw->switch_info->recp_list[ICE_SW_LKUP_DFLT];
rule_lock = &recp_list->filt_rule_lock;
rule_head = &recp_list->filt_rules;
ice_acquire_lock(rule_lock);
if (rule_exists && !LIST_EMPTY(rule_head))
*rule_exists = true;
LIST_FOR_EACH_ENTRY(fm_entry, rule_head,
ice_fltr_mgmt_list_entry, list_entry) {
if (ice_vsi_uses_fltr(fm_entry, vsi_handle)) {
ret = true;
break;
}
}
ice_release_lock(rule_lock);
return ret;
}
/**
* ice_find_ucast_rule_entry - Search for a unicast MAC filter rule entry
* @list_head: head of rule list
* @f_info: rule information
*
* Helper function to search for a unicast rule entry - this is to be used
* to remove unicast MAC filter that is not shared with other VSIs on the
* PF switch.
*
* Returns pointer to entry storing the rule if found
*/
static struct ice_fltr_mgmt_list_entry *
ice_find_ucast_rule_entry(struct LIST_HEAD_TYPE *list_head,
struct ice_fltr_info *f_info)
{
struct ice_fltr_mgmt_list_entry *list_itr;
LIST_FOR_EACH_ENTRY(list_itr, list_head, ice_fltr_mgmt_list_entry,
list_entry) {
if (!memcmp(&f_info->l_data, &list_itr->fltr_info.l_data,
sizeof(f_info->l_data)) &&
f_info->fwd_id.hw_vsi_id ==
list_itr->fltr_info.fwd_id.hw_vsi_id &&
f_info->flag == list_itr->fltr_info.flag)
return list_itr;
}
return NULL;
}
/**
* ice_remove_mac_rule - remove a MAC based filter rule
* @hw: pointer to the hardware structure
* @m_list: list of MAC addresses and forwarding information
* @recp_list: list from which function remove MAC address
*
* This function removes either a MAC filter rule or a specific VSI from a
* VSI list for a multicast MAC address.
*
* Returns ICE_ERR_DOES_NOT_EXIST if a given entry was not added by
* ice_add_mac. Caller should be aware that this call will only work if all
* the entries passed into m_list were added previously. It will not attempt to
* do a partial remove of entries that were found.
*/
static int
ice_remove_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list,
struct ice_sw_recipe *recp_list)
{
struct ice_fltr_list_entry *list_itr, *tmp;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
if (!m_list)
return ICE_ERR_PARAM;
rule_lock = &recp_list->filt_rule_lock;
LIST_FOR_EACH_ENTRY_SAFE(list_itr, tmp, m_list, ice_fltr_list_entry,
list_entry) {
enum ice_sw_lkup_type l_type = list_itr->fltr_info.lkup_type;
u8 *add = &list_itr->fltr_info.l_data.mac.mac_addr[0];
u16 vsi_handle;
if (l_type != ICE_SW_LKUP_MAC)
return ICE_ERR_PARAM;
vsi_handle = list_itr->fltr_info.vsi_handle;
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
list_itr->fltr_info.fwd_id.hw_vsi_id =
ice_get_hw_vsi_num(hw, vsi_handle);
if (IS_UNICAST_ETHER_ADDR(add) && !hw->umac_shared) {
/* Don't remove the unicast address that belongs to
* another VSI on the switch, since it is not being
* shared...
*/
ice_acquire_lock(rule_lock);
if (!ice_find_ucast_rule_entry(&recp_list->filt_rules,
&list_itr->fltr_info)) {
ice_release_lock(rule_lock);
return ICE_ERR_DOES_NOT_EXIST;
}
ice_release_lock(rule_lock);
}
list_itr->status = ice_remove_rule_internal(hw, recp_list,
list_itr);
if (list_itr->status)
return list_itr->status;
}
return 0;
}
/**
* ice_remove_mac - remove a MAC address based filter rule
* @hw: pointer to the hardware structure
* @m_list: list of MAC addresses and forwarding information
*
*/
int ice_remove_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list)
{
struct ice_sw_recipe *recp_list;
recp_list = &hw->switch_info->recp_list[ICE_SW_LKUP_MAC];
return ice_remove_mac_rule(hw, m_list, recp_list);
}
/**
* ice_remove_vlan_rule - Remove VLAN based filter rule
* @hw: pointer to the hardware structure
* @v_list: list of VLAN entries and forwarding information
* @recp_list: list from which function remove VLAN
*/
static int
ice_remove_vlan_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list,
struct ice_sw_recipe *recp_list)
{
struct ice_fltr_list_entry *v_list_itr, *tmp;
LIST_FOR_EACH_ENTRY_SAFE(v_list_itr, tmp, v_list, ice_fltr_list_entry,
list_entry) {
enum ice_sw_lkup_type l_type = v_list_itr->fltr_info.lkup_type;
if (l_type != ICE_SW_LKUP_VLAN)
return ICE_ERR_PARAM;
v_list_itr->status = ice_remove_rule_internal(hw, recp_list,
v_list_itr);
if (v_list_itr->status)
return v_list_itr->status;
}
return 0;
}
/**
* ice_remove_vlan - remove a VLAN address based filter rule
* @hw: pointer to the hardware structure
* @v_list: list of VLAN and forwarding information
*
*/
int
ice_remove_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list)
{
struct ice_sw_recipe *recp_list;
if (!v_list || !hw)
return ICE_ERR_PARAM;
recp_list = &hw->switch_info->recp_list[ICE_SW_LKUP_VLAN];
return ice_remove_vlan_rule(hw, v_list, recp_list);
}
/**
* ice_remove_mac_vlan_rule - Remove MAC VLAN based filter rule
* @hw: pointer to the hardware structure
* @v_list: list of MAC VLAN entries and forwarding information
* @recp_list: list from which function remove MAC VLAN
*/
static int
ice_remove_mac_vlan_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list,
struct ice_sw_recipe *recp_list)
{
struct ice_fltr_list_entry *v_list_itr, *tmp;
recp_list = &hw->switch_info->recp_list[ICE_SW_LKUP_MAC_VLAN];
LIST_FOR_EACH_ENTRY_SAFE(v_list_itr, tmp, v_list, ice_fltr_list_entry,
list_entry) {
enum ice_sw_lkup_type l_type = v_list_itr->fltr_info.lkup_type;
if (l_type != ICE_SW_LKUP_MAC_VLAN)
return ICE_ERR_PARAM;
v_list_itr->status =
ice_remove_rule_internal(hw, recp_list,
v_list_itr);
if (v_list_itr->status)
return v_list_itr->status;
}
return 0;
}
/**
* ice_remove_mac_vlan - remove a MAC VLAN address based filter rule
* @hw: pointer to the hardware structure
* @mv_list: list of MAC VLAN and forwarding information
*/
int
ice_remove_mac_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *mv_list)
{
struct ice_sw_recipe *recp_list;
if (!mv_list || !hw)
return ICE_ERR_PARAM;
recp_list = &hw->switch_info->recp_list[ICE_SW_LKUP_MAC_VLAN];
return ice_remove_mac_vlan_rule(hw, mv_list, recp_list);
}
/**
* ice_vsi_uses_fltr - Determine if given VSI uses specified filter
* @fm_entry: filter entry to inspect
* @vsi_handle: VSI handle to compare with filter info
*/
static bool
ice_vsi_uses_fltr(struct ice_fltr_mgmt_list_entry *fm_entry, u16 vsi_handle)
{
return ((fm_entry->fltr_info.fltr_act == ICE_FWD_TO_VSI &&
fm_entry->fltr_info.vsi_handle == vsi_handle) ||
(fm_entry->fltr_info.fltr_act == ICE_FWD_TO_VSI_LIST &&
fm_entry->vsi_list_info &&
(ice_is_bit_set(fm_entry->vsi_list_info->vsi_map,
vsi_handle))));
}
/**
* ice_add_entry_to_vsi_fltr_list - Add copy of fltr_list_entry to remove list
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle to remove filters from
* @vsi_list_head: pointer to the list to add entry to
* @fi: pointer to fltr_info of filter entry to copy & add
*
* Helper function, used when creating a list of filters to remove from
* a specific VSI. The entry added to vsi_list_head is a COPY of the
* original filter entry, with the exception of fltr_info.fltr_act and
* fltr_info.fwd_id fields. These are set such that later logic can
* extract which VSI to remove the fltr from, and pass on that information.
*/
static int
ice_add_entry_to_vsi_fltr_list(struct ice_hw *hw, u16 vsi_handle,
struct LIST_HEAD_TYPE *vsi_list_head,
struct ice_fltr_info *fi)
{
struct ice_fltr_list_entry *tmp;
/* this memory is freed up in the caller function
* once filters for this VSI are removed
*/
tmp = (struct ice_fltr_list_entry *)ice_malloc(hw, sizeof(*tmp));
if (!tmp)
return ICE_ERR_NO_MEMORY;
tmp->fltr_info = *fi;
/* Overwrite these fields to indicate which VSI to remove filter from,
* so find and remove logic can extract the information from the
* list entries. Note that original entries will still have proper
* values.
*/
tmp->fltr_info.fltr_act = ICE_FWD_TO_VSI;
tmp->fltr_info.vsi_handle = vsi_handle;
tmp->fltr_info.fwd_id.hw_vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
LIST_ADD(&tmp->list_entry, vsi_list_head);
return 0;
}
/**
* ice_add_to_vsi_fltr_list - Add VSI filters to the list
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle to remove filters from
* @lkup_list_head: pointer to the list that has certain lookup type filters
* @vsi_list_head: pointer to the list pertaining to VSI with vsi_handle
*
* Locates all filters in lkup_list_head that are used by the given VSI,
* and adds COPIES of those entries to vsi_list_head (intended to be used
* to remove the listed filters).
* Note that this means all entries in vsi_list_head must be explicitly
* deallocated by the caller when done with list.
*/
static int
ice_add_to_vsi_fltr_list(struct ice_hw *hw, u16 vsi_handle,
struct LIST_HEAD_TYPE *lkup_list_head,
struct LIST_HEAD_TYPE *vsi_list_head)
{
struct ice_fltr_mgmt_list_entry *fm_entry;
int status = 0;
/* check to make sure VSI ID is valid and within boundary */
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
LIST_FOR_EACH_ENTRY(fm_entry, lkup_list_head,
ice_fltr_mgmt_list_entry, list_entry) {
if (!ice_vsi_uses_fltr(fm_entry, vsi_handle))
continue;
status = ice_add_entry_to_vsi_fltr_list(hw, vsi_handle,
vsi_list_head,
&fm_entry->fltr_info);
if (status)
return status;
}
return status;
}
/**
* ice_determine_promisc_mask
* @fi: filter info to parse
* @promisc_mask: pointer to mask to be filled in
*
* Helper function to determine which ICE_PROMISC_ mask corresponds
* to given filter into.
*/
static void ice_determine_promisc_mask(struct ice_fltr_info *fi,
ice_bitmap_t *promisc_mask)
{
u16 vid = fi->l_data.mac_vlan.vlan_id;
u8 *macaddr = fi->l_data.mac.mac_addr;
bool is_rx_lb_fltr = false;
bool is_tx_fltr = false;
ice_zero_bitmap(promisc_mask, ICE_PROMISC_MAX);
if (fi->flag == ICE_FLTR_TX)
is_tx_fltr = true;
if (fi->flag == ICE_FLTR_RX_LB)
is_rx_lb_fltr = true;
if (IS_BROADCAST_ETHER_ADDR(macaddr)) {
ice_set_bit(is_tx_fltr ? ICE_PROMISC_BCAST_TX
: ICE_PROMISC_BCAST_RX, promisc_mask);
} else if (IS_MULTICAST_ETHER_ADDR(macaddr)) {
ice_set_bit(is_tx_fltr ? ICE_PROMISC_MCAST_TX
: ICE_PROMISC_MCAST_RX, promisc_mask);
} else if (IS_UNICAST_ETHER_ADDR(macaddr)) {
if (is_tx_fltr)
ice_set_bit(ICE_PROMISC_UCAST_TX, promisc_mask);
else if (is_rx_lb_fltr)
ice_set_bit(ICE_PROMISC_UCAST_RX_LB, promisc_mask);
else
ice_set_bit(ICE_PROMISC_UCAST_RX, promisc_mask);
}
if (vid) {
ice_set_bit(is_tx_fltr ? ICE_PROMISC_VLAN_TX
: ICE_PROMISC_VLAN_RX, promisc_mask);
}
}
/**
* _ice_get_vsi_promisc - get promiscuous mode of given VSI
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle to retrieve info from
* @promisc_mask: pointer to mask to be filled in
* @vid: VLAN ID of promisc VLAN VSI
* @sw: pointer to switch info struct for which function add rule
* @lkup: switch rule filter lookup type
*/
static int
_ice_get_vsi_promisc(struct ice_hw *hw, u16 vsi_handle,
ice_bitmap_t *promisc_mask, u16 *vid,
struct ice_switch_info *sw, enum ice_sw_lkup_type lkup)
{
ice_declare_bitmap(fltr_promisc_mask, ICE_PROMISC_MAX);
struct ice_fltr_mgmt_list_entry *itr;
struct LIST_HEAD_TYPE *rule_head;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
if (!ice_is_vsi_valid(hw, vsi_handle) ||
(lkup != ICE_SW_LKUP_PROMISC && lkup != ICE_SW_LKUP_PROMISC_VLAN))
return ICE_ERR_PARAM;
*vid = 0;
rule_head = &sw->recp_list[lkup].filt_rules;
rule_lock = &sw->recp_list[lkup].filt_rule_lock;
ice_zero_bitmap(promisc_mask, ICE_PROMISC_MAX);
ice_acquire_lock(rule_lock);
LIST_FOR_EACH_ENTRY(itr, rule_head,
ice_fltr_mgmt_list_entry, list_entry) {
/* Continue if this filter doesn't apply to this VSI or the
* VSI ID is not in the VSI map for this filter
*/
if (!ice_vsi_uses_fltr(itr, vsi_handle))
continue;
ice_determine_promisc_mask(&itr->fltr_info, fltr_promisc_mask);
ice_or_bitmap(promisc_mask, promisc_mask, fltr_promisc_mask,
ICE_PROMISC_MAX);
}
ice_release_lock(rule_lock);
return 0;
}
/**
* ice_get_vsi_promisc - get promiscuous mode of given VSI
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle to retrieve info from
* @promisc_mask: pointer to mask to be filled in
* @vid: VLAN ID of promisc VLAN VSI
*/
int
ice_get_vsi_promisc(struct ice_hw *hw, u16 vsi_handle,
ice_bitmap_t *promisc_mask, u16 *vid)
{
if (!vid || !promisc_mask || !hw)
return ICE_ERR_PARAM;
return _ice_get_vsi_promisc(hw, vsi_handle, promisc_mask,
vid, hw->switch_info, ICE_SW_LKUP_PROMISC);
}
/**
* ice_get_vsi_vlan_promisc - get VLAN promiscuous mode of given VSI
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle to retrieve info from
* @promisc_mask: pointer to mask to be filled in
* @vid: VLAN ID of promisc VLAN VSI
*/
int
ice_get_vsi_vlan_promisc(struct ice_hw *hw, u16 vsi_handle,
ice_bitmap_t *promisc_mask, u16 *vid)
{
if (!hw || !promisc_mask || !vid)
return ICE_ERR_PARAM;
return _ice_get_vsi_promisc(hw, vsi_handle, promisc_mask,
vid, hw->switch_info,
ICE_SW_LKUP_PROMISC_VLAN);
}
/**
* ice_remove_promisc - Remove promisc based filter rules
* @hw: pointer to the hardware structure
* @recp_id: recipe ID for which the rule needs to removed
* @v_list: list of promisc entries
*/
static int
ice_remove_promisc(struct ice_hw *hw, u8 recp_id,
struct LIST_HEAD_TYPE *v_list)
{
struct ice_fltr_list_entry *v_list_itr, *tmp;
struct ice_sw_recipe *recp_list;
recp_list = &hw->switch_info->recp_list[recp_id];
LIST_FOR_EACH_ENTRY_SAFE(v_list_itr, tmp, v_list, ice_fltr_list_entry,
list_entry) {
v_list_itr->status =
ice_remove_rule_internal(hw, recp_list, v_list_itr);
if (v_list_itr->status)
return v_list_itr->status;
}
return 0;
}
/**
* _ice_clear_vsi_promisc - clear specified promiscuous mode(s)
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle to clear mode
* @promisc_mask: pointer to mask of promiscuous config bits to clear
* @vid: VLAN ID to clear VLAN promiscuous
* @sw: pointer to switch info struct for which function add rule
*/
static int
_ice_clear_vsi_promisc(struct ice_hw *hw, u16 vsi_handle,
ice_bitmap_t *promisc_mask, u16 vid,
struct ice_switch_info *sw)
{
ice_declare_bitmap(compl_promisc_mask, ICE_PROMISC_MAX);
ice_declare_bitmap(fltr_promisc_mask, ICE_PROMISC_MAX);
struct ice_fltr_list_entry *fm_entry, *tmp;
struct LIST_HEAD_TYPE remove_list_head;
struct ice_fltr_mgmt_list_entry *itr;
struct LIST_HEAD_TYPE *rule_head;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
int status = 0;
u8 recipe_id;
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
if (ice_is_bit_set(promisc_mask, ICE_PROMISC_VLAN_RX) &&
ice_is_bit_set(promisc_mask, ICE_PROMISC_VLAN_TX))
recipe_id = ICE_SW_LKUP_PROMISC_VLAN;
else
recipe_id = ICE_SW_LKUP_PROMISC;
rule_head = &sw->recp_list[recipe_id].filt_rules;
rule_lock = &sw->recp_list[recipe_id].filt_rule_lock;
INIT_LIST_HEAD(&remove_list_head);
ice_acquire_lock(rule_lock);
LIST_FOR_EACH_ENTRY(itr, rule_head,
ice_fltr_mgmt_list_entry, list_entry) {
struct ice_fltr_info *fltr_info;
ice_zero_bitmap(compl_promisc_mask, ICE_PROMISC_MAX);
if (!ice_vsi_uses_fltr(itr, vsi_handle))
continue;
fltr_info = &itr->fltr_info;
if (recipe_id == ICE_SW_LKUP_PROMISC_VLAN &&
vid != fltr_info->l_data.mac_vlan.vlan_id)
continue;
ice_determine_promisc_mask(fltr_info, fltr_promisc_mask);
ice_andnot_bitmap(compl_promisc_mask, fltr_promisc_mask,
promisc_mask, ICE_PROMISC_MAX);
/* Skip if filter is not completely specified by given mask */
if (ice_is_any_bit_set(compl_promisc_mask, ICE_PROMISC_MAX))
continue;
status = ice_add_entry_to_vsi_fltr_list(hw, vsi_handle,
&remove_list_head,
fltr_info);
if (status) {
ice_release_lock(rule_lock);
goto free_fltr_list;
}
}
ice_release_lock(rule_lock);
status = ice_remove_promisc(hw, recipe_id, &remove_list_head);
free_fltr_list:
LIST_FOR_EACH_ENTRY_SAFE(fm_entry, tmp, &remove_list_head,
ice_fltr_list_entry, list_entry) {
LIST_DEL(&fm_entry->list_entry);
ice_free(hw, fm_entry);
}
return status;
}
/**
* ice_clear_vsi_promisc - clear specified promiscuous mode(s) for given VSI
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle to clear mode
* @promisc_mask: pointer to mask of promiscuous config bits to clear
* @vid: VLAN ID to clear VLAN promiscuous
*/
int
ice_clear_vsi_promisc(struct ice_hw *hw, u16 vsi_handle,
ice_bitmap_t *promisc_mask, u16 vid)
{
if (!hw || !promisc_mask)
return ICE_ERR_PARAM;
return _ice_clear_vsi_promisc(hw, vsi_handle, promisc_mask,
vid, hw->switch_info);
}
/**
* _ice_set_vsi_promisc - set given VSI to given promiscuous mode(s)
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle to configure
* @promisc_mask: pointer to mask of promiscuous config bits
* @vid: VLAN ID to set VLAN promiscuous
* @lport: logical port number to configure promisc mode
* @sw: pointer to switch info struct for which function add rule
*/
static int
_ice_set_vsi_promisc(struct ice_hw *hw, u16 vsi_handle,
ice_bitmap_t *promisc_mask, u16 vid, u8 lport,
struct ice_switch_info *sw)
{
enum { UCAST_FLTR = 1, MCAST_FLTR, BCAST_FLTR };
ice_declare_bitmap(p_mask, ICE_PROMISC_MAX);
struct ice_fltr_list_entry f_list_entry;
bool is_tx_fltr, is_rx_lb_fltr;
struct ice_fltr_info new_fltr;
int status = 0;
u16 hw_vsi_id;
int pkt_type;
u8 recipe_id;
ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
hw_vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
ice_memset(&new_fltr, 0, sizeof(new_fltr), ICE_NONDMA_MEM);
/* Do not modify original bitmap */
ice_cp_bitmap(p_mask, promisc_mask, ICE_PROMISC_MAX);
if (ice_is_bit_set(p_mask, ICE_PROMISC_VLAN_RX) &&
ice_is_bit_set(p_mask, ICE_PROMISC_VLAN_TX)) {
new_fltr.lkup_type = ICE_SW_LKUP_PROMISC_VLAN;
new_fltr.l_data.mac_vlan.vlan_id = vid;
recipe_id = ICE_SW_LKUP_PROMISC_VLAN;
} else {
new_fltr.lkup_type = ICE_SW_LKUP_PROMISC;
recipe_id = ICE_SW_LKUP_PROMISC;
}
/* Separate filters must be set for each direction/packet type
* combination, so we will loop over the mask value, store the
* individual type, and clear it out in the input mask as it
* is found.
*/
while (ice_is_any_bit_set(p_mask, ICE_PROMISC_MAX)) {
struct ice_sw_recipe *recp_list;
u8 *mac_addr;
pkt_type = 0;
is_tx_fltr = false;
is_rx_lb_fltr = false;
if (ice_test_and_clear_bit(ICE_PROMISC_UCAST_RX,
p_mask)) {
pkt_type = UCAST_FLTR;
} else if (ice_test_and_clear_bit(ICE_PROMISC_UCAST_TX,
p_mask)) {
pkt_type = UCAST_FLTR;
is_tx_fltr = true;
} else if (ice_test_and_clear_bit(ICE_PROMISC_MCAST_RX,
p_mask)) {
pkt_type = MCAST_FLTR;
} else if (ice_test_and_clear_bit(ICE_PROMISC_MCAST_TX,
p_mask)) {
pkt_type = MCAST_FLTR;
is_tx_fltr = true;
} else if (ice_test_and_clear_bit(ICE_PROMISC_BCAST_RX,
p_mask)) {
pkt_type = BCAST_FLTR;
} else if (ice_test_and_clear_bit(ICE_PROMISC_BCAST_TX,
p_mask)) {
pkt_type = BCAST_FLTR;
is_tx_fltr = true;
} else if (ice_test_and_clear_bit(ICE_PROMISC_UCAST_RX_LB,
p_mask)) {
pkt_type = UCAST_FLTR;
is_rx_lb_fltr = true;
}
/* Check for VLAN promiscuous flag */
if (ice_is_bit_set(p_mask, ICE_PROMISC_VLAN_RX)) {
ice_clear_bit(ICE_PROMISC_VLAN_RX, p_mask);
} else if (ice_test_and_clear_bit(ICE_PROMISC_VLAN_TX,
p_mask)) {
is_tx_fltr = true;
}
/* Set filter DA based on packet type */
mac_addr = new_fltr.l_data.mac.mac_addr;
if (pkt_type == BCAST_FLTR) {
ice_memset(mac_addr, 0xff, ETH_ALEN, ICE_NONDMA_MEM);
} else if (pkt_type == MCAST_FLTR ||
pkt_type == UCAST_FLTR) {
/* Use the dummy ether header DA */
ice_memcpy(mac_addr, dummy_eth_header, ETH_ALEN,
ICE_NONDMA_TO_NONDMA);
if (pkt_type == MCAST_FLTR)
mac_addr[0] |= 0x1; /* Set multicast bit */
}
/* Need to reset this to zero for all iterations */
new_fltr.flag = 0;
if (is_tx_fltr) {
new_fltr.flag |= ICE_FLTR_TX;
new_fltr.src = hw_vsi_id;
} else if (is_rx_lb_fltr) {
new_fltr.flag |= ICE_FLTR_RX_LB;
new_fltr.src = hw_vsi_id;
} else {
new_fltr.flag |= ICE_FLTR_RX;
new_fltr.src = lport;
}
new_fltr.fltr_act = ICE_FWD_TO_VSI;
new_fltr.vsi_handle = vsi_handle;
new_fltr.fwd_id.hw_vsi_id = hw_vsi_id;
f_list_entry.fltr_info = new_fltr;
recp_list = &sw->recp_list[recipe_id];
status = ice_add_rule_internal(hw, recp_list, lport,
&f_list_entry);
if (status)
goto set_promisc_exit;
}
set_promisc_exit:
return status;
}
/**
* ice_set_vsi_promisc - set given VSI to given promiscuous mode(s)
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle to configure
* @promisc_mask: pointer to mask of promiscuous config bits
* @vid: VLAN ID to set VLAN promiscuous
*/
int
ice_set_vsi_promisc(struct ice_hw *hw, u16 vsi_handle,
ice_bitmap_t *promisc_mask, u16 vid)
{
if (!hw || !promisc_mask)
return ICE_ERR_PARAM;
return _ice_set_vsi_promisc(hw, vsi_handle, promisc_mask, vid,
hw->port_info->lport,
hw->switch_info);
}
/**
* _ice_set_vlan_vsi_promisc
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle to configure
* @promisc_mask: pointer to mask of promiscuous config bits
* @rm_vlan_promisc: Clear VLANs VSI promisc mode
* @lport: logical port number to configure promisc mode
* @sw: pointer to switch info struct for which function add rule
*
* Configure VSI with all associated VLANs to given promiscuous mode(s)
*/
static int
_ice_set_vlan_vsi_promisc(struct ice_hw *hw, u16 vsi_handle,
ice_bitmap_t *promisc_mask, bool rm_vlan_promisc,
u8 lport, struct ice_switch_info *sw)
{
struct ice_fltr_list_entry *list_itr, *tmp;
struct LIST_HEAD_TYPE vsi_list_head;
struct LIST_HEAD_TYPE *vlan_head;
struct ice_lock *vlan_lock; /* Lock to protect filter rule list */
int status;
u16 vlan_id;
INIT_LIST_HEAD(&vsi_list_head);
vlan_lock = &sw->recp_list[ICE_SW_LKUP_VLAN].filt_rule_lock;
vlan_head = &sw->recp_list[ICE_SW_LKUP_VLAN].filt_rules;
ice_acquire_lock(vlan_lock);
status = ice_add_to_vsi_fltr_list(hw, vsi_handle, vlan_head,
&vsi_list_head);
ice_release_lock(vlan_lock);
if (status)
goto free_fltr_list;
LIST_FOR_EACH_ENTRY(list_itr, &vsi_list_head, ice_fltr_list_entry,
list_entry) {
/* Avoid enabling or disabling vlan zero twice when in double
* vlan mode
*/
if (ice_is_dvm_ena(hw) &&
list_itr->fltr_info.l_data.vlan.tpid == 0)
continue;
vlan_id = list_itr->fltr_info.l_data.vlan.vlan_id;
if (rm_vlan_promisc)
status = _ice_clear_vsi_promisc(hw, vsi_handle,
promisc_mask,
vlan_id, sw);
else
status = _ice_set_vsi_promisc(hw, vsi_handle,
promisc_mask, vlan_id,
lport, sw);
if (status && status != ICE_ERR_ALREADY_EXISTS)
break;
}
free_fltr_list:
LIST_FOR_EACH_ENTRY_SAFE(list_itr, tmp, &vsi_list_head,
ice_fltr_list_entry, list_entry) {
LIST_DEL(&list_itr->list_entry);
ice_free(hw, list_itr);
}
return status;
}
/**
* ice_set_vlan_vsi_promisc
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle to configure
* @promisc_mask: mask of promiscuous config bits
* @rm_vlan_promisc: Clear VLANs VSI promisc mode
*
* Configure VSI with all associated VLANs to given promiscuous mode(s)
*/
int
ice_set_vlan_vsi_promisc(struct ice_hw *hw, u16 vsi_handle,
ice_bitmap_t *promisc_mask, bool rm_vlan_promisc)
{
if (!hw || !promisc_mask)
return ICE_ERR_PARAM;
return _ice_set_vlan_vsi_promisc(hw, vsi_handle, promisc_mask,
rm_vlan_promisc, hw->port_info->lport,
hw->switch_info);
}
/**
* ice_remove_vsi_lkup_fltr - Remove lookup type filters for a VSI
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle to remove filters from
* @recp_list: recipe list from which function remove fltr
* @lkup: switch rule filter lookup type
*/
static void
ice_remove_vsi_lkup_fltr(struct ice_hw *hw, u16 vsi_handle,
struct ice_sw_recipe *recp_list,
enum ice_sw_lkup_type lkup)
{
struct ice_fltr_list_entry *fm_entry;
struct LIST_HEAD_TYPE remove_list_head;
struct LIST_HEAD_TYPE *rule_head;
struct ice_fltr_list_entry *tmp;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
int status;
INIT_LIST_HEAD(&remove_list_head);
rule_lock = &recp_list[lkup].filt_rule_lock;
rule_head = &recp_list[lkup].filt_rules;
ice_acquire_lock(rule_lock);
status = ice_add_to_vsi_fltr_list(hw, vsi_handle, rule_head,
&remove_list_head);
ice_release_lock(rule_lock);
if (status)
goto free_fltr_list;
switch (lkup) {
case ICE_SW_LKUP_MAC:
ice_remove_mac_rule(hw, &remove_list_head, &recp_list[lkup]);
break;
case ICE_SW_LKUP_VLAN:
ice_remove_vlan_rule(hw, &remove_list_head, &recp_list[lkup]);
break;
case ICE_SW_LKUP_PROMISC:
case ICE_SW_LKUP_PROMISC_VLAN:
ice_remove_promisc(hw, (u8)lkup, &remove_list_head);
break;
case ICE_SW_LKUP_MAC_VLAN:
ice_remove_mac_vlan(hw, &remove_list_head);
break;
case ICE_SW_LKUP_ETHERTYPE:
case ICE_SW_LKUP_ETHERTYPE_MAC:
ice_remove_eth_mac(hw, &remove_list_head);
break;
case ICE_SW_LKUP_DFLT:
ice_debug(hw, ICE_DBG_SW, "Remove filters for this lookup type hasn't been implemented yet\n");
break;
case ICE_SW_LKUP_LAST:
ice_debug(hw, ICE_DBG_SW, "Unsupported lookup type\n");
break;
}
free_fltr_list:
LIST_FOR_EACH_ENTRY_SAFE(fm_entry, tmp, &remove_list_head,
ice_fltr_list_entry, list_entry) {
LIST_DEL(&fm_entry->list_entry);
ice_free(hw, fm_entry);
}
}
/**
* ice_remove_vsi_fltr_rule - Remove all filters for a VSI
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle to remove filters from
* @sw: pointer to switch info struct
*/
static void
ice_remove_vsi_fltr_rule(struct ice_hw *hw, u16 vsi_handle,
struct ice_switch_info *sw)
{
ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
ice_remove_vsi_lkup_fltr(hw, vsi_handle,
sw->recp_list, ICE_SW_LKUP_MAC);
ice_remove_vsi_lkup_fltr(hw, vsi_handle,
sw->recp_list, ICE_SW_LKUP_MAC_VLAN);
ice_remove_vsi_lkup_fltr(hw, vsi_handle,
sw->recp_list, ICE_SW_LKUP_PROMISC);
ice_remove_vsi_lkup_fltr(hw, vsi_handle,
sw->recp_list, ICE_SW_LKUP_VLAN);
ice_remove_vsi_lkup_fltr(hw, vsi_handle,
sw->recp_list, ICE_SW_LKUP_DFLT);
ice_remove_vsi_lkup_fltr(hw, vsi_handle,
sw->recp_list, ICE_SW_LKUP_ETHERTYPE);
ice_remove_vsi_lkup_fltr(hw, vsi_handle,
sw->recp_list, ICE_SW_LKUP_ETHERTYPE_MAC);
ice_remove_vsi_lkup_fltr(hw, vsi_handle,
sw->recp_list, ICE_SW_LKUP_PROMISC_VLAN);
}
/**
* ice_remove_vsi_fltr - Remove all filters for a VSI
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle to remove filters from
*/
void ice_remove_vsi_fltr(struct ice_hw *hw, u16 vsi_handle)
{
ice_remove_vsi_fltr_rule(hw, vsi_handle, hw->switch_info);
}
/**
* ice_alloc_res_cntr - allocating resource counter
* @hw: pointer to the hardware structure
* @type: type of resource
* @alloc_shared: if set it is shared else dedicated
* @num_items: number of entries requested for FD resource type
* @counter_id: counter index returned by AQ call
*/
int
ice_alloc_res_cntr(struct ice_hw *hw, u8 type, u8 alloc_shared, u16 num_items,
u16 *counter_id)
{
struct ice_aqc_alloc_free_res_elem *buf;
u16 buf_len;
int status;
/* Allocate resource */
buf_len = ice_struct_size(buf, elem, 1);
buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
if (!buf)
return ICE_ERR_NO_MEMORY;
buf->num_elems = CPU_TO_LE16(num_items);
buf->res_type = CPU_TO_LE16(((type << ICE_AQC_RES_TYPE_S) &
ICE_AQC_RES_TYPE_M) | alloc_shared);
status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
ice_aqc_opc_alloc_res, NULL);
if (status)
goto exit;
*counter_id = LE16_TO_CPU(buf->elem[0].e.sw_resp);
exit:
ice_free(hw, buf);
return status;
}
/**
* ice_free_res_cntr - free resource counter
* @hw: pointer to the hardware structure
* @type: type of resource
* @alloc_shared: if set it is shared else dedicated
* @num_items: number of entries to be freed for FD resource type
* @counter_id: counter ID resource which needs to be freed
*/
int
ice_free_res_cntr(struct ice_hw *hw, u8 type, u8 alloc_shared, u16 num_items,
u16 counter_id)
{
struct ice_aqc_alloc_free_res_elem *buf;
u16 buf_len;
int status;
/* Free resource */
buf_len = ice_struct_size(buf, elem, 1);
buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
if (!buf)
return ICE_ERR_NO_MEMORY;
buf->num_elems = CPU_TO_LE16(num_items);
buf->res_type = CPU_TO_LE16(((type << ICE_AQC_RES_TYPE_S) &
ICE_AQC_RES_TYPE_M) | alloc_shared);
buf->elem[0].e.sw_resp = CPU_TO_LE16(counter_id);
status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
ice_aqc_opc_free_res, NULL);
if (status)
ice_debug(hw, ICE_DBG_SW, "counter resource could not be freed\n");
ice_free(hw, buf);
return status;
}
/**
* ice_alloc_vlan_res_counter - obtain counter resource for VLAN type
* @hw: pointer to the hardware structure
* @counter_id: returns counter index
*/
int ice_alloc_vlan_res_counter(struct ice_hw *hw, u16 *counter_id)
{
return ice_alloc_res_cntr(hw, ICE_AQC_RES_TYPE_VLAN_COUNTER,
ICE_AQC_RES_TYPE_FLAG_DEDICATED, 1,
counter_id);
}
/**
* ice_free_vlan_res_counter - Free counter resource for VLAN type
* @hw: pointer to the hardware structure
* @counter_id: counter index to be freed
*/
int ice_free_vlan_res_counter(struct ice_hw *hw, u16 counter_id)
{
return ice_free_res_cntr(hw, ICE_AQC_RES_TYPE_VLAN_COUNTER,
ICE_AQC_RES_TYPE_FLAG_DEDICATED, 1,
counter_id);
}
/**
* ice_add_mac_with_sw_marker - add filter with sw marker
* @hw: pointer to the hardware structure
* @f_info: filter info structure containing the MAC filter information
* @sw_marker: sw marker to tag the Rx descriptor with
*/
int
ice_add_mac_with_sw_marker(struct ice_hw *hw, struct ice_fltr_info *f_info,
u16 sw_marker)
{
struct ice_fltr_mgmt_list_entry *m_entry;
struct ice_fltr_list_entry fl_info;
struct ice_sw_recipe *recp_list;
struct LIST_HEAD_TYPE l_head;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
bool entry_exists;
u16 lg_act_id;
int ret;
if (f_info->fltr_act != ICE_FWD_TO_VSI)
return ICE_ERR_PARAM;
if (f_info->lkup_type != ICE_SW_LKUP_MAC)
return ICE_ERR_PARAM;
if (sw_marker == ICE_INVAL_SW_MARKER_ID)
return ICE_ERR_PARAM;
if (!ice_is_vsi_valid(hw, f_info->vsi_handle))
return ICE_ERR_PARAM;
f_info->fwd_id.hw_vsi_id = ice_get_hw_vsi_num(hw, f_info->vsi_handle);
/* Add filter if it doesn't exist so then the adding of large
* action always results in update
*/
INIT_LIST_HEAD(&l_head);
fl_info.fltr_info = *f_info;
LIST_ADD(&fl_info.list_entry, &l_head);
entry_exists = false;
ret = ice_add_mac_rule(hw, &l_head, hw->switch_info,
hw->port_info->lport);
if (ret == ICE_ERR_ALREADY_EXISTS)
entry_exists = true;
else if (ret)
return ret;
recp_list = &hw->switch_info->recp_list[ICE_SW_LKUP_MAC];
rule_lock = &recp_list->filt_rule_lock;
ice_acquire_lock(rule_lock);
/* Get the book keeping entry for the filter */
m_entry = ice_find_rule_entry(&recp_list->filt_rules, f_info);
if (!m_entry)
goto exit_error;
/* If counter action was enabled for this rule then don't enable
* sw marker large action
*/
if (m_entry->counter_index != ICE_INVAL_COUNTER_ID) {
ret = ICE_ERR_PARAM;
goto exit_error;
}
/* if same marker was added before */
if (m_entry->sw_marker_id == sw_marker) {
ret = ICE_ERR_ALREADY_EXISTS;
goto exit_error;
}
/* Allocate a hardware table entry to hold large act. Three actions
* for marker based large action
*/
ret = ice_alloc_res_lg_act(hw, &lg_act_id, 3);
if (ret)
goto exit_error;
if (lg_act_id == ICE_INVAL_LG_ACT_INDEX)
goto exit_error;
/* Update the switch rule to add the marker action */
ret = ice_add_marker_act(hw, m_entry, sw_marker, lg_act_id);
if (!ret) {
ice_release_lock(rule_lock);
return ret;
}
exit_error:
ice_release_lock(rule_lock);
/* only remove entry if it did not exist previously */
if (!entry_exists)
ret = ice_remove_mac(hw, &l_head);
return ret;
}
/**
* ice_add_mac_with_counter - add filter with counter enabled
* @hw: pointer to the hardware structure
* @f_info: pointer to filter info structure containing the MAC filter
* information
*/
int
ice_add_mac_with_counter(struct ice_hw *hw, struct ice_fltr_info *f_info)
{
struct ice_fltr_mgmt_list_entry *m_entry;
struct ice_fltr_list_entry fl_info;
struct ice_sw_recipe *recp_list;
struct LIST_HEAD_TYPE l_head;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
bool entry_exist;
u16 counter_id;
u16 lg_act_id;
int ret;
if (f_info->fltr_act != ICE_FWD_TO_VSI)
return ICE_ERR_PARAM;
if (f_info->lkup_type != ICE_SW_LKUP_MAC)
return ICE_ERR_PARAM;
if (!ice_is_vsi_valid(hw, f_info->vsi_handle))
return ICE_ERR_PARAM;
f_info->fwd_id.hw_vsi_id = ice_get_hw_vsi_num(hw, f_info->vsi_handle);
recp_list = &hw->switch_info->recp_list[ICE_SW_LKUP_MAC];
entry_exist = false;
rule_lock = &recp_list->filt_rule_lock;
/* Add filter if it doesn't exist so then the adding of large
* action always results in update
*/
INIT_LIST_HEAD(&l_head);
fl_info.fltr_info = *f_info;
LIST_ADD(&fl_info.list_entry, &l_head);
ret = ice_add_mac_rule(hw, &l_head, hw->switch_info,
hw->port_info->lport);
if (ret == ICE_ERR_ALREADY_EXISTS)
entry_exist = true;
else if (ret)
return ret;
ice_acquire_lock(rule_lock);
m_entry = ice_find_rule_entry(&recp_list->filt_rules, f_info);
if (!m_entry) {
ret = ICE_ERR_BAD_PTR;
goto exit_error;
}
/* Don't enable counter for a filter for which sw marker was enabled */
if (m_entry->sw_marker_id != ICE_INVAL_SW_MARKER_ID) {
ret = ICE_ERR_PARAM;
goto exit_error;
}
/* If a counter was already enabled then don't need to add again */
if (m_entry->counter_index != ICE_INVAL_COUNTER_ID) {
ret = ICE_ERR_ALREADY_EXISTS;
goto exit_error;
}
/* Allocate a hardware table entry to VLAN counter */
ret = ice_alloc_vlan_res_counter(hw, &counter_id);
if (ret)
goto exit_error;
/* Allocate a hardware table entry to hold large act. Two actions for
* counter based large action
*/
ret = ice_alloc_res_lg_act(hw, &lg_act_id, 2);
if (ret)
goto exit_error;
if (lg_act_id == ICE_INVAL_LG_ACT_INDEX)
goto exit_error;
/* Update the switch rule to add the counter action */
ret = ice_add_counter_act(hw, m_entry, counter_id, lg_act_id);
if (!ret) {
ice_release_lock(rule_lock);
return ret;
}
exit_error:
ice_release_lock(rule_lock);
/* only remove entry if it did not exist previously */
if (!entry_exist)
ret = ice_remove_mac(hw, &l_head);
return ret;
}
/* This is mapping table entry that maps every word within a given protocol
* structure to the real byte offset as per the specification of that
* protocol header.
* for example dst address is 3 words in ethertype header and corresponding
* bytes are 0, 2, 3 in the actual packet header and src address is at 4, 6, 8
* IMPORTANT: Every structure part of "ice_prot_hdr" union should have a
* matching entry describing its field. This needs to be updated if new
* structure is added to that union.
*/
static const struct ice_prot_ext_tbl_entry ice_prot_ext[ICE_PROTOCOL_LAST] = {
{ ICE_MAC_OFOS, { 0, 2, 4, 6, 8, 10, 12 } },
{ ICE_MAC_IL, { 0, 2, 4, 6, 8, 10, 12 } },
{ ICE_ETYPE_OL, { 0 } },
{ ICE_ETYPE_IL, { 0 } },
{ ICE_VLAN_OFOS, { 2, 0 } },
{ ICE_IPV4_OFOS, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18 } },
{ ICE_IPV4_IL, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18 } },
{ ICE_IPV6_OFOS, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24,
26, 28, 30, 32, 34, 36, 38 } },
{ ICE_IPV6_IL, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24,
26, 28, 30, 32, 34, 36, 38 } },
{ ICE_TCP_IL, { 0, 2 } },
{ ICE_UDP_OF, { 0, 2 } },
{ ICE_UDP_ILOS, { 0, 2 } },
{ ICE_SCTP_IL, { 0, 2 } },
{ ICE_VXLAN, { 8, 10, 12, 14 } },
{ ICE_GENEVE, { 8, 10, 12, 14 } },
{ ICE_VXLAN_GPE, { 8, 10, 12, 14 } },
{ ICE_NVGRE, { 0, 2, 4, 6 } },
{ ICE_GTP, { 8, 10, 12, 14, 16, 18, 20, 22 } },
{ ICE_GTP_NO_PAY, { 8, 10, 12, 14 } },
{ ICE_PPPOE, { 0, 2, 4, 6 } },
{ ICE_PFCP, { 8, 10, 12, 14, 16, 18, 20, 22 } },
{ ICE_L2TPV3, { 0, 2, 4, 6, 8, 10 } },
{ ICE_ESP, { 0, 2, 4, 6 } },
{ ICE_AH, { 0, 2, 4, 6, 8, 10 } },
{ ICE_NAT_T, { 8, 10, 12, 14 } },
{ ICE_VLAN_EX, { 2, 0 } },
{ ICE_VLAN_IN, { 2, 0 } },
};
/* The following table describes preferred grouping of recipes.
* If a recipe that needs to be programmed is a superset or matches one of the
* following combinations, then the recipe needs to be chained as per the
* following policy.
*/
static struct ice_protocol_entry ice_prot_id_tbl[ICE_PROTOCOL_LAST] = {
{ ICE_MAC_OFOS, ICE_MAC_OFOS_HW },
{ ICE_MAC_IL, ICE_MAC_IL_HW },
{ ICE_ETYPE_OL, ICE_ETYPE_OL_HW },
{ ICE_ETYPE_IL, ICE_ETYPE_IL_HW },
{ ICE_VLAN_OFOS, ICE_VLAN_OL_HW },
{ ICE_IPV4_OFOS, ICE_IPV4_OFOS_HW },
{ ICE_IPV4_IL, ICE_IPV4_IL_HW },
{ ICE_IPV6_OFOS, ICE_IPV6_OFOS_HW },
{ ICE_IPV6_IL, ICE_IPV6_IL_HW },
{ ICE_TCP_IL, ICE_TCP_IL_HW },
{ ICE_UDP_OF, ICE_UDP_OF_HW },
{ ICE_UDP_ILOS, ICE_UDP_ILOS_HW },
{ ICE_SCTP_IL, ICE_SCTP_IL_HW },
{ ICE_VXLAN, ICE_UDP_OF_HW },
{ ICE_GENEVE, ICE_UDP_OF_HW },
{ ICE_VXLAN_GPE, ICE_UDP_OF_HW },
{ ICE_NVGRE, ICE_GRE_OF_HW },
{ ICE_GTP, ICE_UDP_OF_HW },
{ ICE_GTP_NO_PAY, ICE_UDP_ILOS_HW },
{ ICE_PPPOE, ICE_PPPOE_HW },
{ ICE_PFCP, ICE_UDP_ILOS_HW },
{ ICE_L2TPV3, ICE_L2TPV3_HW },
{ ICE_ESP, ICE_ESP_HW },
{ ICE_AH, ICE_AH_HW },
{ ICE_NAT_T, ICE_UDP_ILOS_HW },
{ ICE_VLAN_EX, ICE_VLAN_OF_HW },
{ ICE_VLAN_IN, ICE_VLAN_OL_HW },
{ ICE_FLG_DIR, ICE_META_DATA_ID_HW},
};
/*
* ice_find_recp - find a recipe
* @hw: pointer to the hardware structure
* @lkup_exts: extension sequence to match
*
* Returns index of matching recipe, or ICE_MAX_NUM_RECIPES if not found.
*/
static u16 ice_find_recp(struct ice_hw *hw, struct ice_prot_lkup_ext *lkup_exts,
enum ice_sw_tunnel_type tun_type, u32 priority)
{
bool refresh_required = true;
struct ice_sw_recipe *recp;
u8 i;
/* Walk through existing recipes to find a match */
recp = hw->switch_info->recp_list;
for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
/* If recipe was not created for this ID, in SW bookkeeping,
* check if FW has an entry for this recipe. If the FW has an
* entry update it in our SW bookkeeping and continue with the
* matching.
*/
if (!recp[i].recp_created)
if (ice_get_recp_frm_fw(hw,
hw->switch_info->recp_list, i,
&refresh_required))
continue;
/* Skip inverse action recipes */
if (recp[i].root_buf && recp[i].root_buf->content.act_ctrl &
ICE_AQ_RECIPE_ACT_INV_ACT)
continue;
/* if number of words we are looking for match */
if (lkup_exts->n_val_words == recp[i].lkup_exts.n_val_words) {
struct ice_fv_word *ar = recp[i].lkup_exts.fv_words;
struct ice_fv_word *be = lkup_exts->fv_words;
u16 *cr = recp[i].lkup_exts.field_mask;
u16 *de = lkup_exts->field_mask;
bool found = true;
u8 pe, qr;
/* ar, cr, and qr are related to the recipe words, while
* be, de, and pe are related to the lookup words
*/
for (pe = 0; pe < lkup_exts->n_val_words; pe++) {
for (qr = 0; qr < recp[i].lkup_exts.n_val_words;
qr++) {
if (ar[qr].off == be[pe].off &&
ar[qr].prot_id == be[pe].prot_id &&
cr[qr] == de[pe])
/* Found the "pe"th word in the
* given recipe
*/
break;
}
/* After walking through all the words in the
* "i"th recipe if "p"th word was not found then
* this recipe is not what we are looking for.
* So break out from this loop and try the next
* recipe
*/
if (qr >= recp[i].lkup_exts.n_val_words) {
found = false;
break;
}
}
/* If for "i"th recipe the found was never set to false
* then it means we found our match
*/
if (found && priority == recp[i].priority) {
if (tun_type == recp[i].tun_type ||
(recp[i].tun_type == ICE_SW_TUN_UDP &&
(tun_type == ICE_SW_TUN_VXLAN_GPE ||
tun_type == ICE_SW_TUN_VXLAN ||
tun_type == ICE_SW_TUN_GENEVE ||
tun_type == ICE_SW_TUN_GENEVE_VLAN ||
tun_type == ICE_SW_TUN_VXLAN_VLAN)))
return i; /* Return the recipe ID */
}
}
}
return ICE_MAX_NUM_RECIPES;
}
/**
* ice_change_proto_id_to_dvm - change proto id in prot_id_tbl
*
* As protocol id for outer vlan is different in dvm and svm, if dvm is
* supported protocol array record for outer vlan has to be modified to
* reflect the value proper for DVM.
*/
void ice_change_proto_id_to_dvm(void)
{
u8 i;
for (i = 0; i < ARRAY_SIZE(ice_prot_id_tbl); i++)
if (ice_prot_id_tbl[i].type == ICE_VLAN_OFOS &&
ice_prot_id_tbl[i].protocol_id != ICE_VLAN_OF_HW)
ice_prot_id_tbl[i].protocol_id = ICE_VLAN_OF_HW;
}
/**
* ice_prot_type_to_id - get protocol ID from protocol type
* @type: protocol type
* @id: pointer to variable that will receive the ID
*
* Returns true if found, false otherwise
*/
static bool ice_prot_type_to_id(enum ice_protocol_type type, u8 *id)
{
u8 i;
for (i = 0; i < ARRAY_SIZE(ice_prot_id_tbl); i++)
if (ice_prot_id_tbl[i].type == type) {
*id = ice_prot_id_tbl[i].protocol_id;
return true;
}
return false;
}
/**
* ice_fill_valid_words - count valid words
* @rule: advanced rule with lookup information
* @lkup_exts: byte offset extractions of the words that are valid
*
* calculate valid words in a lookup rule using mask value
*/
static u8
ice_fill_valid_words(struct ice_adv_lkup_elem *rule,
struct ice_prot_lkup_ext *lkup_exts)
{
u8 j, word, prot_id, ret_val;
if (!ice_prot_type_to_id(rule->type, &prot_id))
return 0;
word = lkup_exts->n_val_words;
for (j = 0; j < sizeof(rule->m_u) / sizeof(u16); j++)
if (((u16 *)&rule->m_u)[j] &&
(size_t)rule->type < ARRAY_SIZE(ice_prot_ext)) {
/* No more space to accommodate */
if (word >= ICE_MAX_CHAIN_WORDS)
return 0;
lkup_exts->fv_words[word].off =
ice_prot_ext[rule->type].offs[j];
lkup_exts->fv_words[word].prot_id =
ice_prot_id_tbl[rule->type].protocol_id;
lkup_exts->field_mask[word] =
BE16_TO_CPU(((_FORCE_ __be16 *)&rule->m_u)[j]);
word++;
}
ret_val = word - lkup_exts->n_val_words;
lkup_exts->n_val_words = word;
return ret_val;
}
/**
* ice_create_first_fit_recp_def - Create a recipe grouping
* @hw: pointer to the hardware structure
* @lkup_exts: an array of protocol header extractions
* @rg_list: pointer to a list that stores new recipe groups
* @recp_cnt: pointer to a variable that stores returned number of recipe groups
*
* Using first fit algorithm, take all the words that are still not done
* and start grouping them in 4-word groups. Each group makes up one
* recipe.
*/
static int
ice_create_first_fit_recp_def(struct ice_hw *hw,
struct ice_prot_lkup_ext *lkup_exts,
struct LIST_HEAD_TYPE *rg_list,
u8 *recp_cnt)
{
struct ice_pref_recipe_group *grp = NULL;
u8 j;
*recp_cnt = 0;
if (!lkup_exts->n_val_words) {
struct ice_recp_grp_entry *entry;
entry = (struct ice_recp_grp_entry *)
ice_malloc(hw, sizeof(*entry));
if (!entry)
return ICE_ERR_NO_MEMORY;
LIST_ADD(&entry->l_entry, rg_list);
grp = &entry->r_group;
(*recp_cnt)++;
grp->n_val_pairs = 0;
}
/* Walk through every word in the rule to check if it is not done. If so
* then this word needs to be part of a new recipe.
*/
for (j = 0; j < lkup_exts->n_val_words; j++)
if (!ice_is_bit_set(lkup_exts->done, j)) {
if (!grp ||
grp->n_val_pairs == ICE_NUM_WORDS_RECIPE) {
struct ice_recp_grp_entry *entry;
entry = (struct ice_recp_grp_entry *)
ice_malloc(hw, sizeof(*entry));
if (!entry)
return ICE_ERR_NO_MEMORY;
LIST_ADD(&entry->l_entry, rg_list);
grp = &entry->r_group;
(*recp_cnt)++;
}
if (grp->n_val_pairs < ICE_NUM_WORDS_RECIPE) {
grp->pairs[grp->n_val_pairs].prot_id =
lkup_exts->fv_words[j].prot_id;
grp->pairs[grp->n_val_pairs].off =
lkup_exts->fv_words[j].off;
grp->mask[grp->n_val_pairs] = lkup_exts->field_mask[j];
grp->n_val_pairs++;
}
}
return 0;
}
/**
* ice_fill_fv_word_index - fill in the field vector indices for a recipe group
* @hw: pointer to the hardware structure
* @fv_list: field vector with the extraction sequence information
* @rg_list: recipe groupings with protocol-offset pairs
*
* Helper function to fill in the field vector indices for protocol-offset
* pairs. These indexes are then ultimately programmed into a recipe.
*/
static int
ice_fill_fv_word_index(struct ice_hw *hw, struct LIST_HEAD_TYPE *fv_list,
struct LIST_HEAD_TYPE *rg_list)
{
struct ice_sw_fv_list_entry *fv;
struct ice_recp_grp_entry *rg;
struct ice_fv_word *fv_ext;
if (LIST_EMPTY(fv_list))
return 0;
fv = LIST_FIRST_ENTRY(fv_list, struct ice_sw_fv_list_entry, list_entry);
fv_ext = fv->fv_ptr->ew;
LIST_FOR_EACH_ENTRY(rg, rg_list, ice_recp_grp_entry, l_entry) {
u8 i;
for (i = 0; i < rg->r_group.n_val_pairs; i++) {
struct ice_fv_word *pr;
bool found = false;
u16 mask;
u8 j;
pr = &rg->r_group.pairs[i];
mask = rg->r_group.mask[i];
for (j = 0; j < hw->blk[ICE_BLK_SW].es.fvw; j++)
if (fv_ext[j].prot_id == pr->prot_id &&
fv_ext[j].off == pr->off) {
found = true;
/* Store index of field vector */
rg->fv_idx[i] = j;
rg->fv_mask[i] = mask;
break;
}
/* Protocol/offset could not be found, caller gave an
* invalid pair
*/
if (!found)
return ICE_ERR_PARAM;
}
}
return 0;
}
/**
* ice_find_free_recp_res_idx - find free result indexes for recipe
* @hw: pointer to hardware structure
* @profiles: bitmap of profiles that will be associated with the new recipe
* @free_idx: pointer to variable to receive the free index bitmap
*
* The algorithm used here is:
* 1. When creating a new recipe, create a set P which contains all
* Profiles that will be associated with our new recipe
*
* 2. For each Profile p in set P:
* a. Add all recipes associated with Profile p into set R
* b. Optional : PossibleIndexes &= profile[p].possibleIndexes
* [initially PossibleIndexes should be 0xFFFFFFFFFFFFFFFF]
* i. Or just assume they all have the same possible indexes:
* 44, 45, 46, 47
* i.e., PossibleIndexes = 0x0000F00000000000
*
* 3. For each Recipe r in set R:
* a. UsedIndexes |= (bitwise or ) recipe[r].res_indexes
* b. FreeIndexes = UsedIndexes ^ PossibleIndexes
*
* FreeIndexes will contain the bits indicating the indexes free for use,
* then the code needs to update the recipe[r].used_result_idx_bits to
* indicate which indexes were selected for use by this recipe.
*/
static u16
ice_find_free_recp_res_idx(struct ice_hw *hw, const ice_bitmap_t *profiles,
ice_bitmap_t *free_idx)
{
ice_declare_bitmap(possible_idx, ICE_MAX_FV_WORDS);
ice_declare_bitmap(recipes, ICE_MAX_NUM_RECIPES);
ice_declare_bitmap(used_idx, ICE_MAX_FV_WORDS);
u16 bit;
ice_zero_bitmap(possible_idx, ICE_MAX_FV_WORDS);
ice_zero_bitmap(recipes, ICE_MAX_NUM_RECIPES);
ice_zero_bitmap(used_idx, ICE_MAX_FV_WORDS);
ice_zero_bitmap(free_idx, ICE_MAX_FV_WORDS);
ice_bitmap_set(possible_idx, 0, ICE_MAX_FV_WORDS);
/* For each profile we are going to associate the recipe with, add the
* recipes that are associated with that profile. This will give us
* the set of recipes that our recipe may collide with. Also, determine
* what possible result indexes are usable given this set of profiles.
*/
ice_for_each_set_bit(bit, profiles, ICE_MAX_NUM_PROFILES) {
ice_or_bitmap(recipes, recipes, profile_to_recipe[bit],
ICE_MAX_NUM_RECIPES);
ice_and_bitmap(possible_idx, possible_idx,
hw->switch_info->prof_res_bm[bit],
ICE_MAX_FV_WORDS);
}
/* For each recipe that our new recipe may collide with, determine
* which indexes have been used.
*/
ice_for_each_set_bit(bit, recipes, ICE_MAX_NUM_RECIPES)
ice_or_bitmap(used_idx, used_idx,
hw->switch_info->recp_list[bit].res_idxs,
ICE_MAX_FV_WORDS);
ice_xor_bitmap(free_idx, used_idx, possible_idx, ICE_MAX_FV_WORDS);
/* return number of free indexes */
return ice_bitmap_hweight(free_idx, ICE_MAX_FV_WORDS);
}
static void ice_set_recipe_index(unsigned long idx, u8 *bitmap)
{
u32 byte = idx / BITS_PER_BYTE;
u32 bit = idx % BITS_PER_BYTE;
if (byte >= 8)
return;
bitmap[byte] |= 1 << bit;
}
/**
* ice_add_sw_recipe - function to call AQ calls to create switch recipe
* @hw: pointer to hardware structure
* @rm: recipe management list entry
* @profiles: bitmap of profiles that will be associated.
*/
static int
ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,
ice_bitmap_t *profiles)
{
ice_declare_bitmap(result_idx_bm, ICE_MAX_FV_WORDS);
struct ice_aqc_recipe_data_elem *tmp;
struct ice_aqc_recipe_data_elem *buf;
struct ice_recp_grp_entry *entry;
u16 free_res_idx;
u16 recipe_count;
u8 chain_idx;
u8 recps = 0;
int status;
/* When more than one recipe are required, another recipe is needed to
* chain them together. Matching a tunnel metadata ID takes up one of
* the match fields in the chaining recipe reducing the number of
* chained recipes by one.
*/
/* check number of free result indices */
ice_zero_bitmap(result_idx_bm, ICE_MAX_FV_WORDS);
free_res_idx = ice_find_free_recp_res_idx(hw, profiles, result_idx_bm);
ice_debug(hw, ICE_DBG_SW, "Result idx slots: %d, need %d\n",
free_res_idx, rm->n_grp_count);
if (rm->n_grp_count > 1) {
if (rm->n_grp_count > free_res_idx)
return ICE_ERR_MAX_LIMIT;
rm->n_grp_count++;
}
if (rm->n_grp_count > ICE_MAX_CHAIN_RECIPE)
return ICE_ERR_MAX_LIMIT;
tmp = (struct ice_aqc_recipe_data_elem *)ice_calloc(hw,
ICE_MAX_NUM_RECIPES,
sizeof(*tmp));
if (!tmp)
return ICE_ERR_NO_MEMORY;
buf = (struct ice_aqc_recipe_data_elem *)
ice_calloc(hw, rm->n_grp_count, sizeof(*buf));
if (!buf) {
status = ICE_ERR_NO_MEMORY;
goto err_mem;
}
ice_zero_bitmap(rm->r_bitmap, ICE_MAX_NUM_RECIPES);
recipe_count = ICE_MAX_NUM_RECIPES;
status = ice_aq_get_recipe(hw, tmp, &recipe_count, ICE_SW_LKUP_MAC,
NULL);
if (status || recipe_count == 0)
goto err_unroll;
/* Allocate the recipe resources, and configure them according to the
* match fields from protocol headers and extracted field vectors.
*/
chain_idx = (u8)ice_find_first_bit(result_idx_bm, ICE_MAX_FV_WORDS);
LIST_FOR_EACH_ENTRY(entry, &rm->rg_list, ice_recp_grp_entry, l_entry) {
u8 i;
status = ice_alloc_recipe(hw, &entry->rid);
if (status)
goto err_unroll;
/* Clear the result index of the located recipe, as this will be
* updated, if needed, later in the recipe creation process.
*/
tmp[0].content.result_indx = 0;
buf[recps] = tmp[0];
buf[recps].recipe_indx = (u8)entry->rid;
/* if the recipe is a non-root recipe RID should be programmed
* as 0 for the rules to be applied correctly.
*/
buf[recps].content.rid = 0;
ice_memset(&buf[recps].content.lkup_indx, 0,
sizeof(buf[recps].content.lkup_indx),
ICE_NONDMA_MEM);
/* All recipes use look-up index 0 to match switch ID. */
buf[recps].content.lkup_indx[0] = ICE_AQ_SW_ID_LKUP_IDX;
buf[recps].content.mask[0] =
CPU_TO_LE16(ICE_AQ_SW_ID_LKUP_MASK);
/* Setup lkup_indx 1..4 to INVALID/ignore and set the mask
* to be 0
*/
for (i = 1; i <= ICE_NUM_WORDS_RECIPE; i++) {
buf[recps].content.lkup_indx[i] = 0x80;
buf[recps].content.mask[i] = 0;
}
for (i = 0; i < entry->r_group.n_val_pairs; i++) {
buf[recps].content.lkup_indx[i + 1] =
(u8)entry->fv_idx[i];
buf[recps].content.mask[i + 1] =
CPU_TO_LE16(entry->fv_mask[i]);
}
if (rm->n_grp_count > 1) {
/* Checks to see if there really is a valid result index
* that can be used.
*/
if (chain_idx >= ICE_MAX_FV_WORDS) {
ice_debug(hw, ICE_DBG_SW, "No chain index available\n");
status = ICE_ERR_MAX_LIMIT;
goto err_unroll;
}
entry->chain_idx = chain_idx;
buf[recps].content.result_indx =
ICE_AQ_RECIPE_RESULT_EN |
((chain_idx << ICE_AQ_RECIPE_RESULT_DATA_S) &
ICE_AQ_RECIPE_RESULT_DATA_M);
ice_clear_bit(chain_idx, result_idx_bm);
chain_idx = (u8)ice_find_first_bit(result_idx_bm,
ICE_MAX_FV_WORDS);
}
/* fill recipe dependencies */
ice_memset(buf[recps].recipe_bitmap, 0,
sizeof(buf[recps].recipe_bitmap), ICE_NONDMA_MEM);
ice_set_recipe_index(buf[recps].recipe_indx,
buf[recps].recipe_bitmap);
buf[recps].content.act_ctrl_fwd_priority = rm->priority;
recps++;
}
if (rm->n_grp_count == 1) {
rm->root_rid = buf[0].recipe_indx;
ice_set_bit(buf[0].recipe_indx, rm->r_bitmap);
buf[0].content.rid = rm->root_rid | ICE_AQ_RECIPE_ID_IS_ROOT;
if (sizeof(buf[0].recipe_bitmap) >= sizeof(rm->r_bitmap)) {
ice_memcpy(buf[0].recipe_bitmap, rm->r_bitmap,
sizeof(buf[0].recipe_bitmap),
ICE_NONDMA_TO_NONDMA);
} else {
status = ICE_ERR_BAD_PTR;
goto err_unroll;
}
/* Applicable only for ROOT_RECIPE, set the fwd_priority for
* the recipe which is getting created if specified
* by user. Usually any advanced switch filter, which results
* into new extraction sequence, ended up creating a new recipe
* of type ROOT and usually recipes are associated with profiles
* Switch rule referreing newly created recipe, needs to have
* either/or 'fwd' or 'join' priority, otherwise switch rule
* evaluation will not happen correctly. In other words, if
* switch rule to be evaluated on priority basis, then recipe
* needs to have priority, otherwise it will be evaluated last.
*/
buf[0].content.act_ctrl_fwd_priority = rm->priority;
} else {
struct ice_recp_grp_entry *last_chain_entry;
u16 rid, i;
/* Allocate the last recipe that will chain the outcomes of the
* other recipes together
*/
status = ice_alloc_recipe(hw, &rid);
if (status)
goto err_unroll;
buf[recps].recipe_indx = (u8)rid;
buf[recps].content.rid = (u8)rid;
buf[recps].content.rid |= ICE_AQ_RECIPE_ID_IS_ROOT;
/* the new entry created should also be part of rg_list to
* make sure we have complete recipe
*/
last_chain_entry = (struct ice_recp_grp_entry *)ice_malloc(hw,
sizeof(*last_chain_entry));
if (!last_chain_entry) {
status = ICE_ERR_NO_MEMORY;
goto err_unroll;
}
last_chain_entry->rid = rid;
ice_memset(&buf[recps].content.lkup_indx, 0,
sizeof(buf[recps].content.lkup_indx),
ICE_NONDMA_MEM);
/* All recipes use look-up index 0 to match switch ID. */
buf[recps].content.lkup_indx[0] = ICE_AQ_SW_ID_LKUP_IDX;
buf[recps].content.mask[0] =
CPU_TO_LE16(ICE_AQ_SW_ID_LKUP_MASK);
for (i = 1; i <= ICE_NUM_WORDS_RECIPE; i++) {
buf[recps].content.lkup_indx[i] =
ICE_AQ_RECIPE_LKUP_IGNORE;
buf[recps].content.mask[i] = 0;
}
i = 1;
/* update r_bitmap with the recp that is used for chaining */
ice_set_bit(rid, rm->r_bitmap);
/* this is the recipe that chains all the other recipes so it
* should not have a chaining ID to indicate the same
*/
last_chain_entry->chain_idx = ICE_INVAL_CHAIN_IND;
LIST_FOR_EACH_ENTRY(entry, &rm->rg_list, ice_recp_grp_entry,
l_entry) {
buf[recps].content.lkup_indx[i] = entry->chain_idx;
buf[recps].content.mask[i++] = CPU_TO_LE16(0xFFFF);
ice_set_bit(entry->rid, rm->r_bitmap);
}
LIST_ADD(&last_chain_entry->l_entry, &rm->rg_list);
if (sizeof(buf[recps].recipe_bitmap) >=
sizeof(rm->r_bitmap)) {
ice_memcpy(buf[recps].recipe_bitmap, rm->r_bitmap,
sizeof(buf[recps].recipe_bitmap),
ICE_NONDMA_TO_NONDMA);
} else {
status = ICE_ERR_BAD_PTR;
goto err_unroll;
}
buf[recps].content.act_ctrl_fwd_priority = rm->priority;
recps++;
rm->root_rid = (u8)rid;
}
status = ice_acquire_change_lock(hw, ICE_RES_WRITE);
if (status)
goto err_unroll;
status = ice_aq_add_recipe(hw, buf, rm->n_grp_count, NULL);
ice_release_change_lock(hw);
if (status)
goto err_unroll;
/* Every recipe that just got created add it to the recipe
* book keeping list
*/
LIST_FOR_EACH_ENTRY(entry, &rm->rg_list, ice_recp_grp_entry, l_entry) {
struct ice_switch_info *sw = hw->switch_info;
bool is_root, idx_found = false;
struct ice_sw_recipe *recp;
u16 idx, buf_idx = 0;
/* find buffer index for copying some data */
for (idx = 0; idx < rm->n_grp_count; idx++)
if (buf[idx].recipe_indx == entry->rid) {
buf_idx = idx;
idx_found = true;
}
if (!idx_found) {
status = ICE_ERR_OUT_OF_RANGE;
goto err_unroll;
}
recp = &sw->recp_list[entry->rid];
is_root = (rm->root_rid == entry->rid);
recp->is_root = is_root;
recp->root_rid = (u8)entry->rid;
recp->big_recp = (is_root && rm->n_grp_count > 1);
ice_memcpy(&recp->ext_words, entry->r_group.pairs,
entry->r_group.n_val_pairs *
sizeof(struct ice_fv_word),
ICE_NONDMA_TO_NONDMA);
ice_memcpy(recp->r_bitmap, buf[buf_idx].recipe_bitmap,
sizeof(recp->r_bitmap), ICE_NONDMA_TO_NONDMA);
/* Copy non-result fv index values and masks to recipe. This
* call will also update the result recipe bitmask.
*/
ice_collect_result_idx(&buf[buf_idx], recp);
/* for non-root recipes, also copy to the root, this allows
* easier matching of a complete chained recipe
*/
if (!is_root)
ice_collect_result_idx(&buf[buf_idx],
&sw->recp_list[rm->root_rid]);
recp->n_ext_words = entry->r_group.n_val_pairs;
recp->chain_idx = entry->chain_idx;
recp->priority = buf[buf_idx].content.act_ctrl_fwd_priority;
recp->n_grp_count = rm->n_grp_count;
recp->tun_type = rm->tun_type;
recp->recp_created = true;
}
rm->root_buf = buf;
ice_free(hw, tmp);
return status;
err_unroll:
err_mem:
ice_free(hw, tmp);
ice_free(hw, buf);
return status;
}
/**
* ice_create_recipe_group - creates recipe group
* @hw: pointer to hardware structure
* @rm: recipe management list entry
* @lkup_exts: lookup elements
*/
static int
ice_create_recipe_group(struct ice_hw *hw, struct ice_sw_recipe *rm,
struct ice_prot_lkup_ext *lkup_exts)
{
u8 recp_count = 0;
int status;
rm->n_grp_count = 0;
/* Create recipes for words that are marked not done by packing them
* as best fit.
*/
status = ice_create_first_fit_recp_def(hw, lkup_exts,
&rm->rg_list, &recp_count);
if (!status) {
rm->n_grp_count += recp_count;
rm->n_ext_words = lkup_exts->n_val_words;
ice_memcpy(&rm->ext_words, lkup_exts->fv_words,
sizeof(rm->ext_words), ICE_NONDMA_TO_NONDMA);
ice_memcpy(rm->word_masks, lkup_exts->field_mask,
sizeof(rm->word_masks), ICE_NONDMA_TO_NONDMA);
}
return status;
}
/**
* ice_tun_type_match_word - determine if tun type needs a match mask
* @rinfo: other information regarding the rule e.g. priority and action info
* @off: offset of packet flag
* @mask: mask to be used for the tunnel
*/
static bool
ice_tun_type_match_word(struct ice_adv_rule_info *rinfo, u16 *off, u16 *mask)
{
switch (rinfo->tun_type) {
case ICE_SW_TUN_VXLAN_GPE:
case ICE_SW_TUN_GENEVE:
case ICE_SW_TUN_VXLAN:
case ICE_SW_TUN_NVGRE:
case ICE_SW_TUN_UDP:
case ICE_ALL_TUNNELS:
case ICE_SW_TUN_AND_NON_TUN_QINQ:
case ICE_NON_TUN_QINQ:
case ICE_SW_TUN_PPPOE_QINQ:
case ICE_SW_TUN_PPPOE_PAY_QINQ:
case ICE_SW_TUN_PPPOE_IPV4_QINQ:
case ICE_SW_TUN_PPPOE_IPV6_QINQ:
*mask = ICE_TUN_FLAG_MASK;
*off = ICE_TUN_FLAG_MDID_OFF(1);
return true;
case ICE_SW_TUN_AND_NON_TUN:
if (rinfo->add_dir_lkup) {
*mask = ICE_DIR_FLAG_MASK;
*off = ICE_TUN_FLAG_MDID_OFF(0);
return true;
}
*mask = 0;
*off = 0;
return false;
case ICE_SW_TUN_GENEVE_VLAN:
case ICE_SW_TUN_VXLAN_VLAN:
*mask = ICE_TUN_FLAG_MASK & ~(ICE_TUN_FLAG_VLAN_MASK |
ICE_TUN_FLAG_IN_VLAN_MASK);
*off = ICE_TUN_FLAG_MDID_OFF(1);
return true;
default:
*mask = 0;
*off = 0;
return false;
}
}
/**
* ice_add_special_words - Add words that are not protocols, such as metadata
* @rinfo: other information regarding the rule e.g. priority and action info
* @lkup_exts: lookup word structure
* @dvm_ena: is double VLAN mode enabled
*/
static int
ice_add_special_words(struct ice_adv_rule_info *rinfo,
struct ice_prot_lkup_ext *lkup_exts, bool dvm_ena)
{
u16 mask;
u16 off;
/*
* Failing to add direction metadata is not considered an error, because
* the kinds of rules which would trigger this error are already so
* highly specific that they're unlikely to match both Rx and Tx traffic
* at the same time.
*/
if (lkup_exts->n_val_words < ICE_MAX_CHAIN_WORDS) {
u8 word = lkup_exts->n_val_words++;
lkup_exts->fv_words[word].prot_id = ICE_META_DATA_ID_HW;
lkup_exts->fv_words[word].off = ICE_TUN_FLAG_MDID_OFF(0);
lkup_exts->field_mask[word] = ICE_FROM_NETWORK_FLAG_MASK;
}
/* If this is a tunneled packet, then add recipe index to match the
* tunnel bit in the packet metadata flags. If this is a tun_and_non_tun
* packet, then add recipe index to match the direction bit in the flag.
*/
if (ice_tun_type_match_word(rinfo, &off, &mask)) {
if (lkup_exts->n_val_words < ICE_MAX_CHAIN_WORDS) {
u8 word = lkup_exts->n_val_words++;
lkup_exts->fv_words[word].prot_id = ICE_META_DATA_ID_HW;
lkup_exts->fv_words[word].off = off;
lkup_exts->field_mask[word] = mask;
} else {
return ICE_ERR_MAX_LIMIT;
}
}
if (rinfo->vlan_type != 0 && dvm_ena) {
if (lkup_exts->n_val_words < ICE_MAX_CHAIN_WORDS) {
u8 word = lkup_exts->n_val_words++;
lkup_exts->fv_words[word].prot_id = ICE_META_DATA_ID_HW;
lkup_exts->fv_words[word].off = ICE_VLAN_FLAG_MDID_OFF;
lkup_exts->field_mask[word] =
ICE_PKT_FLAGS_0_TO_15_VLAN_FLAGS_MASK;
} else {
return ICE_ERR_MAX_LIMIT;
}
}
return 0;
}
/* ice_get_compat_fv_bitmap - Get compatible field vector bitmap for rule
* @hw: pointer to hardware structure
* @rinfo: other information regarding the rule e.g. priority and action info
* @bm: pointer to memory for returning the bitmap of field vectors
*/
static void
ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo,
ice_bitmap_t *bm)
{
enum ice_prof_type prof_type;
ice_zero_bitmap(bm, ICE_MAX_NUM_PROFILES);
switch (rinfo->tun_type) {
case ICE_NON_TUN:
case ICE_NON_TUN_QINQ:
prof_type = ICE_PROF_NON_TUN;
break;
case ICE_ALL_TUNNELS:
prof_type = ICE_PROF_TUN_ALL;
break;
case ICE_SW_TUN_VXLAN_GPE:
case ICE_SW_TUN_GENEVE:
case ICE_SW_TUN_GENEVE_VLAN:
case ICE_SW_TUN_VXLAN:
case ICE_SW_TUN_VXLAN_VLAN:
case ICE_SW_TUN_UDP:
case ICE_SW_TUN_GTP:
prof_type = ICE_PROF_TUN_UDP;
break;
case ICE_SW_TUN_NVGRE:
prof_type = ICE_PROF_TUN_GRE;
break;
case ICE_SW_IPV4_TCP:
ice_set_bit(ICE_PROFID_IPV4_TCP, bm);
return;
case ICE_SW_IPV4_UDP:
ice_set_bit(ICE_PROFID_IPV4_UDP, bm);
return;
case ICE_SW_IPV6_TCP:
ice_set_bit(ICE_PROFID_IPV6_TCP, bm);
return;
case ICE_SW_IPV6_UDP:
ice_set_bit(ICE_PROFID_IPV6_UDP, bm);
return;
case ICE_SW_TUN_PPPOE:
case ICE_SW_TUN_PPPOE_QINQ:
prof_type = ICE_PROF_TUN_PPPOE;
break;
case ICE_SW_TUN_PPPOE_PAY:
case ICE_SW_TUN_PPPOE_PAY_QINQ:
ice_set_bit(ICE_PROFID_PPPOE_PAY, bm);
return;
case ICE_SW_TUN_PPPOE_IPV4:
case ICE_SW_TUN_PPPOE_IPV4_QINQ:
ice_set_bit(ICE_PROFID_PPPOE_IPV4_OTHER, bm);
ice_set_bit(ICE_PROFID_PPPOE_IPV4_UDP, bm);
ice_set_bit(ICE_PROFID_PPPOE_IPV4_TCP, bm);
return;
case ICE_SW_TUN_PPPOE_IPV4_TCP:
ice_set_bit(ICE_PROFID_PPPOE_IPV4_TCP, bm);
return;
case ICE_SW_TUN_PPPOE_IPV4_UDP:
ice_set_bit(ICE_PROFID_PPPOE_IPV4_UDP, bm);
return;
case ICE_SW_TUN_PPPOE_IPV6:
case ICE_SW_TUN_PPPOE_IPV6_QINQ:
ice_set_bit(ICE_PROFID_PPPOE_IPV6_OTHER, bm);
ice_set_bit(ICE_PROFID_PPPOE_IPV6_UDP, bm);
ice_set_bit(ICE_PROFID_PPPOE_IPV6_TCP, bm);
return;
case ICE_SW_TUN_PPPOE_IPV6_TCP:
ice_set_bit(ICE_PROFID_PPPOE_IPV6_TCP, bm);
return;
case ICE_SW_TUN_PPPOE_IPV6_UDP:
ice_set_bit(ICE_PROFID_PPPOE_IPV6_UDP, bm);
return;
case ICE_SW_TUN_PROFID_IPV6_ESP:
case ICE_SW_TUN_IPV6_ESP:
ice_set_bit(ICE_PROFID_IPV6_ESP, bm);
return;
case ICE_SW_TUN_PROFID_IPV6_AH:
case ICE_SW_TUN_IPV6_AH:
ice_set_bit(ICE_PROFID_IPV6_AH, bm);
return;
case ICE_SW_TUN_PROFID_MAC_IPV6_L2TPV3:
case ICE_SW_TUN_IPV6_L2TPV3:
ice_set_bit(ICE_PROFID_MAC_IPV6_L2TPV3, bm);
return;
case ICE_SW_TUN_PROFID_IPV6_NAT_T:
case ICE_SW_TUN_IPV6_NAT_T:
ice_set_bit(ICE_PROFID_IPV6_NAT_T, bm);
return;
case ICE_SW_TUN_PROFID_IPV4_PFCP_NODE:
ice_set_bit(ICE_PROFID_IPV4_PFCP_NODE, bm);
return;
case ICE_SW_TUN_PROFID_IPV4_PFCP_SESSION:
ice_set_bit(ICE_PROFID_IPV4_PFCP_SESSION, bm);
return;
case ICE_SW_TUN_PROFID_IPV6_PFCP_NODE:
ice_set_bit(ICE_PROFID_IPV6_PFCP_NODE, bm);
return;
case ICE_SW_TUN_PROFID_IPV6_PFCP_SESSION:
ice_set_bit(ICE_PROFID_IPV6_PFCP_SESSION, bm);
return;
case ICE_SW_TUN_IPV4_NAT_T:
ice_set_bit(ICE_PROFID_IPV4_NAT_T, bm);
return;
case ICE_SW_TUN_IPV4_L2TPV3:
ice_set_bit(ICE_PROFID_MAC_IPV4_L2TPV3, bm);
return;
case ICE_SW_TUN_IPV4_ESP:
ice_set_bit(ICE_PROFID_IPV4_ESP, bm);
return;
case ICE_SW_TUN_IPV4_AH:
ice_set_bit(ICE_PROFID_IPV4_AH, bm);
return;
case ICE_SW_TUN_IPV4_GTPU_NO_PAY:
ice_set_bit(ICE_PROFID_IPV4_GTPU_TEID, bm);
return;
case ICE_SW_TUN_IPV6_GTPU_NO_PAY:
ice_set_bit(ICE_PROFID_IPV6_GTPU_TEID, bm);
return;
case ICE_SW_TUN_IPV4_GTPU_IPV4:
ice_set_bit(ICE_PROFID_IPV4_GTPU_IPV4_OTHER, bm);
ice_set_bit(ICE_PROFID_IPV4_GTPU_IPV4_UDP, bm);
ice_set_bit(ICE_PROFID_IPV4_GTPU_IPV4_TCP, bm);
return;
case ICE_SW_TUN_IPV4_GTPU_IPV4_UDP:
ice_set_bit(ICE_PROFID_IPV4_GTPU_IPV4_UDP, bm);
return;
case ICE_SW_TUN_IPV4_GTPU_IPV4_TCP:
ice_set_bit(ICE_PROFID_IPV4_GTPU_IPV4_TCP, bm);
return;
case ICE_SW_TUN_IPV4_GTPU_EH_IPV4:
ice_set_bit(ICE_PROFID_IPV4_GTPU_EH_IPV4_OTHER, bm);
ice_set_bit(ICE_PROFID_IPV4_GTPU_EH_IPV4_UDP, bm);
ice_set_bit(ICE_PROFID_IPV4_GTPU_EH_IPV4_TCP, bm);
return;
case ICE_SW_TUN_IPV4_GTPU_EH_IPV4_UDP:
ice_set_bit(ICE_PROFID_IPV4_GTPU_EH_IPV4_UDP, bm);
return;
case ICE_SW_TUN_IPV4_GTPU_EH_IPV4_TCP:
ice_set_bit(ICE_PROFID_IPV4_GTPU_EH_IPV4_TCP, bm);
return;
case ICE_SW_TUN_IPV6_GTPU_IPV4:
ice_set_bit(ICE_PROFID_IPV6_GTPU_IPV4_OTHER, bm);
ice_set_bit(ICE_PROFID_IPV6_GTPU_IPV4_UDP, bm);
ice_set_bit(ICE_PROFID_IPV6_GTPU_IPV4_TCP, bm);
return;
case ICE_SW_TUN_IPV6_GTPU_IPV4_UDP:
ice_set_bit(ICE_PROFID_IPV6_GTPU_IPV4_UDP, bm);
return;
case ICE_SW_TUN_IPV6_GTPU_IPV4_TCP:
ice_set_bit(ICE_PROFID_IPV6_GTPU_IPV4_TCP, bm);
return;
case ICE_SW_TUN_IPV6_GTPU_EH_IPV4:
ice_set_bit(ICE_PROFID_IPV6_GTPU_EH_IPV4_OTHER, bm);
ice_set_bit(ICE_PROFID_IPV6_GTPU_EH_IPV4_UDP, bm);
ice_set_bit(ICE_PROFID_IPV6_GTPU_EH_IPV4_TCP, bm);
return;
case ICE_SW_TUN_IPV6_GTPU_EH_IPV4_UDP:
ice_set_bit(ICE_PROFID_IPV6_GTPU_EH_IPV4_UDP, bm);
return;
case ICE_SW_TUN_IPV6_GTPU_EH_IPV4_TCP:
ice_set_bit(ICE_PROFID_IPV6_GTPU_EH_IPV4_TCP, bm);
return;
case ICE_SW_TUN_IPV4_GTPU_IPV6:
ice_set_bit(ICE_PROFID_IPV4_GTPU_IPV6_OTHER, bm);
ice_set_bit(ICE_PROFID_IPV4_GTPU_IPV6_UDP, bm);
ice_set_bit(ICE_PROFID_IPV4_GTPU_IPV6_TCP, bm);
return;
case ICE_SW_TUN_IPV4_GTPU_IPV6_UDP:
ice_set_bit(ICE_PROFID_IPV4_GTPU_IPV6_UDP, bm);
return;
case ICE_SW_TUN_IPV4_GTPU_IPV6_TCP:
ice_set_bit(ICE_PROFID_IPV4_GTPU_IPV6_TCP, bm);
return;
case ICE_SW_TUN_IPV4_GTPU_EH_IPV6:
ice_set_bit(ICE_PROFID_IPV4_GTPU_EH_IPV6_OTHER, bm);
ice_set_bit(ICE_PROFID_IPV4_GTPU_EH_IPV6_UDP, bm);
ice_set_bit(ICE_PROFID_IPV4_GTPU_EH_IPV6_TCP, bm);
return;
case ICE_SW_TUN_IPV4_GTPU_EH_IPV6_UDP:
ice_set_bit(ICE_PROFID_IPV4_GTPU_EH_IPV6_UDP, bm);
return;
case ICE_SW_TUN_IPV4_GTPU_EH_IPV6_TCP:
ice_set_bit(ICE_PROFID_IPV4_GTPU_EH_IPV6_TCP, bm);
return;
case ICE_SW_TUN_IPV6_GTPU_IPV6:
ice_set_bit(ICE_PROFID_IPV6_GTPU_IPV6_OTHER, bm);
ice_set_bit(ICE_PROFID_IPV6_GTPU_IPV6_UDP, bm);
ice_set_bit(ICE_PROFID_IPV6_GTPU_IPV6_TCP, bm);
return;
case ICE_SW_TUN_IPV6_GTPU_IPV6_UDP:
ice_set_bit(ICE_PROFID_IPV6_GTPU_IPV6_UDP, bm);
return;
case ICE_SW_TUN_IPV6_GTPU_IPV6_TCP:
ice_set_bit(ICE_PROFID_IPV6_GTPU_IPV6_TCP, bm);
return;
case ICE_SW_TUN_IPV6_GTPU_EH_IPV6:
ice_set_bit(ICE_PROFID_IPV6_GTPU_EH_IPV6_OTHER, bm);
ice_set_bit(ICE_PROFID_IPV6_GTPU_EH_IPV6_UDP, bm);
ice_set_bit(ICE_PROFID_IPV6_GTPU_EH_IPV6_TCP, bm);
return;
case ICE_SW_TUN_IPV6_GTPU_EH_IPV6_UDP:
ice_set_bit(ICE_PROFID_IPV6_GTPU_EH_IPV6_UDP, bm);
return;
case ICE_SW_TUN_IPV6_GTPU_EH_IPV6_TCP:
ice_set_bit(ICE_PROFID_IPV6_GTPU_EH_IPV6_TCP, bm);
return;
case ICE_SW_TUN_AND_NON_TUN:
case ICE_SW_TUN_AND_NON_TUN_QINQ:
default:
prof_type = ICE_PROF_ALL;
break;
}
ice_get_sw_fv_bitmap(hw, prof_type, bm);
}
/**
* ice_is_prof_rule - determine if rule type is a profile rule
* @type: the rule type
*
* if the rule type is a profile rule, that means that there no field value
* match required, in this case just a profile hit is required.
*/
bool ice_is_prof_rule(enum ice_sw_tunnel_type type)
{
switch (type) {
case ICE_SW_TUN_AND_NON_TUN:
case ICE_SW_TUN_PROFID_IPV6_ESP:
case ICE_SW_TUN_PROFID_IPV6_AH:
case ICE_SW_TUN_PROFID_MAC_IPV6_L2TPV3:
case ICE_SW_TUN_PROFID_IPV6_NAT_T:
case ICE_SW_TUN_PROFID_IPV4_PFCP_NODE:
case ICE_SW_TUN_PROFID_IPV4_PFCP_SESSION:
case ICE_SW_TUN_PROFID_IPV6_PFCP_NODE:
case ICE_SW_TUN_PROFID_IPV6_PFCP_SESSION:
return true;
default:
break;
}
return false;
}
/**
* ice_add_adv_recipe - Add an advanced recipe that is not part of the default
* @hw: pointer to hardware structure
* @lkups: lookup elements or match criteria for the advanced recipe, one
* structure per protocol header
* @lkups_cnt: number of protocols
* @rinfo: other information regarding the rule e.g. priority and action info
* @rid: return the recipe ID of the recipe created
*/
int
ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
u16 lkups_cnt, struct ice_adv_rule_info *rinfo, u16 *rid)
{
ice_declare_bitmap(fv_bitmap, ICE_MAX_NUM_PROFILES);
ice_declare_bitmap(profiles, ICE_MAX_NUM_PROFILES);
struct ice_prot_lkup_ext *lkup_exts;
struct ice_recp_grp_entry *r_entry;
struct ice_sw_fv_list_entry *fvit;
struct ice_recp_grp_entry *r_tmp;
struct ice_sw_fv_list_entry *tmp;
struct ice_sw_recipe *rm;
u8 i;
int status = ICE_SUCCESS;
if (!ice_is_prof_rule(rinfo->tun_type) && !lkups_cnt)
return ICE_ERR_PARAM;
lkup_exts = (struct ice_prot_lkup_ext *)
ice_malloc(hw, sizeof(*lkup_exts));
if (!lkup_exts)
return ICE_ERR_NO_MEMORY;
/* Determine the number of words to be matched and if it exceeds a
* recipe's restrictions
*/
for (i = 0; i < lkups_cnt; i++) {
u16 count;
if (lkups[i].type >= ICE_PROTOCOL_LAST) {
status = ICE_ERR_CFG;
goto err_free_lkup_exts;
}
count = ice_fill_valid_words(&lkups[i], lkup_exts);
if (!count) {
status = ICE_ERR_CFG;
goto err_free_lkup_exts;
}
}
rm = (struct ice_sw_recipe *)ice_malloc(hw, sizeof(*rm));
if (!rm) {
status = ICE_ERR_NO_MEMORY;
goto err_free_lkup_exts;
}
/* Get field vectors that contain fields extracted from all the protocol
* headers being programmed.
*/
INIT_LIST_HEAD(&rm->fv_list);
INIT_LIST_HEAD(&rm->rg_list);
/* Get bitmap of field vectors (profiles) that are compatible with the
* rule request; only these will be searched in the subsequent call to
* ice_get_sw_fv_list.
*/
ice_get_compat_fv_bitmap(hw, rinfo, fv_bitmap);
/* Create any special protocol/offset pairs, such as looking at tunnel
* bits by extracting metadata
*/
status = ice_add_special_words(rinfo, lkup_exts, ice_is_dvm_ena(hw));
if (status)
goto err_free_lkup_exts;
status = ice_get_sw_fv_list(hw, lkup_exts, fv_bitmap, &rm->fv_list);
if (status)
goto err_unroll;
/* Group match words into recipes using preferred recipe grouping
* criteria.
*/
status = ice_create_recipe_group(hw, rm, lkup_exts);
if (status)
goto err_unroll;
/* set the recipe priority if specified */
rm->priority = (u8)rinfo->priority;
/* Find offsets from the field vector. Pick the first one for all the
* recipes.
*/
status = ice_fill_fv_word_index(hw, &rm->fv_list, &rm->rg_list);
if (status)
goto err_unroll;
/* An empty FV list means to use all the profiles returned in the
* profile bitmap
*/
if (LIST_EMPTY(&rm->fv_list)) {
u16 j;
ice_for_each_set_bit(j, fv_bitmap, ICE_MAX_NUM_PROFILES) {
struct ice_sw_fv_list_entry *fvl;
fvl = (struct ice_sw_fv_list_entry *)
ice_malloc(hw, sizeof(*fvl));
if (!fvl)
goto err_unroll;
fvl->fv_ptr = NULL;
fvl->profile_id = j;
LIST_ADD(&fvl->list_entry, &rm->fv_list);
}
}
/* get bitmap of all profiles the recipe will be associated with */
ice_zero_bitmap(profiles, ICE_MAX_NUM_PROFILES);
LIST_FOR_EACH_ENTRY(fvit, &rm->fv_list, ice_sw_fv_list_entry,
list_entry) {
ice_debug(hw, ICE_DBG_SW, "profile: %d\n", fvit->profile_id);
ice_set_bit((u16)fvit->profile_id, profiles);
}
/* Look for a recipe which matches our requested fv / mask list */
*rid = ice_find_recp(hw, lkup_exts, rinfo->tun_type, rinfo->priority);
if (*rid < ICE_MAX_NUM_RECIPES)
/* Success if found a recipe that match the existing criteria */
goto err_unroll;
rm->tun_type = rinfo->tun_type;
/* Recipe we need does not exist, add a recipe */
status = ice_add_sw_recipe(hw, rm, profiles);
if (status)
goto err_unroll;
/* Associate all the recipes created with all the profiles in the
* common field vector.
*/
LIST_FOR_EACH_ENTRY(fvit, &rm->fv_list, ice_sw_fv_list_entry,
list_entry) {
ice_declare_bitmap(r_bitmap, ICE_MAX_NUM_RECIPES);
u16 j;
status = ice_aq_get_recipe_to_profile(hw, fvit->profile_id,
(u8 *)r_bitmap, NULL);
if (status)
goto err_unroll;
ice_or_bitmap(r_bitmap, r_bitmap, rm->r_bitmap,
ICE_MAX_NUM_RECIPES);
status = ice_acquire_change_lock(hw, ICE_RES_WRITE);
if (status)
goto err_unroll;
status = ice_aq_map_recipe_to_profile(hw, fvit->profile_id,
(u8 *)r_bitmap,
NULL);
ice_release_change_lock(hw);
if (status)
goto err_unroll;
/* Update profile to recipe bitmap array */
ice_cp_bitmap(profile_to_recipe[fvit->profile_id], r_bitmap,
ICE_MAX_NUM_RECIPES);
/* Update recipe to profile bitmap array */
ice_for_each_set_bit(j, rm->r_bitmap, ICE_MAX_NUM_RECIPES)
ice_set_bit((u16)fvit->profile_id,
recipe_to_profile[j]);
}
*rid = rm->root_rid;
ice_memcpy(&hw->switch_info->recp_list[*rid].lkup_exts,
lkup_exts, sizeof(*lkup_exts), ICE_NONDMA_TO_NONDMA);
err_unroll:
LIST_FOR_EACH_ENTRY_SAFE(r_entry, r_tmp, &rm->rg_list,
ice_recp_grp_entry, l_entry) {
LIST_DEL(&r_entry->l_entry);
ice_free(hw, r_entry);
}
LIST_FOR_EACH_ENTRY_SAFE(fvit, tmp, &rm->fv_list, ice_sw_fv_list_entry,
list_entry) {
LIST_DEL(&fvit->list_entry);
ice_free(hw, fvit);
}
if (rm->root_buf)
ice_free(hw, rm->root_buf);
ice_free(hw, rm);
err_free_lkup_exts:
ice_free(hw, lkup_exts);
return status;
}
/**
* ice_find_dummy_packet - find dummy packet by tunnel type
*
* @lkups: lookup elements or match criteria for the advanced recipe, one
* structure per protocol header
* @lkups_cnt: number of protocols
* @tun_type: tunnel type from the match criteria
* @pkt: dummy packet to fill according to filter match criteria
* @pkt_len: packet length of dummy packet
* @offsets: pointer to receive the pointer to the offsets for the packet
*/
void
ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
enum ice_sw_tunnel_type tun_type, const u8 **pkt,
u16 *pkt_len,
const struct ice_dummy_pkt_offsets **offsets)
{
bool tcp = false, udp = false, outer_ipv6 = false, vlan = false;
bool inner_ipv6 = false, pppoe = false;
bool cvlan = false;
bool gre = false, mpls = false;
u16 i;
for (i = 0; i < lkups_cnt; i++) {
if (lkups[i].type == ICE_UDP_ILOS)
udp = true;
else if (lkups[i].type == ICE_TCP_IL)
tcp = true;
else if (lkups[i].type == ICE_IPV6_OFOS)
outer_ipv6 = true;
else if (lkups[i].type == ICE_VLAN_OFOS ||
lkups[i].type == ICE_VLAN_EX)
vlan = true;
else if (lkups[i].type == ICE_VLAN_IN)
cvlan = true;
else if (lkups[i].type == ICE_ETYPE_OL &&
lkups[i].h_u.ethertype.ethtype_id ==
CPU_TO_BE16(ICE_IPV6_ETHER_ID) &&
lkups[i].m_u.ethertype.ethtype_id ==
CPU_TO_BE16(0xFFFF))
outer_ipv6 = true;
else if (lkups[i].type == ICE_ETYPE_IL &&
lkups[i].h_u.ethertype.ethtype_id ==
CPU_TO_BE16(ICE_IPV6_ETHER_ID) &&
lkups[i].m_u.ethertype.ethtype_id ==
CPU_TO_BE16(0xFFFF))
inner_ipv6 = true;
else if (lkups[i].type == ICE_PPPOE) {
pppoe = true;
if (lkups[i].h_u.pppoe_hdr.ppp_prot_id ==
CPU_TO_BE16(ICE_PPP_IPV6_PROTO_ID) &&
lkups[i].m_u.pppoe_hdr.ppp_prot_id ==
CPU_TO_BE16(0xFFFF))
outer_ipv6 = true;
}
else if (lkups[i].type == ICE_IPV4_OFOS &&
lkups[i].h_u.ipv4_hdr.protocol ==
ICE_IPV4_NVGRE_PROTO_ID &&
lkups[i].m_u.ipv4_hdr.protocol ==
0xFF)
gre = true;
else if (lkups[i].type == ICE_IPV4_IL &&
lkups[i].h_u.ipv4_hdr.protocol ==
ICE_TCP_PROTO_ID &&
lkups[i].m_u.ipv4_hdr.protocol ==
0xFF)
tcp = true;
else if (lkups[i].type == ICE_ETYPE_OL &&
lkups[i].h_u.ethertype.ethtype_id ==
CPU_TO_BE16(ICE_MPLS_ETHER_ID) &&
lkups[i].m_u.ethertype.ethtype_id == 0xFFFF)
mpls = true;
}
if (tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ ||
tun_type == ICE_NON_TUN_QINQ) {
if (outer_ipv6) {
if (tcp) {
*pkt = dummy_qinq_ipv6_tcp_pkt;
*pkt_len = sizeof(dummy_qinq_ipv6_tcp_pkt);
*offsets = dummy_qinq_ipv6_tcp_packet_offsets;
return;
}
if (udp) {
*pkt = dummy_qinq_ipv6_udp_pkt;
*pkt_len = sizeof(dummy_qinq_ipv6_udp_pkt);
*offsets = dummy_qinq_ipv6_udp_packet_offsets;
return;
}
*pkt = dummy_qinq_ipv6_pkt;
*pkt_len = sizeof(dummy_qinq_ipv6_pkt);
*offsets = dummy_qinq_ipv6_packet_offsets;
return;
} else {
if (tcp) {
*pkt = dummy_qinq_ipv4_tcp_pkt;
*pkt_len = sizeof(dummy_qinq_ipv4_tcp_pkt);
*offsets = dummy_qinq_ipv4_tcp_packet_offsets;
return;
}
if (udp) {
*pkt = dummy_qinq_ipv4_udp_pkt;
*pkt_len = sizeof(dummy_qinq_ipv4_udp_pkt);
*offsets = dummy_qinq_ipv4_udp_packet_offsets;
return;
}
*pkt = dummy_qinq_ipv4_pkt;
*pkt_len = sizeof(dummy_qinq_ipv4_pkt);
*offsets = dummy_qinq_ipv4_packet_offsets;
return;
}
}
if (tun_type == ICE_SW_IPV4_TCP) {
*pkt = dummy_tcp_packet;
*pkt_len = sizeof(dummy_tcp_packet);
*offsets = dummy_tcp_packet_offsets;
return;
}
if (tun_type == ICE_SW_IPV4_UDP) {
*pkt = dummy_udp_packet;
*pkt_len = sizeof(dummy_udp_packet);
*offsets = dummy_udp_packet_offsets;
return;
}
if (tun_type == ICE_SW_IPV6_TCP) {
*pkt = dummy_tcp_ipv6_packet;
*pkt_len = sizeof(dummy_tcp_ipv6_packet);
*offsets = dummy_tcp_ipv6_packet_offsets;
return;
}
if (tun_type == ICE_SW_IPV6_UDP) {
*pkt = dummy_udp_ipv6_packet;
*pkt_len = sizeof(dummy_udp_ipv6_packet);
*offsets = dummy_udp_ipv6_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_PPPOE_IPV6_QINQ) {
*pkt = dummy_qinq_pppoe_ipv6_packet;
*pkt_len = sizeof(dummy_qinq_pppoe_ipv6_packet);
*offsets = dummy_qinq_pppoe_packet_ipv6_offsets;
return;
} else if (tun_type == ICE_SW_TUN_PPPOE_IPV4_QINQ) {
*pkt = dummy_qinq_pppoe_ipv4_pkt;
*pkt_len = sizeof(dummy_qinq_pppoe_ipv4_pkt);
*offsets = dummy_qinq_pppoe_ipv4_packet_offsets;
return;
} else if (tun_type == ICE_SW_TUN_PPPOE_QINQ && outer_ipv6) {
*pkt = dummy_qinq_pppoe_ipv6_packet;
*pkt_len = sizeof(dummy_qinq_pppoe_ipv6_packet);
*offsets = dummy_qinq_pppoe_packet_offsets;
return;
} else if (tun_type == ICE_SW_TUN_PPPOE_QINQ ||
tun_type == ICE_SW_TUN_PPPOE_PAY_QINQ) {
*pkt = dummy_qinq_pppoe_ipv4_pkt;
*pkt_len = sizeof(dummy_qinq_pppoe_ipv4_pkt);
*offsets = dummy_qinq_pppoe_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV4_GTPU_NO_PAY) {
*pkt = dummy_ipv4_gtpu_ipv4_packet;
*pkt_len = sizeof(dummy_ipv4_gtpu_ipv4_packet);
*offsets = dummy_ipv4_gtp_no_pay_packet_offsets;
return;
} else if (tun_type == ICE_SW_TUN_IPV6_GTPU_NO_PAY) {
*pkt = dummy_ipv6_gtp_packet;
*pkt_len = sizeof(dummy_ipv6_gtp_packet);
*offsets = dummy_ipv6_gtp_no_pay_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV4_ESP) {
*pkt = dummy_ipv4_esp_pkt;
*pkt_len = sizeof(dummy_ipv4_esp_pkt);
*offsets = dummy_ipv4_esp_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV6_ESP) {
*pkt = dummy_ipv6_esp_pkt;
*pkt_len = sizeof(dummy_ipv6_esp_pkt);
*offsets = dummy_ipv6_esp_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV4_AH) {
*pkt = dummy_ipv4_ah_pkt;
*pkt_len = sizeof(dummy_ipv4_ah_pkt);
*offsets = dummy_ipv4_ah_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV6_AH) {
*pkt = dummy_ipv6_ah_pkt;
*pkt_len = sizeof(dummy_ipv6_ah_pkt);
*offsets = dummy_ipv6_ah_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV4_NAT_T) {
*pkt = dummy_ipv4_nat_pkt;
*pkt_len = sizeof(dummy_ipv4_nat_pkt);
*offsets = dummy_ipv4_nat_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV6_NAT_T) {
*pkt = dummy_ipv6_nat_pkt;
*pkt_len = sizeof(dummy_ipv6_nat_pkt);
*offsets = dummy_ipv6_nat_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV4_L2TPV3) {
*pkt = dummy_ipv4_l2tpv3_pkt;
*pkt_len = sizeof(dummy_ipv4_l2tpv3_pkt);
*offsets = dummy_ipv4_l2tpv3_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV6_L2TPV3) {
*pkt = dummy_ipv6_l2tpv3_pkt;
*pkt_len = sizeof(dummy_ipv6_l2tpv3_pkt);
*offsets = dummy_ipv6_l2tpv3_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_GTP) {
*pkt = dummy_udp_gtp_packet;
*pkt_len = sizeof(dummy_udp_gtp_packet);
*offsets = dummy_udp_gtp_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV4_GTPU_IPV4 ||
tun_type == ICE_SW_TUN_IPV4_GTPU_EH_IPV4) {
*pkt = dummy_ipv4_gtpu_ipv4_packet;
*pkt_len = sizeof(dummy_ipv4_gtpu_ipv4_packet);
*offsets = dummy_ipv4_gtpu_ipv4_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV4_GTPU_IPV4_UDP ||
tun_type == ICE_SW_TUN_IPV4_GTPU_EH_IPV4_UDP) {
*pkt = dummy_ipv4_gtpu_ipv4_udp_packet;
*pkt_len = sizeof(dummy_ipv4_gtpu_ipv4_udp_packet);
*offsets = dummy_ipv4_gtpu_ipv4_udp_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV4_GTPU_IPV4_TCP ||
tun_type == ICE_SW_TUN_IPV4_GTPU_EH_IPV4_TCP) {
*pkt = dummy_ipv4_gtpu_ipv4_tcp_packet;
*pkt_len = sizeof(dummy_ipv4_gtpu_ipv4_tcp_packet);
*offsets = dummy_ipv4_gtpu_ipv4_tcp_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV4_GTPU_IPV6 ||
tun_type == ICE_SW_TUN_IPV4_GTPU_EH_IPV6) {
*pkt = dummy_ipv4_gtpu_ipv6_packet;
*pkt_len = sizeof(dummy_ipv4_gtpu_ipv6_packet);
*offsets = dummy_ipv4_gtpu_ipv6_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV4_GTPU_IPV6_UDP ||
tun_type == ICE_SW_TUN_IPV4_GTPU_EH_IPV6_UDP) {
*pkt = dummy_ipv4_gtpu_ipv6_udp_packet;
*pkt_len = sizeof(dummy_ipv4_gtpu_ipv6_udp_packet);
*offsets = dummy_ipv4_gtpu_ipv6_udp_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV4_GTPU_IPV6_TCP ||
tun_type == ICE_SW_TUN_IPV4_GTPU_EH_IPV6_TCP) {
*pkt = dummy_ipv4_gtpu_ipv6_tcp_packet;
*pkt_len = sizeof(dummy_ipv4_gtpu_ipv6_tcp_packet);
*offsets = dummy_ipv4_gtpu_ipv6_tcp_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV6_GTPU_IPV4 ||
tun_type == ICE_SW_TUN_IPV6_GTPU_EH_IPV4) {
*pkt = dummy_ipv6_gtpu_ipv4_packet;
*pkt_len = sizeof(dummy_ipv6_gtpu_ipv4_packet);
*offsets = dummy_ipv6_gtpu_ipv4_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV6_GTPU_IPV4_UDP ||
tun_type == ICE_SW_TUN_IPV6_GTPU_EH_IPV4_UDP) {
*pkt = dummy_ipv6_gtpu_ipv4_udp_packet;
*pkt_len = sizeof(dummy_ipv6_gtpu_ipv4_udp_packet);
*offsets = dummy_ipv6_gtpu_ipv4_udp_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV6_GTPU_IPV4_TCP ||
tun_type == ICE_SW_TUN_IPV6_GTPU_EH_IPV4_TCP) {
*pkt = dummy_ipv6_gtpu_ipv4_tcp_packet;
*pkt_len = sizeof(dummy_ipv6_gtpu_ipv4_tcp_packet);
*offsets = dummy_ipv6_gtpu_ipv4_tcp_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV6_GTPU_IPV6 ||
tun_type == ICE_SW_TUN_IPV6_GTPU_EH_IPV6) {
*pkt = dummy_ipv6_gtpu_ipv6_packet;
*pkt_len = sizeof(dummy_ipv6_gtpu_ipv6_packet);
*offsets = dummy_ipv6_gtpu_ipv6_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV6_GTPU_IPV6_UDP ||
tun_type == ICE_SW_TUN_IPV6_GTPU_EH_IPV6_UDP) {
*pkt = dummy_ipv6_gtpu_ipv6_udp_packet;
*pkt_len = sizeof(dummy_ipv6_gtpu_ipv6_udp_packet);
*offsets = dummy_ipv6_gtpu_ipv6_udp_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_IPV6_GTPU_IPV6_TCP ||
tun_type == ICE_SW_TUN_IPV6_GTPU_EH_IPV6_TCP) {
*pkt = dummy_ipv6_gtpu_ipv6_tcp_packet;
*pkt_len = sizeof(dummy_ipv6_gtpu_ipv6_tcp_packet);
*offsets = dummy_ipv6_gtpu_ipv6_tcp_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_PPPOE && outer_ipv6) {
*pkt = dummy_pppoe_ipv6_packet;
*pkt_len = sizeof(dummy_pppoe_ipv6_packet);
*offsets = dummy_pppoe_packet_offsets;
return;
} else if (tun_type == ICE_SW_TUN_PPPOE ||
tun_type == ICE_SW_TUN_PPPOE_PAY) {
*pkt = dummy_pppoe_ipv4_packet;
*pkt_len = sizeof(dummy_pppoe_ipv4_packet);
*offsets = dummy_pppoe_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_PPPOE_IPV4) {
*pkt = dummy_pppoe_ipv4_packet;
*pkt_len = sizeof(dummy_pppoe_ipv4_packet);
*offsets = dummy_pppoe_packet_ipv4_offsets;
return;
}
if (tun_type == ICE_SW_TUN_PPPOE_IPV4_TCP) {
*pkt = dummy_pppoe_ipv4_tcp_packet;
*pkt_len = sizeof(dummy_pppoe_ipv4_tcp_packet);
*offsets = dummy_pppoe_ipv4_tcp_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_PPPOE_IPV4_UDP) {
*pkt = dummy_pppoe_ipv4_udp_packet;
*pkt_len = sizeof(dummy_pppoe_ipv4_udp_packet);
*offsets = dummy_pppoe_ipv4_udp_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_PPPOE_IPV6) {
*pkt = dummy_pppoe_ipv6_packet;
*pkt_len = sizeof(dummy_pppoe_ipv6_packet);
*offsets = dummy_pppoe_packet_ipv6_offsets;
return;
}
if (tun_type == ICE_SW_TUN_PPPOE_IPV6_TCP) {
*pkt = dummy_pppoe_ipv6_tcp_packet;
*pkt_len = sizeof(dummy_pppoe_ipv6_tcp_packet);
*offsets = dummy_pppoe_ipv6_tcp_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_PPPOE_IPV6_UDP) {
*pkt = dummy_pppoe_ipv6_udp_packet;
*pkt_len = sizeof(dummy_pppoe_ipv6_udp_packet);
*offsets = dummy_pppoe_ipv6_udp_packet_offsets;
return;
}
if (tun_type == ICE_ALL_TUNNELS) {
*pkt = dummy_gre_udp_packet;
*pkt_len = sizeof(dummy_gre_udp_packet);
*offsets = dummy_gre_udp_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_NVGRE || gre) {
if (tcp && inner_ipv6) {
*pkt = dummy_gre_ipv6_tcp_packet;
*pkt_len = sizeof(dummy_gre_ipv6_tcp_packet);
*offsets = dummy_gre_ipv6_tcp_packet_offsets;
return;
}
if (tcp) {
*pkt = dummy_gre_tcp_packet;
*pkt_len = sizeof(dummy_gre_tcp_packet);
*offsets = dummy_gre_tcp_packet_offsets;
return;
}
if (inner_ipv6) {
*pkt = dummy_gre_ipv6_udp_packet;
*pkt_len = sizeof(dummy_gre_ipv6_udp_packet);
*offsets = dummy_gre_ipv6_udp_packet_offsets;
return;
}
*pkt = dummy_gre_udp_packet;
*pkt_len = sizeof(dummy_gre_udp_packet);
*offsets = dummy_gre_udp_packet_offsets;
return;
}
if (tun_type == ICE_SW_TUN_VXLAN || tun_type == ICE_SW_TUN_GENEVE ||
tun_type == ICE_SW_TUN_VXLAN_GPE || tun_type == ICE_SW_TUN_UDP ||
tun_type == ICE_SW_TUN_GENEVE_VLAN ||
tun_type == ICE_SW_TUN_VXLAN_VLAN) {
if (tcp && inner_ipv6) {
*pkt = dummy_udp_tun_ipv6_tcp_packet;
*pkt_len = sizeof(dummy_udp_tun_ipv6_tcp_packet);
*offsets = dummy_udp_tun_ipv6_tcp_packet_offsets;
return;
}
if (tcp) {
*pkt = dummy_udp_tun_tcp_packet;
*pkt_len = sizeof(dummy_udp_tun_tcp_packet);
*offsets = dummy_udp_tun_tcp_packet_offsets;
return;
}
if (inner_ipv6) {
*pkt = dummy_udp_tun_ipv6_udp_packet;
*pkt_len = sizeof(dummy_udp_tun_ipv6_udp_packet);
*offsets = dummy_udp_tun_ipv6_udp_packet_offsets;
return;
}
*pkt = dummy_udp_tun_udp_packet;
*pkt_len = sizeof(dummy_udp_tun_udp_packet);
*offsets = dummy_udp_tun_udp_packet_offsets;
return;
}
if (udp && !outer_ipv6) {
if (vlan) {
*pkt = dummy_vlan_udp_packet;
*pkt_len = sizeof(dummy_vlan_udp_packet);
*offsets = dummy_vlan_udp_packet_offsets;
return;
} else if (pppoe) {
*pkt = dummy_pppoe_ipv4_udp_packet;
*pkt_len = sizeof(dummy_pppoe_ipv4_udp_packet);
*offsets = dummy_pppoe_ipv4_udp_packet_offsets;
return;
}
*pkt = dummy_udp_packet;
*pkt_len = sizeof(dummy_udp_packet);
*offsets = dummy_udp_packet_offsets;
return;
} else if (udp && outer_ipv6) {
if (vlan) {
*pkt = dummy_vlan_udp_ipv6_packet;
*pkt_len = sizeof(dummy_vlan_udp_ipv6_packet);
*offsets = dummy_vlan_udp_ipv6_packet_offsets;
return;
} else if (pppoe) {
*pkt = dummy_pppoe_ipv6_udp_packet;
*pkt_len = sizeof(dummy_pppoe_ipv6_udp_packet);
*offsets = dummy_pppoe_ipv6_udp_packet_offsets;
return;
}
*pkt = dummy_udp_ipv6_packet;
*pkt_len = sizeof(dummy_udp_ipv6_packet);
*offsets = dummy_udp_ipv6_packet_offsets;
return;
} else if ((tcp && outer_ipv6) || outer_ipv6) {
if (vlan) {
*pkt = dummy_vlan_tcp_ipv6_packet;
*pkt_len = sizeof(dummy_vlan_tcp_ipv6_packet);
*offsets = dummy_vlan_tcp_ipv6_packet_offsets;
return;
} else if (pppoe) {
*pkt = dummy_pppoe_ipv6_tcp_packet;
*pkt_len = sizeof(dummy_pppoe_ipv6_tcp_packet);
*offsets = dummy_pppoe_ipv6_tcp_packet_offsets;
return;
}
*pkt = dummy_tcp_ipv6_packet;
*pkt_len = sizeof(dummy_tcp_ipv6_packet);
*offsets = dummy_tcp_ipv6_packet_offsets;
return;
}
if (vlan) {
*pkt = dummy_vlan_tcp_packet;
*pkt_len = sizeof(dummy_vlan_tcp_packet);
*offsets = dummy_vlan_tcp_packet_offsets;
} else if (pppoe) {
*pkt = dummy_pppoe_ipv4_tcp_packet;
*pkt_len = sizeof(dummy_pppoe_ipv4_tcp_packet);
*offsets = dummy_pppoe_ipv4_tcp_packet_offsets;
return;
} else if (mpls) {
*pkt = dummy_mpls_packet;
*pkt_len = sizeof(dummy_mpls_packet);
*offsets = dummy_mpls_packet_offsets;
} else {
*pkt = dummy_tcp_packet;
*pkt_len = sizeof(dummy_tcp_packet);
*offsets = dummy_tcp_packet_offsets;
}
}
/**
* ice_fill_adv_dummy_packet - fill a dummy packet with given match criteria
*
* @lkups: lookup elements or match criteria for the advanced recipe, one
* structure per protocol header
* @lkups_cnt: number of protocols
* @s_rule: stores rule information from the match criteria
* @dummy_pkt: dummy packet to fill according to filter match criteria
* @pkt_len: packet length of dummy packet
* @offsets: offset info for the dummy packet
*/
int
ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
struct ice_sw_rule_lkup_rx_tx *s_rule,
const u8 *dummy_pkt, u16 pkt_len,
const struct ice_dummy_pkt_offsets *offsets)
{
u8 *pkt;
u16 i;
/* Start with a packet with a pre-defined/dummy content. Then, fill
* in the header values to be looked up or matched.
*/
pkt = s_rule->hdr_data;
ice_memcpy(pkt, dummy_pkt, pkt_len, ICE_NONDMA_TO_NONDMA);
for (i = 0; i < lkups_cnt; i++) {
enum ice_protocol_type type;
u16 offset = 0, len = 0, j;
bool found = false;
/* find the start of this layer; it should be found since this
* was already checked when search for the dummy packet
*/
type = lkups[i].type;
for (j = 0; offsets[j].type != ICE_PROTOCOL_LAST; j++) {
if (type == offsets[j].type) {
offset = offsets[j].offset;
found = true;
break;
}
}
/* this should never happen in a correct calling sequence */
if (!found)
return ICE_ERR_PARAM;
switch (lkups[i].type) {
case ICE_MAC_OFOS:
case ICE_MAC_IL:
len = sizeof(struct ice_ether_hdr);
break;
case ICE_ETYPE_OL:
case ICE_ETYPE_IL:
len = sizeof(struct ice_ethtype_hdr);
break;
case ICE_VLAN_OFOS:
case ICE_VLAN_EX:
case ICE_VLAN_IN:
len = sizeof(struct ice_vlan_hdr);
break;
case ICE_IPV4_OFOS:
case ICE_IPV4_IL:
len = sizeof(struct ice_ipv4_hdr);
break;
case ICE_IPV6_OFOS:
case ICE_IPV6_IL:
len = sizeof(struct ice_ipv6_hdr);
break;
case ICE_TCP_IL:
case ICE_UDP_OF:
case ICE_UDP_ILOS:
len = sizeof(struct ice_l4_hdr);
break;
case ICE_SCTP_IL:
len = sizeof(struct ice_sctp_hdr);
break;
case ICE_NVGRE:
len = sizeof(struct ice_nvgre);
break;
case ICE_VXLAN:
case ICE_GENEVE:
case ICE_VXLAN_GPE:
len = sizeof(struct ice_udp_tnl_hdr);
break;
case ICE_ESP:
len = sizeof(struct ice_esp_hdr);
break;
case ICE_NAT_T:
len = sizeof(struct ice_nat_t_hdr);
break;
case ICE_AH:
len = sizeof(struct ice_ah_hdr);
break;
case ICE_GTP_NO_PAY:
case ICE_GTP:
len = sizeof(struct ice_udp_gtp_hdr);
break;
case ICE_PPPOE:
len = sizeof(struct ice_pppoe_hdr);
break;
case ICE_L2TPV3:
len = sizeof(struct ice_l2tpv3_sess_hdr);
break;
default:
return ICE_ERR_PARAM;
}
/* the length should be a word multiple */
if (len % ICE_BYTES_PER_WORD)
return ICE_ERR_CFG;
/* We have the offset to the header start, the length, the
* caller's header values and mask. Use this information to
* copy the data into the dummy packet appropriately based on
* the mask. Note that we need to only write the bits as
* indicated by the mask to make sure we don't improperly write
* over any significant packet data.
*/
for (j = 0; j < len / sizeof(u16); j++)
if (((u16 *)&lkups[i].m_u)[j])
((u16 *)(pkt + offset))[j] =
(((u16 *)(pkt + offset))[j] &
~((u16 *)&lkups[i].m_u)[j]) |
(((u16 *)&lkups[i].h_u)[j] &
((u16 *)&lkups[i].m_u)[j]);
}
s_rule->hdr_len = CPU_TO_LE16(pkt_len);
return 0;
}
/**
* ice_fill_adv_packet_tun - fill dummy packet with udp tunnel port
* @hw: pointer to the hardware structure
* @tun_type: tunnel type
* @pkt: dummy packet to fill in
* @offsets: offset info for the dummy packet
*/
static int
ice_fill_adv_packet_tun(struct ice_hw *hw, enum ice_sw_tunnel_type tun_type,
u8 *pkt, const struct ice_dummy_pkt_offsets *offsets)
{
u16 open_port, i;
switch (tun_type) {
case ICE_SW_TUN_AND_NON_TUN:
case ICE_SW_TUN_VXLAN_GPE:
case ICE_SW_TUN_VXLAN:
case ICE_SW_TUN_VXLAN_VLAN:
case ICE_SW_TUN_UDP:
if (!ice_get_open_tunnel_port(hw, TNL_VXLAN, &open_port))
return ICE_ERR_CFG;
break;
case ICE_SW_TUN_GENEVE:
case ICE_SW_TUN_GENEVE_VLAN:
if (!ice_get_open_tunnel_port(hw, TNL_GENEVE, &open_port))
return ICE_ERR_CFG;
break;
default:
/* Nothing needs to be done for this tunnel type */
return 0;
}
/* Find the outer UDP protocol header and insert the port number */
for (i = 0; offsets[i].type != ICE_PROTOCOL_LAST; i++) {
if (offsets[i].type == ICE_UDP_OF) {
struct ice_l4_hdr *hdr;
u16 offset;
offset = offsets[i].offset;
hdr = (struct ice_l4_hdr *)&pkt[offset];
hdr->dst_port = CPU_TO_BE16(open_port);
return 0;
}
}
return ICE_ERR_CFG;
}
/**
* ice_fill_adv_packet_vlan - fill dummy packet with VLAN tag type
* @vlan_type: VLAN tag type
* @pkt: dummy packet to fill in
* @offsets: offset info for the dummy packet
*/
static int
ice_fill_adv_packet_vlan(u16 vlan_type, u8 *pkt,
const struct ice_dummy_pkt_offsets *offsets)
{
u16 i;
/* Find VLAN header and insert VLAN TPID */
for (i = 0; offsets[i].type != ICE_PROTOCOL_LAST; i++) {
if (offsets[i].type == ICE_VLAN_OFOS ||
offsets[i].type == ICE_VLAN_EX) {
struct ice_vlan_hdr *hdr;
u16 offset;
offset = offsets[i].offset;
hdr = (struct ice_vlan_hdr *)&pkt[offset];
hdr->type = CPU_TO_BE16(vlan_type);
return 0;
}
}
return ICE_ERR_CFG;
}
/**
* ice_find_adv_rule_entry - Search a rule entry
* @hw: pointer to the hardware structure
* @lkups: lookup elements or match criteria for the advanced recipe, one
* structure per protocol header
* @lkups_cnt: number of protocols
* @recp_id: recipe ID for which we are finding the rule
* @rinfo: other information regarding the rule e.g. priority and action info
*
* Helper function to search for a given advance rule entry
* Returns pointer to entry storing the rule if found
*/
struct ice_adv_fltr_mgmt_list_entry *
ice_find_adv_rule_entry(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
u16 lkups_cnt, u16 recp_id,
struct ice_adv_rule_info *rinfo)
{
struct ice_adv_fltr_mgmt_list_entry *list_itr;
struct ice_switch_info *sw = hw->switch_info;
int i;
LIST_FOR_EACH_ENTRY(list_itr, &sw->recp_list[recp_id].filt_rules,
ice_adv_fltr_mgmt_list_entry, list_entry) {
bool lkups_matched = true;
if (lkups_cnt != list_itr->lkups_cnt)
continue;
for (i = 0; i < list_itr->lkups_cnt; i++)
if (memcmp(&list_itr->lkups[i], &lkups[i],
sizeof(*lkups))) {
lkups_matched = false;
break;
}
if (rinfo->sw_act.flag == list_itr->rule_info.sw_act.flag &&
rinfo->tun_type == list_itr->rule_info.tun_type &&
rinfo->vlan_type == list_itr->rule_info.vlan_type &&
lkups_matched)
return list_itr;
}
return NULL;
}
/**
* ice_adv_add_update_vsi_list
* @hw: pointer to the hardware structure
* @m_entry: pointer to current adv filter management list entry
* @cur_fltr: filter information from the book keeping entry
* @new_fltr: filter information with the new VSI to be added
*
* Call AQ command to add or update previously created VSI list with new VSI.
*
* Helper function to do book keeping associated with adding filter information
* The algorithm to do the booking keeping is described below :
* When a VSI needs to subscribe to a given advanced filter
* if only one VSI has been added till now
* Allocate a new VSI list and add two VSIs
* to this list using switch rule command
* Update the previously created switch rule with the
* newly created VSI list ID
* if a VSI list was previously created
* Add the new VSI to the previously created VSI list set
* using the update switch rule command
*/
int
ice_adv_add_update_vsi_list(struct ice_hw *hw,
struct ice_adv_fltr_mgmt_list_entry *m_entry,
struct ice_adv_rule_info *cur_fltr,
struct ice_adv_rule_info *new_fltr)
{
u16 vsi_list_id = 0;
int status;
if (cur_fltr->sw_act.fltr_act == ICE_FWD_TO_Q ||
cur_fltr->sw_act.fltr_act == ICE_FWD_TO_QGRP ||
cur_fltr->sw_act.fltr_act == ICE_DROP_PACKET)
return ICE_ERR_NOT_IMPL;
if ((new_fltr->sw_act.fltr_act == ICE_FWD_TO_Q ||
new_fltr->sw_act.fltr_act == ICE_FWD_TO_QGRP) &&
(cur_fltr->sw_act.fltr_act == ICE_FWD_TO_VSI ||
cur_fltr->sw_act.fltr_act == ICE_FWD_TO_VSI_LIST))
return ICE_ERR_NOT_IMPL;
if (m_entry->vsi_count < 2 && !m_entry->vsi_list_info) {
/* Only one entry existed in the mapping and it was not already
* a part of a VSI list. So, create a VSI list with the old and
* new VSIs.
*/
struct ice_fltr_info tmp_fltr;
u16 vsi_handle_arr[2];
/* A rule already exists with the new VSI being added */
if (cur_fltr->sw_act.fwd_id.hw_vsi_id ==
new_fltr->sw_act.fwd_id.hw_vsi_id)
return ICE_ERR_ALREADY_EXISTS;
vsi_handle_arr[0] = cur_fltr->sw_act.vsi_handle;
vsi_handle_arr[1] = new_fltr->sw_act.vsi_handle;
status = ice_create_vsi_list_rule(hw, &vsi_handle_arr[0], 2,
&vsi_list_id,
ICE_SW_LKUP_LAST);
if (status)
return status;
ice_memset(&tmp_fltr, 0, sizeof(tmp_fltr), ICE_NONDMA_MEM);
tmp_fltr.flag = m_entry->rule_info.sw_act.flag;
tmp_fltr.fltr_rule_id = cur_fltr->fltr_rule_id;
tmp_fltr.fltr_act = ICE_FWD_TO_VSI_LIST;
tmp_fltr.fwd_id.vsi_list_id = vsi_list_id;
tmp_fltr.lkup_type = ICE_SW_LKUP_LAST;
/* Update the previous switch rule of "forward to VSI" to
* "fwd to VSI list"
*/
status = ice_update_pkt_fwd_rule(hw, &tmp_fltr);
if (status)
return status;
cur_fltr->sw_act.fwd_id.vsi_list_id = vsi_list_id;
cur_fltr->sw_act.fltr_act = ICE_FWD_TO_VSI_LIST;
m_entry->vsi_list_info =
ice_create_vsi_list_map(hw, &vsi_handle_arr[0], 2,
vsi_list_id);
} else {
u16 vsi_handle = new_fltr->sw_act.vsi_handle;
if (!m_entry->vsi_list_info)
return ICE_ERR_CFG;
/* A rule already exists with the new VSI being added */
if (ice_is_bit_set(m_entry->vsi_list_info->vsi_map, vsi_handle))
return ICE_ERR_ALREADY_EXISTS;
/* Update the previously created VSI list set with
* the new VSI ID passed in
*/
vsi_list_id = cur_fltr->sw_act.fwd_id.vsi_list_id;
status = ice_update_vsi_list_rule(hw, &vsi_handle, 1,
vsi_list_id, false,
ice_aqc_opc_update_sw_rules,
ICE_SW_LKUP_LAST);
/* update VSI list mapping info with new VSI ID */
if (!status)
ice_set_bit(vsi_handle,
m_entry->vsi_list_info->vsi_map);
}
if (!status)
m_entry->vsi_count++;
return status;
}
/**
* ice_set_lg_action_entry
* @act_type: large action type is defined in struct ice_sw_rule_lg_act
* @lg_act_entry: large action entry content
*
* Helper function to set large action entry. Each entry represents a single
* action and up to 4 actions can be chained.
*/
static u32
ice_set_lg_action_entry(u8 act_type, union lg_act_entry *lg_entry)
{
u32 act = act_type;
switch (act_type) {
case ICE_LG_ACT_VSI_FORWARDING:
act |= ICE_LG_ACT_VALID_BIT;
act |= (lg_entry->vsi_fwd.vsi_list <<
ICE_LG_ACT_VSI_LIST_ID_S) &
ICE_LG_ACT_VSI_LIST_ID_M;
break;
case ICE_LG_ACT_TO_Q:
act |= ICE_LG_ACT_Q_PRIORITY_SET;
act |= (lg_entry->to_q.q_idx << ICE_LG_ACT_Q_INDEX_S) &
ICE_LG_ACT_Q_INDEX_M;
act |= (lg_entry->to_q.q_region_sz << ICE_LG_ACT_Q_REGION_S) &
ICE_LG_ACT_Q_REGION_M;
act |= (lg_entry->to_q.q_pri << ICE_LG_ACT_Q_REGION_S) &
ICE_LG_ACT_Q_REGION_M;
break;
case ICE_LG_ACT_PRUNE:
act |= (lg_entry->prune.vsi_list << ICE_LG_ACT_VSI_LIST_ID_S) &
ICE_LG_ACT_VSI_LIST_ID_M;
if (lg_entry->prune.egr)
act |= ICE_LG_ACT_EGRESS;
if (lg_entry->prune.ing)
act |= ICE_LG_ACT_INGRESS;
if (lg_entry->prune.prune_t)
act |= ICE_LG_ACT_PRUNET;
break;
case ICE_LG_OTHER_ACT_MIRROR:
act |= (lg_entry->mirror.mirror_vsi <<
ICE_LG_ACT_MIRROR_VSI_ID_S) &
ICE_LG_ACT_MIRROR_VSI_ID_M;
break;
case ICE_LG_ACT_GENERIC:
act |= (lg_entry->generic_act.generic_value <<
ICE_LG_ACT_GENERIC_VALUE_S) &
ICE_LG_ACT_GENERIC_VALUE_M;
act |= (lg_entry->generic_act.offset <<
ICE_LG_ACT_GENERIC_OFFSET_S) &
ICE_LG_ACT_GENERIC_OFFSET_M;
act |= (lg_entry->generic_act.priority <<
ICE_LG_ACT_GENERIC_PRIORITY_S) &
ICE_LG_ACT_GENERIC_PRIORITY_M;
break;
case ICE_LG_ACT_STAT_COUNT:
act |= (lg_entry->statistics.counter_idx <<
ICE_LG_ACT_STAT_COUNT_S) &
ICE_LG_ACT_STAT_COUNT_M;
break;
}
return act;
}
/**
* ice_fill_sw_marker_lg_act
* @hw: pointer to the hardware structure
* @sw_marker: sw marker to tag the Rx descriptor with
* @l_id: large action resource ID
* @lkup_rule_sz: lookup rule size
* @lg_act_size: large action rule size
* @num_lg_acts: number of actions to hold with a large action entry
* @s_rule: switch lookup rule structure
*
* Fill a large action to hold software marker and link the lookup rule
* with an action pointing to this larger action
*/
static struct ice_sw_rule_lg_act *
ice_fill_sw_marker_lg_act(struct ice_hw *hw, u32 sw_marker, u16 l_id,
u16 lkup_rule_sz, u16 lg_act_size, u16 num_lg_acts,
struct ice_sw_rule_lkup_rx_tx *s_rule)
{
struct ice_sw_rule_lkup_rx_tx *rx_tx;
const u16 offset_generic_md_word_0 = 0;
const u16 offset_generic_md_word_1 = 1;
struct ice_sw_rule_lg_act *lg_act;
union lg_act_entry lg_e_lo;
union lg_act_entry lg_e_hi;
const u8 priority = 0x3;
u16 rules_size;
u32 act;
/* For software marker we need 2 large actions for 32 bit mark id */
rules_size = lg_act_size + lkup_rule_sz;
lg_act = (struct ice_sw_rule_lg_act *)ice_malloc(hw, rules_size);
if (!lg_act)
return NULL;
rx_tx = (struct ice_sw_rule_lkup_rx_tx *)((u8 *)lg_act + lg_act_size);
ice_memcpy(rx_tx, s_rule, lkup_rule_sz, ICE_NONDMA_TO_NONDMA);
ice_free(hw, s_rule);
s_rule = NULL;
lg_act->hdr.type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT);
lg_act->index = CPU_TO_LE16(l_id);
lg_act->size = CPU_TO_LE16(num_lg_acts);
/* GENERIC VALUE action to hold the software marker ID low 16 bits */
/* and set in meta data index 4 by default. */
lg_e_lo.generic_act.generic_value = (u16)(sw_marker & 0xFFFF);
lg_e_lo.generic_act.offset = offset_generic_md_word_0;
lg_e_lo.generic_act.priority = priority;
act = ice_set_lg_action_entry(ICE_LG_ACT_GENERIC, &lg_e_lo);
lg_act->act[0] = CPU_TO_LE32(act);
if (num_lg_acts == 1)
return lg_act;
/* This is a 32 bits marker id, chain a new entry to set higher 16 bits
* and set in meta data index 5 by default.
*/
lg_e_hi.generic_act.generic_value = (u16)((sw_marker >> 16) & 0xFFFF);
lg_e_hi.generic_act.offset = offset_generic_md_word_1;
lg_e_hi.generic_act.priority = priority;
act = ice_set_lg_action_entry(ICE_LG_ACT_GENERIC, &lg_e_hi);
lg_act->act[1] = CPU_TO_LE32(act);
return lg_act;
}
/**
* ice_add_adv_rule - helper function to create an advanced switch rule
* @hw: pointer to the hardware structure
* @lkups: information on the words that needs to be looked up. All words
* together makes one recipe
* @lkups_cnt: num of entries in the lkups array
* @rinfo: other information related to the rule that needs to be programmed
* @added_entry: this will return recipe_id, rule_id and vsi_handle. should be
* ignored is case of error.
*
* This function can program only 1 rule at a time. The lkups is used to
* describe the all the words that forms the "lookup" portion of the recipe.
* These words can span multiple protocols. Callers to this function need to
* pass in a list of protocol headers with lookup information along and mask
* that determines which words are valid from the given protocol header.
* rinfo describes other information related to this rule such as forwarding
* IDs, priority of this rule, etc.
*/
int
ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
u16 lkups_cnt, struct ice_adv_rule_info *rinfo,
struct ice_rule_query_data *added_entry)
{
struct ice_adv_fltr_mgmt_list_entry *m_entry, *adv_fltr = NULL;
u16 lg_act_sz, lg_act_id = ICE_INVAL_LG_ACT_INDEX;
u16 rid = 0, i, pkt_len, rule_buf_sz, vsi_handle;
const struct ice_dummy_pkt_offsets *pkt_offsets;
struct ice_sw_rule_lg_act *lg_rule = NULL;
struct ice_sw_rule_lkup_rx_tx *s_rule = NULL;
struct ice_sw_rule_lkup_rx_tx *rx_tx;
struct LIST_HEAD_TYPE *rule_head;
struct ice_switch_info *sw;
u16 nb_lg_acts_mark = 1;
const u8 *pkt = NULL;
u8 num_rules = 1;
bool prof_rule;
u16 word_cnt;
u32 act = 0;
int status;
u8 q_rgn;
/* Initialize profile to result index bitmap */
if (!hw->switch_info->prof_res_bm_init) {
hw->switch_info->prof_res_bm_init = 1;
ice_init_prof_result_bm(hw);
}
prof_rule = ice_is_prof_rule(rinfo->tun_type);
if (!prof_rule && !lkups_cnt)
return ICE_ERR_PARAM;
/* get # of words we need to match */
word_cnt = 0;
for (i = 0; i < lkups_cnt; i++) {
u16 j, *ptr;
ptr = (u16 *)&lkups[i].m_u;
for (j = 0; j < sizeof(lkups->m_u) / sizeof(u16); j++)
if (ptr[j] != 0)
word_cnt++;
}
if (prof_rule) {
if (word_cnt > ICE_MAX_CHAIN_WORDS)
return ICE_ERR_PARAM;
} else {
if (!word_cnt || word_cnt > ICE_MAX_CHAIN_WORDS)
return ICE_ERR_PARAM;
}
/* make sure that we can locate a dummy packet */
ice_find_dummy_packet(lkups, lkups_cnt, rinfo->tun_type, &pkt, &pkt_len,
&pkt_offsets);
if (!pkt) {
status = ICE_ERR_PARAM;
goto err_ice_add_adv_rule;
}
if (!(rinfo->sw_act.fltr_act == ICE_FWD_TO_VSI ||
rinfo->sw_act.fltr_act == ICE_FWD_TO_Q ||
rinfo->sw_act.fltr_act == ICE_FWD_TO_QGRP ||
rinfo->sw_act.fltr_act == ICE_SET_MARK ||
rinfo->sw_act.fltr_act == ICE_DROP_PACKET))
return ICE_ERR_CFG;
vsi_handle = rinfo->sw_act.vsi_handle;
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
if (rinfo->sw_act.fltr_act == ICE_FWD_TO_VSI)
rinfo->sw_act.fwd_id.hw_vsi_id =
ice_get_hw_vsi_num(hw, vsi_handle);
if (rinfo->sw_act.flag & ICE_FLTR_TX)
rinfo->sw_act.src = ice_get_hw_vsi_num(hw, vsi_handle);
status = ice_add_adv_recipe(hw, lkups, lkups_cnt, rinfo, &rid);
if (status)
return status;
m_entry = ice_find_adv_rule_entry(hw, lkups, lkups_cnt, rid, rinfo);
if (m_entry) {
/* we have to add VSI to VSI_LIST and increment vsi_count.
* Also Update VSI list so that we can change forwarding rule
* if the rule already exists, we will check if it exists with
* same vsi_id, if not then add it to the VSI list if it already
* exists if not then create a VSI list and add the existing VSI
* ID and the new VSI ID to the list
* We will add that VSI to the list
*/
status = ice_adv_add_update_vsi_list(hw, m_entry,
&m_entry->rule_info,
rinfo);
if (added_entry) {
added_entry->rid = rid;
added_entry->rule_id = m_entry->rule_info.fltr_rule_id;
added_entry->vsi_handle = rinfo->sw_act.vsi_handle;
}
return status;
}
rule_buf_sz = ice_struct_size(s_rule, hdr_data, 0) + pkt_len;
s_rule = (struct ice_sw_rule_lkup_rx_tx *)ice_malloc(hw, rule_buf_sz);
if (!s_rule)
return ICE_ERR_NO_MEMORY;
if (!rinfo->flags_info.act_valid)
act |= ICE_SINGLE_ACT_LAN_ENABLE;
else
act |= rinfo->flags_info.act & (ICE_SINGLE_ACT_LAN_ENABLE |
ICE_SINGLE_ACT_LB_ENABLE);
switch (rinfo->sw_act.fltr_act) {
case ICE_FWD_TO_VSI:
act |= (rinfo->sw_act.fwd_id.hw_vsi_id <<
ICE_SINGLE_ACT_VSI_ID_S) & ICE_SINGLE_ACT_VSI_ID_M;
act |= ICE_SINGLE_ACT_VSI_FORWARDING | ICE_SINGLE_ACT_VALID_BIT;
break;
case ICE_FWD_TO_Q:
act |= ICE_SINGLE_ACT_TO_Q;
act |= (rinfo->sw_act.fwd_id.q_id << ICE_SINGLE_ACT_Q_INDEX_S) &
ICE_SINGLE_ACT_Q_INDEX_M;
break;
case ICE_FWD_TO_QGRP:
q_rgn = rinfo->sw_act.qgrp_size > 0 ?
(u8)ice_ilog2(rinfo->sw_act.qgrp_size) : 0;
act |= ICE_SINGLE_ACT_TO_Q;
act |= (rinfo->sw_act.fwd_id.q_id << ICE_SINGLE_ACT_Q_INDEX_S) &
ICE_SINGLE_ACT_Q_INDEX_M;
act |= (q_rgn << ICE_SINGLE_ACT_Q_REGION_S) &
ICE_SINGLE_ACT_Q_REGION_M;
break;
case ICE_SET_MARK:
if (rinfo->sw_act.markid > 0xFFFF)
nb_lg_acts_mark += 1;
/* Allocate a hardware table entry to hold large act. */
status = ice_alloc_res_lg_act(hw, &lg_act_id, nb_lg_acts_mark);
if (status || lg_act_id == ICE_INVAL_LG_ACT_INDEX)
return ICE_ERR_NO_MEMORY;
act = ICE_SINGLE_ACT_PTR;
act |= (lg_act_id << ICE_SINGLE_ACT_PTR_VAL_S) &
ICE_SINGLE_ACT_PTR_VAL_M;
act |= ICE_SINGLE_ACT_PTR_BIT;
break;
case ICE_DROP_PACKET:
act |= ICE_SINGLE_ACT_VSI_FORWARDING | ICE_SINGLE_ACT_DROP |
ICE_SINGLE_ACT_VALID_BIT;
break;
default:
status = ICE_ERR_CFG;
goto err_ice_add_adv_rule;
}
/* Set the rule LOOKUP type based on caller specified 'Rx'
* instead of hardcoding it to be either LOOKUP_TX/RX
*
* for 'Rx' set the source to be the port number
* for 'Tx' set the source to be the source HW VSI number (determined
* by caller)
*/
if (rinfo->rx) {
s_rule->hdr.type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_RX);
s_rule->src = CPU_TO_LE16(hw->port_info->lport);
} else {
s_rule->hdr.type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_TX);
s_rule->src = CPU_TO_LE16(rinfo->sw_act.src);
}
s_rule->recipe_id = CPU_TO_LE16(rid);
s_rule->act = CPU_TO_LE32(act);
status = ice_fill_adv_dummy_packet(lkups, lkups_cnt, s_rule, pkt,
pkt_len, pkt_offsets);
if (status)
goto err_ice_add_adv_rule;
if (rinfo->tun_type != ICE_NON_TUN &&
rinfo->tun_type != ICE_SW_TUN_AND_NON_TUN) {
status = ice_fill_adv_packet_tun(hw, rinfo->tun_type,
s_rule->hdr_data,
pkt_offsets);
if (status)
goto err_ice_add_adv_rule;
}
if (rinfo->vlan_type != 0 && ice_is_dvm_ena(hw)) {
status = ice_fill_adv_packet_vlan(rinfo->vlan_type,
s_rule->hdr_data,
pkt_offsets);
if (status)
goto err_ice_add_adv_rule;
}
rx_tx = s_rule;
if (rinfo->sw_act.fltr_act == ICE_SET_MARK) {
lg_act_sz = (u16)ice_struct_size(lg_rule, act, nb_lg_acts_mark);
lg_rule = ice_fill_sw_marker_lg_act(hw, rinfo->sw_act.markid,
lg_act_id, rule_buf_sz,
lg_act_sz, nb_lg_acts_mark,
s_rule);
if (!lg_rule)
goto err_ice_add_adv_rule;
s_rule = (struct ice_sw_rule_lkup_rx_tx *)lg_rule;
rule_buf_sz += lg_act_sz;
num_rules += 1;
rx_tx = (struct ice_sw_rule_lkup_rx_tx *)
((u8 *)s_rule + lg_act_sz);
}
status = ice_aq_sw_rules(hw, (struct ice_aqc_sw_rules *)s_rule,
rule_buf_sz, num_rules,
ice_aqc_opc_add_sw_rules, NULL);
if (status)
goto err_ice_add_adv_rule;
adv_fltr = (struct ice_adv_fltr_mgmt_list_entry *)
ice_malloc(hw, sizeof(struct ice_adv_fltr_mgmt_list_entry));
if (!adv_fltr) {
status = ICE_ERR_NO_MEMORY;
goto err_ice_add_adv_rule;
}
if (lkups_cnt) {
adv_fltr->lkups = (struct ice_adv_lkup_elem *)
ice_memdup(hw, lkups, lkups_cnt * sizeof(*lkups),
ICE_NONDMA_TO_NONDMA);
} else {
adv_fltr->lkups = NULL;
}
if (!adv_fltr->lkups && !prof_rule) {
status = ICE_ERR_NO_MEMORY;
goto err_ice_add_adv_rule;
}
adv_fltr->lkups_cnt = lkups_cnt;
adv_fltr->rule_info = *rinfo;
adv_fltr->rule_info.fltr_rule_id =
LE16_TO_CPU(rx_tx->index);
adv_fltr->rule_info.lg_id = LE16_TO_CPU(lg_act_id);
sw = hw->switch_info;
sw->recp_list[rid].adv_rule = true;
rule_head = &sw->recp_list[rid].filt_rules;
if (rinfo->sw_act.fltr_act == ICE_FWD_TO_VSI)
adv_fltr->vsi_count = 1;
/* Add rule entry to book keeping list */
LIST_ADD(&adv_fltr->list_entry, rule_head);
if (added_entry) {
added_entry->rid = rid;
added_entry->rule_id = adv_fltr->rule_info.fltr_rule_id;
added_entry->vsi_handle = rinfo->sw_act.vsi_handle;
}
err_ice_add_adv_rule:
if (status && rinfo->sw_act.fltr_act == ICE_SET_MARK)
ice_free_sw_marker_lg(hw, lg_act_id, rinfo->sw_act.markid);
if (status && adv_fltr) {
ice_free(hw, adv_fltr->lkups);
ice_free(hw, adv_fltr);
}
ice_free(hw, s_rule);
return status;
}
/**
* ice_adv_rem_update_vsi_list
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle of the VSI to remove
* @fm_list: filter management entry for which the VSI list management needs to
* be done
*/
static int
ice_adv_rem_update_vsi_list(struct ice_hw *hw, u16 vsi_handle,
struct ice_adv_fltr_mgmt_list_entry *fm_list)
{
struct ice_vsi_list_map_info *vsi_list_info;
enum ice_sw_lkup_type lkup_type;
u16 vsi_list_id;
int status;
if (fm_list->rule_info.sw_act.fltr_act != ICE_FWD_TO_VSI_LIST ||
fm_list->vsi_count == 0)
return ICE_ERR_PARAM;
/* A rule with the VSI being removed does not exist */
if (!ice_is_bit_set(fm_list->vsi_list_info->vsi_map, vsi_handle))
return ICE_ERR_DOES_NOT_EXIST;
lkup_type = ICE_SW_LKUP_LAST;
vsi_list_id = fm_list->rule_info.sw_act.fwd_id.vsi_list_id;
status = ice_update_vsi_list_rule(hw, &vsi_handle, 1, vsi_list_id, true,
ice_aqc_opc_update_sw_rules,
lkup_type);
if (status)
return status;
fm_list->vsi_count--;
ice_clear_bit(vsi_handle, fm_list->vsi_list_info->vsi_map);
vsi_list_info = fm_list->vsi_list_info;
if (fm_list->vsi_count == 1) {
struct ice_fltr_info tmp_fltr;
u16 rem_vsi_handle;
rem_vsi_handle = ice_find_first_bit(vsi_list_info->vsi_map,
ICE_MAX_VSI);
if (!ice_is_vsi_valid(hw, rem_vsi_handle))
return ICE_ERR_OUT_OF_RANGE;
/* Make sure VSI list is empty before removing it below */
status = ice_update_vsi_list_rule(hw, &rem_vsi_handle, 1,
vsi_list_id, true,
ice_aqc_opc_update_sw_rules,
lkup_type);
if (status)
return status;
ice_memset(&tmp_fltr, 0, sizeof(tmp_fltr), ICE_NONDMA_MEM);
tmp_fltr.flag = fm_list->rule_info.sw_act.flag;
tmp_fltr.fltr_rule_id = fm_list->rule_info.fltr_rule_id;
fm_list->rule_info.sw_act.fltr_act = ICE_FWD_TO_VSI;
tmp_fltr.fltr_act = ICE_FWD_TO_VSI;
tmp_fltr.fwd_id.hw_vsi_id =
ice_get_hw_vsi_num(hw, rem_vsi_handle);
fm_list->rule_info.sw_act.fwd_id.hw_vsi_id =
ice_get_hw_vsi_num(hw, rem_vsi_handle);
fm_list->rule_info.sw_act.vsi_handle = rem_vsi_handle;
/* Update the previous switch rule of "MAC forward to VSI" to
* "MAC fwd to VSI list"
*/
status = ice_update_pkt_fwd_rule(hw, &tmp_fltr);
if (status) {
ice_debug(hw, ICE_DBG_SW, "Failed to update pkt fwd rule to FWD_TO_VSI on HW VSI %d, error %d\n",
tmp_fltr.fwd_id.hw_vsi_id, status);
return status;
}
fm_list->vsi_list_info->ref_cnt--;
/* Remove the VSI list since it is no longer used */
status = ice_remove_vsi_list_rule(hw, vsi_list_id, lkup_type);
if (status) {
ice_debug(hw, ICE_DBG_SW, "Failed to remove VSI list %d, error %d\n",
vsi_list_id, status);
return status;
}
LIST_DEL(&vsi_list_info->list_entry);
ice_free(hw, vsi_list_info);
fm_list->vsi_list_info = NULL;
}
return status;
}
/**
* ice_rem_adv_rule - removes existing advanced switch rule
* @hw: pointer to the hardware structure
* @lkups: information on the words that needs to be looked up. All words
* together makes one recipe
* @lkups_cnt: num of entries in the lkups array
* @rinfo: Its the pointer to the rule information for the rule
*
* This function can be used to remove 1 rule at a time. The lkups is
* used to describe all the words that forms the "lookup" portion of the
* rule. These words can span multiple protocols. Callers to this function
* need to pass in a list of protocol headers with lookup information along
* and mask that determines which words are valid from the given protocol
* header. rinfo describes other information related to this rule such as
* forwarding IDs, priority of this rule, etc.
*/
int
ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
u16 lkups_cnt, struct ice_adv_rule_info *rinfo)
{
struct ice_adv_fltr_mgmt_list_entry *list_elem;
struct ice_prot_lkup_ext lkup_exts;
bool remove_rule = false;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
u16 i, rid, vsi_handle;
int status = ICE_SUCCESS;
ice_memset(&lkup_exts, 0, sizeof(lkup_exts), ICE_NONDMA_MEM);
for (i = 0; i < lkups_cnt; i++) {
u16 count;
if (lkups[i].type >= ICE_PROTOCOL_LAST)
return ICE_ERR_CFG;
count = ice_fill_valid_words(&lkups[i], &lkup_exts);
if (!count)
return ICE_ERR_CFG;
}
/* Create any special protocol/offset pairs, such as looking at tunnel
* bits by extracting metadata
*/
status = ice_add_special_words(rinfo, &lkup_exts, ice_is_dvm_ena(hw));
if (status)
return status;
rid = ice_find_recp(hw, &lkup_exts, rinfo->tun_type, rinfo->priority);
/* If did not find a recipe that match the existing criteria */
if (rid == ICE_MAX_NUM_RECIPES)
return ICE_ERR_PARAM;
rule_lock = &hw->switch_info->recp_list[rid].filt_rule_lock;
list_elem = ice_find_adv_rule_entry(hw, lkups, lkups_cnt, rid, rinfo);
/* the rule is already removed */
if (!list_elem)
return ICE_SUCCESS;
ice_acquire_lock(rule_lock);
if (list_elem->rule_info.sw_act.fltr_act != ICE_FWD_TO_VSI_LIST) {
remove_rule = true;
} else if (list_elem->vsi_count > 1) {
remove_rule = false;
vsi_handle = rinfo->sw_act.vsi_handle;
status = ice_adv_rem_update_vsi_list(hw, vsi_handle, list_elem);
} else {
vsi_handle = rinfo->sw_act.vsi_handle;
status = ice_adv_rem_update_vsi_list(hw, vsi_handle, list_elem);
if (status) {
ice_release_lock(rule_lock);
return status;
}
if (list_elem->vsi_count == 0)
remove_rule = true;
}
ice_release_lock(rule_lock);
if (remove_rule) {
struct ice_sw_rule_lkup_rx_tx *s_rule;
u16 rule_buf_sz;
if (rinfo->sw_act.fltr_act == ICE_SET_MARK)
ice_free_sw_marker_lg(hw, list_elem->rule_info.lg_id,
rinfo->sw_act.markid);
rule_buf_sz = ice_struct_size(s_rule, hdr_data, 0);
s_rule = (struct ice_sw_rule_lkup_rx_tx *)
ice_malloc(hw, rule_buf_sz);
if (!s_rule)
return ICE_ERR_NO_MEMORY;
s_rule->act = 0;
s_rule->index = CPU_TO_LE16(list_elem->rule_info.fltr_rule_id);
s_rule->hdr_len = 0;
status = ice_aq_sw_rules(hw, s_rule, rule_buf_sz, 1,
ice_aqc_opc_remove_sw_rules, NULL);
if (status == ICE_SUCCESS || status == ICE_ERR_DOES_NOT_EXIST) {
struct ice_switch_info *sw = hw->switch_info;
ice_acquire_lock(rule_lock);
LIST_DEL(&list_elem->list_entry);
ice_free(hw, list_elem->lkups);
ice_free(hw, list_elem);
ice_release_lock(rule_lock);
if (LIST_EMPTY(&sw->recp_list[rid].filt_rules))
sw->recp_list[rid].adv_rule = false;
}
ice_free(hw, s_rule);
}
return status;
}
/**
* ice_rem_adv_rule_by_id - removes existing advanced switch rule by ID
* @hw: pointer to the hardware structure
* @remove_entry: data struct which holds rule_id, VSI handle and recipe ID
*
* This function is used to remove 1 rule at a time. The removal is based on
* the remove_entry parameter. This function will remove rule for a given
* vsi_handle with a given rule_id which is passed as parameter in remove_entry
*/
int
ice_rem_adv_rule_by_id(struct ice_hw *hw,
struct ice_rule_query_data *remove_entry)
{
struct ice_adv_fltr_mgmt_list_entry *list_itr;
struct LIST_HEAD_TYPE *list_head;
struct ice_adv_rule_info rinfo;
struct ice_switch_info *sw;
sw = hw->switch_info;
if (!sw->recp_list[remove_entry->rid].recp_created)
return ICE_ERR_PARAM;
list_head = &sw->recp_list[remove_entry->rid].filt_rules;
LIST_FOR_EACH_ENTRY(list_itr, list_head, ice_adv_fltr_mgmt_list_entry,
list_entry) {
if (list_itr->rule_info.fltr_rule_id ==
remove_entry->rule_id) {
rinfo = list_itr->rule_info;
rinfo.sw_act.vsi_handle = remove_entry->vsi_handle;
return ice_rem_adv_rule(hw, list_itr->lkups,
list_itr->lkups_cnt, &rinfo);
}
}
/* either list is empty or unable to find rule */
return ICE_ERR_DOES_NOT_EXIST;
}
/**
* ice_rem_adv_rule_for_vsi - removes existing advanced switch rules for a
* given VSI handle
* @hw: pointer to the hardware structure
* @vsi_handle: VSI handle for which we are supposed to remove all the rules.
*
* This function is used to remove all the rules for a given VSI and as soon
* as removing a rule fails, it will return immediately with the error code,
* else it will return 0.
*/
int ice_rem_adv_rule_for_vsi(struct ice_hw *hw, u16 vsi_handle)
{
struct ice_adv_fltr_mgmt_list_entry *list_itr, *tmp_entry;
struct ice_vsi_list_map_info *map_info;
struct ice_adv_rule_info rinfo;
struct LIST_HEAD_TYPE *list_head;
struct ice_switch_info *sw;
int status;
u8 rid;
sw = hw->switch_info;
for (rid = 0; rid < ICE_MAX_NUM_RECIPES; rid++) {
if (!sw->recp_list[rid].recp_created)
continue;
if (!sw->recp_list[rid].adv_rule)
continue;
list_head = &sw->recp_list[rid].filt_rules;
LIST_FOR_EACH_ENTRY_SAFE(list_itr, tmp_entry, list_head,
ice_adv_fltr_mgmt_list_entry,
list_entry) {
rinfo = list_itr->rule_info;
if (rinfo.sw_act.fltr_act == ICE_FWD_TO_VSI_LIST) {
map_info = list_itr->vsi_list_info;
if (!map_info)
continue;
if (!ice_is_bit_set(map_info->vsi_map,
vsi_handle))
continue;
} else if (rinfo.sw_act.vsi_handle != vsi_handle) {
continue;
}
rinfo.sw_act.vsi_handle = vsi_handle;
status = ice_rem_adv_rule(hw, list_itr->lkups,
list_itr->lkups_cnt, &rinfo);
if (status)
return status;
}
}
return ICE_SUCCESS;
}
/**
* ice_replay_fltr - Replay all the filters stored by a specific list head
* @hw: pointer to the hardware structure
* @list_head: list for which filters needs to be replayed
* @recp_id: Recipe ID for which rules need to be replayed
*/
static int
ice_replay_fltr(struct ice_hw *hw, u8 recp_id, struct LIST_HEAD_TYPE *list_head)
{
struct ice_fltr_mgmt_list_entry *itr;
struct ice_sw_recipe *recp_list;
u8 lport = hw->port_info->lport;
struct LIST_HEAD_TYPE l_head;
int status = 0;
if (LIST_EMPTY(list_head))
return status;
recp_list = &hw->switch_info->recp_list[recp_id];
/* Move entries from the given list_head to a temporary l_head so that
* they can be replayed. Otherwise when trying to re-add the same
* filter, the function will return already exists
*/
LIST_REPLACE_INIT(list_head, &l_head);
/* Mark the given list_head empty by reinitializing it so filters
* could be added again by *handler
*/
LIST_FOR_EACH_ENTRY(itr, &l_head, ice_fltr_mgmt_list_entry,
list_entry) {
struct ice_fltr_list_entry f_entry;
u16 vsi_handle;
f_entry.fltr_info = itr->fltr_info;
if (itr->vsi_count < 2 && recp_id != ICE_SW_LKUP_VLAN) {
status = ice_add_rule_internal(hw, recp_list, lport,
&f_entry);
if (status)
goto end;
continue;
}
/* Add a filter per VSI separately */
ice_for_each_set_bit(vsi_handle, itr->vsi_list_info->vsi_map,
ICE_MAX_VSI) {
if (!ice_is_vsi_valid(hw, vsi_handle))
break;
ice_clear_bit(vsi_handle, itr->vsi_list_info->vsi_map);
f_entry.fltr_info.vsi_handle = vsi_handle;
f_entry.fltr_info.fwd_id.hw_vsi_id =
ice_get_hw_vsi_num(hw, vsi_handle);
f_entry.fltr_info.fltr_act = ICE_FWD_TO_VSI;
if (recp_id == ICE_SW_LKUP_VLAN)
status = ice_add_vlan_internal(hw, recp_list,
&f_entry);
else
status = ice_add_rule_internal(hw, recp_list,
lport,
&f_entry);
if (status)
goto end;
}
}
end:
/* Clear the filter management list */
ice_rem_sw_rule_info(hw, &l_head);
return status;
}
/**
* ice_replay_all_fltr - replay all filters stored in bookkeeping lists
* @hw: pointer to the hardware structure
*
* NOTE: This function does not clean up partially added filters on error.
* It is up to caller of the function to issue a reset or fail early.
*/
int ice_replay_all_fltr(struct ice_hw *hw)
{
struct ice_switch_info *sw = hw->switch_info;
int status = ICE_SUCCESS;
u8 i;
for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
struct LIST_HEAD_TYPE *head = &sw->recp_list[i].filt_rules;
status = ice_replay_fltr(hw, i, head);
if (status != ICE_SUCCESS)
return status;
}
return status;
}
/**
* ice_replay_vsi_fltr - Replay filters for requested VSI
* @hw: pointer to the hardware structure
* @pi: pointer to port information structure
* @sw: pointer to switch info struct for which function replays filters
* @vsi_handle: driver VSI handle
* @recp_id: Recipe ID for which rules need to be replayed
* @list_head: list for which filters need to be replayed
*
* Replays the filter of recipe recp_id for a VSI represented via vsi_handle.
* It is required to pass valid VSI handle.
*/
static int
ice_replay_vsi_fltr(struct ice_hw *hw, struct ice_port_info *pi,
struct ice_switch_info *sw, u16 vsi_handle, u8 recp_id,
struct LIST_HEAD_TYPE *list_head)
{
struct ice_fltr_mgmt_list_entry *itr;
struct ice_sw_recipe *recp_list;
int status = 0;
u16 hw_vsi_id;
if (LIST_EMPTY(list_head))
return status;
recp_list = &sw->recp_list[recp_id];
hw_vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
LIST_FOR_EACH_ENTRY(itr, list_head, ice_fltr_mgmt_list_entry,
list_entry) {
struct ice_fltr_list_entry f_entry;
f_entry.fltr_info = itr->fltr_info;
if (itr->vsi_count < 2 && recp_id != ICE_SW_LKUP_VLAN &&
itr->fltr_info.vsi_handle == vsi_handle) {
/* update the src in case it is VSI num */
if (f_entry.fltr_info.src_id == ICE_SRC_ID_VSI)
f_entry.fltr_info.src = hw_vsi_id;
status = ice_add_rule_internal(hw, recp_list,
pi->lport,
&f_entry);
if (status)
goto end;
continue;
}
if (!itr->vsi_list_info ||
!ice_is_bit_set(itr->vsi_list_info->vsi_map, vsi_handle))
continue;
f_entry.fltr_info.vsi_handle = vsi_handle;
f_entry.fltr_info.fltr_act = ICE_FWD_TO_VSI;
/* update the src in case it is VSI num */
if (f_entry.fltr_info.src_id == ICE_SRC_ID_VSI)
f_entry.fltr_info.src = hw_vsi_id;
if (recp_id == ICE_SW_LKUP_VLAN)
status = ice_add_vlan_internal(hw, recp_list, &f_entry);
else
status = ice_add_rule_internal(hw, recp_list,
pi->lport,
&f_entry);
if (status)
goto end;
}
end:
return status;
}
/**
* ice_replay_vsi_adv_rule - Replay advanced rule for requested VSI
* @hw: pointer to the hardware structure
* @vsi_handle: driver VSI handle
* @list_head: list for which filters need to be replayed
*
* Replay the advanced rule for the given VSI.
*/
static int
ice_replay_vsi_adv_rule(struct ice_hw *hw, u16 vsi_handle,
struct LIST_HEAD_TYPE *list_head)
{
struct ice_rule_query_data added_entry = { 0 };
struct ice_adv_fltr_mgmt_list_entry *adv_fltr;
int status = 0;
if (LIST_EMPTY(list_head))
return status;
LIST_FOR_EACH_ENTRY(adv_fltr, list_head, ice_adv_fltr_mgmt_list_entry,
list_entry) {
struct ice_adv_rule_info *rinfo = &adv_fltr->rule_info;
u16 lk_cnt = adv_fltr->lkups_cnt;
if (vsi_handle != rinfo->sw_act.vsi_handle)
continue;
status = ice_add_adv_rule(hw, adv_fltr->lkups, lk_cnt, rinfo,
&added_entry);
if (status)
break;
}
return status;
}
/**
* ice_replay_vsi_all_fltr - replay all filters stored in bookkeeping lists
* @hw: pointer to the hardware structure
* @pi: pointer to port information structure
* @vsi_handle: driver VSI handle
*
* Replays filters for requested VSI via vsi_handle.
*/
int
ice_replay_vsi_all_fltr(struct ice_hw *hw, struct ice_port_info *pi,
u16 vsi_handle)
{
struct ice_switch_info *sw = NULL;
int status;
u8 i;
sw = hw->switch_info;
/* Update the recipes that were created */
for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
struct LIST_HEAD_TYPE *head;
head = &sw->recp_list[i].filt_replay_rules;
if (!sw->recp_list[i].adv_rule)
status = ice_replay_vsi_fltr(hw, pi, sw, vsi_handle, i,
head);
else
status = ice_replay_vsi_adv_rule(hw, vsi_handle, head);
if (status)
return status;
}
return 0;
}
/**
* ice_rm_sw_replay_rule_info - helper function to delete filter replay rules
* @hw: pointer to the HW struct
* @sw: pointer to switch info struct for which function removes filters
*
* Deletes the filter replay rules for given switch
*/
void ice_rm_sw_replay_rule_info(struct ice_hw *hw, struct ice_switch_info *sw)
{
u8 i;
if (!sw)
return;
for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
if (!LIST_EMPTY(&sw->recp_list[i].filt_replay_rules)) {
struct LIST_HEAD_TYPE *l_head;
l_head = &sw->recp_list[i].filt_replay_rules;
if (!sw->recp_list[i].adv_rule)
ice_rem_sw_rule_info(hw, l_head);
else
ice_rem_adv_rule_info(hw, l_head);
}
}
}
/**
* ice_rm_all_sw_replay_rule_info - deletes filter replay rules
* @hw: pointer to the HW struct
*
* Deletes the filter replay rules.
*/
void ice_rm_all_sw_replay_rule_info(struct ice_hw *hw)
{
ice_rm_sw_replay_rule_info(hw, hw->switch_info);
}
|