File: types.vhdl

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fauhdlc 20180504-3.1
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-- $Id$ 

-- test a for a type error regarding overloads

-- Copyright (C) 2009 FAUmachine Team <info@faumachine.org>.
-- This program is free software. You can redistribute it and/or modify it
-- under the terms of the GNU General Public License, either version 2 of
-- the License, or (at your option) any later version. See COPYING.

library ieee;
use ieee.std_logic_1164.all;
entity test_bench is
end entity test_bench;

architecture test_bench_impl of test_bench is
	signal s: std_logic;
begin
	p : process
	begin
		s <= '1' xor '0';
		s <= '1' and 0; -- @ERROR@ type error
		s <= s = '1' and s = 0; -- @ERROR type error
	end process;
end architecture test_bench_impl;