File: chip_intel_x86_64_cpuid.c

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/*
 * Copyright (C) 2007-2014 FAUmachine Team <info@faumachine.org>.
 * This program is free software. You can redistribute it and/or modify it
 * under the terms of the GNU General Public License, either version 2 of
 * the License, or (at your option) any later version. See COPYING.
 */

#define FAST

#define XCONC(a, b, c)  a ## _ ## b ## _ ## c
#define CONC(a, b, c)   XCONC(a, b, c)

#include <assert.h>
#include <setjmp.h>
#include <stdio.h>

#include "glue-main.h"
#include "glue-floatx.h"

#include "chip_intel_x86_64_def.h"

#include "arch_gen_cpu_x86_state.h"

void
chip_intel_x86_64_helper_cpuid(struct cpssp *cpssp)
{
	uint32_t index_;

	index_ = (uint32_t) cpssp->regs[R_EAX];
    
	/* test if maximum index reached */
	if (index_ & 0x80000000) {
		if (index_ > 0x80000008) 
			index_ = 6;
	} else {
		if (index_ > 6) 
			index_ = 6;
	}

	switch (index_) {
	case 0x00000000:
		cpssp->regs[R_EAX] = 0x00000006;
		cpssp->regs[R_EBX] = 0x756e6547; /* GenuineIntel */
		cpssp->regs[R_ECX] = 0x6c65746e;
		cpssp->regs[R_EDX] = 0x49656e69;
		break;

	case 0x00000001:
		cpssp->regs[R_EAX] = 0x00000f62; /* CPU Version */
		cpssp->regs[R_EBX] = 0x00020800;
		cpssp->regs[R_ECX] = CONFIG_CPU_SSE3_SUPPORT << 0
			| CONFIG_CPU_MONITOR_SUPPORT << 3
			| CONFIG_CPU_DSCPL_SUPPORT << 4
			| CONFIG_CPU_VMX_SUPPORT << 5
			/* Bit 6 is reserved. */
			| CONFIG_CPU_EST_SUPPORT << 7
			| CONFIG_CPU_TM2_SUPPORT << 8
			| CONFIG_CPU_SSSE3_SUPPORT << 9
			| CONFIG_CPU_CNXTID_SUPPORT << 10
			/* Bit 11 is reserved. */
			/* Bit 12 is reserved. */
			| CONFIG_CPU_CMPXCHG16B_SUPPORT << 13
			| CONFIG_CPU_XTPR_SUPPORT << 14
			| CONFIG_CPU_PDCM_SUPPORT << 15;
		cpssp->regs[R_ECX] &= 0; /* FIXME */

		cpssp->regs[R_EDX] = CONFIG_CPU_FPU_SUPPORT << 0
			| CONFIG_CPU_VME_SUPPORT << 1
			| CONFIG_CPU_DE_SUPPORT << 2
			| CONFIG_CPU_PSE_SUPPORT << 3
			| CONFIG_CPU_TSC_SUPPORT << 4
			| CONFIG_CPU_MSR_SUPPORT << 5
			| CONFIG_CPU_PAE_SUPPORT << 6
			| CONFIG_CPU_MCE_SUPPORT << 7
			| CONFIG_CPU_CX8_SUPPORT << 8
			| CONFIG_CPU_APIC_SUPPORT << 9
			| CONFIG_CPU_SEP_SUPPORT << 11 
			| CONFIG_CPU_MTRR_SUPPORT << 12
			| CONFIG_CPU_PGE_SUPPORT << 13
			| CONFIG_CPU_MCA_SUPPORT << 14
			| CONFIG_CPU_CMOV_SUPPORT << 15
			| CONFIG_CPU_PAT_SUPPORT << 16
			| CONFIG_CPU_PSE36_SUPPORT << 17
			| CONFIG_CPU_PSN_SUPPORT << 18
			| CONFIG_CPU_CFLSH_SUPPORT << 19
			| CONFIG_CPU_DS_SUPPORT << 21
			| CONFIG_CPU_ACPI_SUPPORT << 22
			| CONFIG_CPU_MMX_SUPPORT << 23
			| CONFIG_CPU_FXSR_SUPPORT << 24
			| CONFIG_CPU_SSE_SUPPORT << 25
			| CONFIG_CPU_SSE2_SUPPORT << 26
			| CONFIG_CPU_SS_SUPPORT << 27
			| CONFIG_CPU_HTT_SUPPORT << 28
			| CONFIG_CPU_TM_SUPPORT << 29
			| CONFIG_CPU_PBE_SUPPORT << 31;
		/* FIXME */
#define CPUID_FP87 (1 << 0)
#define CPUID_VME  (1 << 1)
#define CPUID_DE   (1 << 2)
#define CPUID_PSE  (1 << 3)
#define CPUID_TSC  (1 << 4)
#define CPUID_MSR  (1 << 5)
#define CPUID_PAE  (1 << 6)
#define CPUID_MCE  (1 << 7)
#define CPUID_CX8  (1 << 8)
#define CPUID_APIC (1 << 9)
#define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
#define CPUID_MTRR (1 << 12)
#define CPUID_PGE  (1 << 13)
#define CPUID_MCA  (1 << 14)
#define CPUID_CMOV (1 << 15)
#define CPUID_PAT  (1 << 16)
#define CPUID_CLFLUSH (1 << 19)
/* ... */
#define CPUID_MMX  (1 << 23)
#define CPUID_FXSR (1 << 24)
#define CPUID_SSE  (1 << 25)
#define CPUID_SSE2 (1 << 26)
		cpssp->regs[R_EDX] &= CPUID_FP87	/* 0: Floating Point Unit */
			| CPUID_VME	/* 1: VME */
			| CPUID_DE	/* 2: Debugging Extensions */
			| CPUID_PSE	/* 3: Page Size Extensions */
			| CPUID_TSC	/* 4: Time Stamp Counter */
			| CPUID_MSR	/* 5: Model Specific Registers */
			| CPUID_PAE	/* 6: Physical Address Extensions */
			| CPUID_MCE	/* 7: Machine Check Exception */
			| CPUID_CX8	/* 8: Compare and Exchange 8 Byte */
			| CPUID_APIC	/* 9: Advanced PIC */
			/* reserved */
			| CPUID_SEP	/* 11: sysenter/sysleave Instructions */
			| CPUID_MTRR	/* 12: Mem. Type Range Reg. */
			| CPUID_PGE	/* 13: Page Global Bit Extension */
			| CPUID_MCA	/* 14: Machine Check Architecture */
			| CPUID_CMOV	/* 15: Conditional Move */
			| CPUID_PAT	/* 16: Page Attribute Table */
			/* | CPUID_PSE36 */ /* 17: 36bit Page Size Extension */
			/* | CPUID_PSN */
			| CPUID_CLFLUSH	/* 19: clflush Instruction */
			/* | CPUID_DS */
			/* | CPUID_ACPI */
			| CPUID_MMX	/* 23: Multimedia Extension */
			| CPUID_FXSR	/* 24: fxsave/fxrstor Instructions */
			| CPUID_SSE	/* 25: SSE */
			| CPUID_SSE2
			/* | CPUID_SS */
			/* | CPUID_HTT */
			/* | CPUID_TM */
			/* | CPUID_PBE */
			;

		cpssp->update_signature = 0;
		break;

	case 0x00000002:
		cpssp->regs[R_EAX] = (0x60 << 24) /* data L1 cache, 16KB, 8 ways, 64B lines */
		    | (0x5b << 16) /* data TLB, 4K/4M pages, fully, 64 entries */
		    | (0x51 << 8) /* code TLB, 4K/4M/2M pages, fully, 128 entries */
		    | (0x01 << 0); /* call cpuid once */
		cpssp->regs[R_EBX] = 0x00000000;
		cpssp->regs[R_ECX] = 0x00000000;
		cpssp->regs[R_EDX] = (0x00 << 24) /* - */
		    | (0x7d << 16) /* C/D L2 cache, 2MB, 8 ways, 64B entries */
		    | (0x70 << 8) /* trace L1 cache, 12KuOPs, 8 ways */
		    | (0x40 << 0); /* no integrated L3 cache */
		break;

	case 0x00000003:
		cpssp->regs[R_EAX] = 0x00000000;
		cpssp->regs[R_EBX] = 0x00000000;
		cpssp->regs[R_ECX] = 0x00000000;
		cpssp->regs[R_EDX] = 0x00000000;
		break;

	case 0x00000004:
		switch (cpssp->regs[R_ECX]) {
		case 0:
			cpssp->regs[R_EAX] =     0x0121;
			cpssp->regs[R_EBX] = 0x01c0003f;
			cpssp->regs[R_ECX] = 0x0000001f;
			break;
		case 1:
			cpssp->regs[R_EAX] =     0x0143;
			cpssp->regs[R_EBX] = 0x01c0103f;
			cpssp->regs[R_ECX] = 0x000007ff;
			break;
		default:
			cpssp->regs[R_EAX] =     0x0000;
			break;
		}
		cpssp->regs[R_EAX] |= ((1-1) << 26)	/* # Processor Cores */
		     | ((1-1) << 14);	/* # Threads */
		cpssp->regs[R_EDX] = 0x00000000;
		break;

	case 0x00000005:
		cpssp->regs[R_EAX] = 0x00000040;
		cpssp->regs[R_EBX] = 0x00000040;
		cpssp->regs[R_ECX] = 0x00000000;
		cpssp->regs[R_EDX] = 0x00000000;
		break;

	case 0x00000006:
		cpssp->regs[R_EAX] = 0x00000000;
		cpssp->regs[R_EBX] = 0x00000000;
		cpssp->regs[R_ECX] = 0x00000000;
		cpssp->regs[R_EDX] = 0x00000000;
		break;

	case 0x80000000:
		cpssp->regs[R_EAX] = 0x80000008;
		cpssp->regs[R_EBX] = 0x00000000;
		cpssp->regs[R_ECX] = 0x00000000;
		cpssp->regs[R_EDX] = 0x00000000;
		break;

	case 0x80000001:
		cpssp->regs[R_EAX] = 0x00000000;
		cpssp->regs[R_EBX] = 0x00000000;

		cpssp->regs[R_ECX] = CONFIG_CPU_LAHF_SUPPORT << 0;
		/* FIXME */
		cpssp->regs[R_ECX] &= 0;

		cpssp->regs[R_EDX] = CONFIG_CPU_SYSCALL_SUPPORT << 11
			| CONFIG_CPU_NX_SUPPORT << 20
			| CONFIG_CPU_FFXSR_SUPPORT << 25
			| CONFIG_CPU_LM_SUPPORT << 29;
		/* FIXME */
		cpssp->regs[R_EDX] &= CONFIG_CPU_SYSCALL_SUPPORT << 11
			| CONFIG_CPU_NX_SUPPORT << 20
			| CONFIG_CPU_LM_SUPPORT << 29;
		break;

	case 0x80000002:
		cpssp->regs[R_EAX] = 0x20202020;
		cpssp->regs[R_EBX] = 0x20202020;
		cpssp->regs[R_ECX] = 0x20202020;
		cpssp->regs[R_EDX] = 0x6e492020;
		break;

	case 0x80000003:
		cpssp->regs[R_EAX] = 0x286c6574;
		cpssp->regs[R_EBX] = 0x50202952;
		cpssp->regs[R_ECX] = 0x69746e65;
		cpssp->regs[R_EDX] = 0x52286d75;
		break;

	case 0x80000004:
		cpssp->regs[R_EAX] = 0x20442029;
		cpssp->regs[R_EBX] = 0x20555043;
		cpssp->regs[R_ECX] = 0x30342e33;
		cpssp->regs[R_EDX] = 0x007a4847;
		break;

	case 0x80000005:
		cpssp->regs[R_EAX] = 0x00000000;
		cpssp->regs[R_EBX] = 0x00000000;
		cpssp->regs[R_ECX] = 0x00000000;
		cpssp->regs[R_EDX] = 0x00000000;
		break;

	case 0x80000006:
		cpssp->regs[R_EAX] = 0x00000000;
		cpssp->regs[R_EBX] = 0x00000000;
		cpssp->regs[R_ECX] = 0x08006040;
		cpssp->regs[R_EDX] = 0x00000000;
		break;

	case 0x80000007:
		cpssp->regs[R_EAX] = 0x00000000;
		cpssp->regs[R_EBX] = 0x00000000;
		cpssp->regs[R_ECX] = 0x00000000;
		cpssp->regs[R_EDX] = 0x00000000;
		break;

	case 0x80000008:
		cpssp->regs[R_EAX] = (CONFIG_CPU_VIRT_BITS << 8)
			| (CONFIG_CPU_PHYS_BITS << 0);
		cpssp->regs[R_EBX] = 0x00000000;
		cpssp->regs[R_ECX] = 0x00000000;
		cpssp->regs[R_EDX] = 0x00000000;
		break;
	}
}