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--
-- Copyright (C) 2015 FAUmachine Team <info@faumachine.org>.
-- This program is free software. You can redistribute it and/or modify it
-- under the terms of the GNU General Public License, either version 2 of
-- the License, or (at your option) any later version. See COPYING.
--
library expect;
use expect.types.all;
use expect.procedures.all;
library ieee;
use ieee.std_logic_1164.ALL;
entity test_bench is
end test_bench;
architecture structural of test_bench is
signal vdd : std_logic;
signal gnd : std_logic;
signal a0 : std_logic;
signal b0 : std_logic;
signal c0 : std_logic;
signal a1 : std_logic;
signal b1 : std_logic;
signal c1 : std_logic;
signal a2 : std_logic;
signal b2 : std_logic;
signal c2 : std_logic;
signal a3 : std_logic;
signal b3 : std_logic;
signal c3 : std_logic;
begin
comp : chip_gen_7400
port map(
vdd => vdd,
gnd => gnd,
a0 => a0,
b0 => b0,
c0 => c0,
a1 => a1,
b1 => b1,
c1 => c1,
a2 => a2,
b2 => b2,
c2 => c2,
a3 => a3,
b3 => b3,
c3 => c3
);
end structural;
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