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Version 0.0+201212
------------------
Wolfgang Spraul (215):
parse .bit header strings
minor README update
added header and (some) command parsing
first steps
small improvement in frame structure
a little more memory dumping, not satisfied with hacking speed
a little more beauty
giselle
learned a little about the I/O pins
tiny svg steps
shorten the output a little, make it more readable
added some boolean algebra (part I)
finished lut equiv. schematic
css
added quine-mccluskey algo, still open: petrick's method, xor, others?
ramb16 cleanup, going public domain, see unlicense.org
cleaner ramb16 inst
little more ramb16 cleanup. next: two-pass frame handling, better support for compressed bitstreams
incremental commit, some refactoring
committing a bit more frequently because my HDD clicks strangely and replacement only arrives tomorrow...
minor cleanup, bug fixes
finished frame cleanup. tomorrow: back to clb, then other primitives.
initial lut support
minor lut fix
a little DSP support, lots of reading and thinking
ran into a wall with routing drawings, starting a C model of the chip
working on C model
finished top, bottom and center - left and right missing
started modeling left side of chip
finished first round in tile modeling - next back to semiconductor devices and routing
moved model into separate file so multiple utils can use it
added new stub util new_floorplan
added simple hashed string array for tile and wire names
minor model cleanup
modeled first line - NN2
minor README update
another small wire segment modeled
modeling wires, about 0.7% of them done
wires
wires
wires 1.1%
modeling
wires
wires
first steps in logic wires
cleanup, wires, new_fp prints static connections
small sort order fix
some dcm and pll wiring
tile positioning cleanup p1
finished tile positioning cleanup
started with global clock wiring
wires left and right
working
more powerful hashed string array, high-speed search and replace utility hstrrep
added small text utilities hstrrep, sort_seq and merge_seq
cleanup, fixes, some gclk vertical wiring
moving functions around a little
finished gclk
some bram, macc and logic ports
a few more ports
wrote pair2net utility to build nets out of connection pairs
cleanup, some more devices
a little switch infrastructure
better tools, a bit of logicout wiring
a few more devices
NN4
SS4
some work around switches
first steps in logicin routing
finished logicin switches
finished logicout switches
more logicin switching
more switches
more switches
ports
IO connections
more term connections
term pcice connections
broke up the 5000 line model.c into 7 sub-files
gfan, clk, sr, logic carry
IO switches
switches
iologic switches
logic switches
higher-level compiler warnings - thanks to Werner!
planning some libs: model, bits, floorplan, control, test
starting with auto-tester
autotester
very first steps in autotester
Merge branch 'master' of github.com:Wolfgang-Spraul/fpgatools
minor iob work
don't stop me now
autotester
minor cleanup
added bit2fp stub
clarification
make bit2txt output a bit more readable
autotester, iob pinwire fixes
added 2 switch and conn helper functions
autotest stub
logicio switches
merged bit2txt into bit2fp
first steps in fp2bit, header and regs
worked on fp2bit, will breakup bits.c into 2 files next...
broke bits.c into 2 separate files bit_regs.c and bit_frames.c
bit2fp cleanup
working in model, 0.1%
README update with some TODO plans
minor README update
minor README update
minor README update
slow day
some switch work
autotest, minor fixes all over
cleanup
minor routing improvement
tile and x-coord flag cleanup
logic block and logicin ports
a little more routing
enabling a few switches
switches, but hit a dead end, have to work on nets...
pinwire cleanup
pinwire cleanup
minor devidx cleanup, net preparation
some net helper functions
minor floorplan fixes
net cleanup
minor fixes, slow Sunday...
cleanup, fixes, renames/reorg - messy but committed to set base for next steps...
better routing from and to logic block
minor testing and lut fixes, merge_log.sh helper script
what a mess, this can only be the first step...
minor testing additions - next: big autotest cleanup
autotest cleanup
better autotest framework, make test
slightly improved switch design, preparing for switch device
started with routing switches
Merge branch 'master' of github.com:Wolfgang-Spraul/fpgatools
more logic config
Merge branch 'master' of github.com:Wolfgang-Spraul/fpgatools
a little iologic switch work
intro paragraph
a few more short north and south wires, autotester
switch cleanup
more switches
more switches
Merge branch 'master' of github.com:Wolfgang-Spraul/fpgatools
finished modeling routing switchbox (2nd version)
moved switchbox to parts.c, cleanup
switch cleanup - nice code savings!
renamed fpga_net to fnet, added hello_world
continued in hello_world.c
hello world minor improvement
improving hello_world
a little more iob support
minor lut work
disable auto-crc by default
better iologic switch support
improved iob config
fixed minor iob bugs, improved iob_cfg test
added mini-jtag for configuration
changelog update
TODO update
improved testing
Merge branch 'master' of github.com:Wolfgang-Spraul/fpgatools
forgot
added blinking_led
preparing for some more lut work
added lut_encoding tests
Merge branch 'master' of github.com:Wolfgang-Spraul/fpgatools
support IO standards LVCMOS 33/25/18/15/12, LVTTL
Merge branch 'master' of github.com:Wolfgang-Spraul/fpgatools
lut cleanup and support for more cases - unfinished
Merge branch 'master' of github.com:Wolfgang-Spraul/fpgatools
improved logic testing
better support for latches
more logic and lut configuration work
cleanup and improvement of logic configuration
continued on blinking_led.c
fixed some pad names
carry chain fixes
several bug fixes
more work in iologic switches, minor fixes
minor pieces here and there, a little lost right now...
carry chain fixes, devices, bram and macc switches
more switch work
some more switches
forgot one header line...
LINKS cleanup
some work on horizontal wiring
worked on directional wires
more dirwire modeling
wire work
more wires
pcice wires
wires - more to come
worked on wires of all kinds
some more pll lock, ioclk wires and cleanup
error handling improvement
switches
minor cleanup
speed optimization for connections
Merge branch 'master' of github.com:Wolfgang-Spraul/fpgatools
minor 5% speed improvement in building model
started with clock routing
more clock routing
more clock routing
more clock routing
improved switches
more logic device cases
routing improvements
more routing
more routing work
blinking_led verified
blinking_led cmdline params
Wolfgang-Spraul (1):
Merge pull request #2 from minux/mine
Xiangfu (53):
using pkg-config for libxml-2.0 cflags etc
Makefile: add install/uninstall rules
files for debian package
add an empty man page file
add REAME for build debian package, small cleanup
Makefile: add verbosity control
ignore error on rmdir
only install fp2bit and bit2fp on fpgatools
debian: report a ITP bug for fpgatools package
create static lib files: libfpga-bit.a libfpga-control.a libfpga-cores.a libfpga-floorplan.a libfpga-model.a
add simple man page for bit2fp and fp2bit
debian: fix man page add libs package
debian: some update on description
Makefile: add automatic dependencies
Makefile: build .so instead of .a libs
makefile: include dev files
debian: remove empty -doc package, we can add it later
.gitignore: update
Makefile: forget bit.h
create a subfolder for libs
remove rpath after install, add libs version
debian: update manpages path
libs: remove all files when uninstall
debian: update ocommit for get-orig-source
using bash in Makefile
mini-jtag: using macros on clean
mini-jtag: include ../Makefile.common, fix some warnings
mini-jtag: update usage()
mini-jtag: load bitstream from stdin
mini-jtag: small cleanup on parameters, add rev_dump for remove duplicate code"
mini-jtag: add test-hello_world
fix warnings
mini-jtag: remove globle buf, use independent out buffer
mini-jtag: code style clean up
mini-jtag: split shift_dr/ir function
mini-jtag: more code on readreg
mini-jtag: add test all rule
mini-jtag: finish readreg
mini-jtag: load bits file does not require JPROGRAM instruction fix load not working with xc6slx45
mini-jtag: replace atoi with strtol
debian: update to latest commit
install: only depends on fp2bit and bit2fp
update libs/Makefile for debian packaging
debian: more works on libfpga and fpgatools depends
debian: remove debian/ from fpgatools upstream
move libxml depends to draw_svg_tiles target
fix no format arguments warnings debian package build system will mark this as error
add CPPFLAGS and LDFALGS, run chrpath on .so files
libs/Makefile: more lib version works
libs: cleanup clean/install/uninstall
mini-jtag: reset board before load config bits file
mini-jtag: reset board before load config bits file
fix snprintf no format arguments warnings
minux (5):
Makefile.common: change -Ofast to -O2 for compat.
*.sh: use "/usr/bin/env bash" shebang line
libs, mini-jtag: fix two typos
Makefile.common: don't export CC, AR, ... to sub-make
libs/bit.h: compat. change for embedded anonymous union
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