File: error.vhdl

package info (click to toggle)
freehdl 0.0.8-2.2
  • links: PTS
  • area: main
  • in suites: buster, sid, stretch
  • size: 8,632 kB
  • ctags: 10,443
  • sloc: cpp: 45,275; sh: 11,405; yacc: 4,206; ansic: 2,026; lex: 486; perl: 430; makefile: 390; tcl: 100
file content (156 lines) | stat: -rw-r--r-- 3,221 bytes parent folder | download | duplicates (5)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
package mypack is
	type bvec2d is array (0 to 1, 0 to 1) of bit;
end package;

use work.mypack.all;
entity adder is 
 	-- Currently, no generics are supported
	generic (gen1, gen2 : bit_vector (1 to 3));
	port (x : in bit_vector(1 to 4);
	      y : in bvec2d);
end adder;

architecture arch of adder is
	signal a, b, q : bit_vector(1 to 8);
begin
 p: process (a,b)
	variable ov : bit;
 begin
	ov := '0';
 end process;
end arch;

use work.mypack.all;
entity ccc is
	port (a : out bit_vector(0 to 3));
end ccc;

architecture arch of ccc is
begin
	a <= "0001";
end arch;


-- This design is used to test the error detection
-- routines of the compiler. Note that it contains
-- a lot if illegal code!
use work.mypack.all;
entity tveccomp is 
 	-- Currently, no generics are supported
	generic (gen : integer);
	port (bvec : inout bit_vector(0 to 7));
end tveccomp;

use work.ccc;
use work.adder;
architecture arch of tveccomp is
	type colors is (red, green, yellow, black, wheat, white);
	subtype colors2 is colors range green to yellow;
	subtype myint is positive range gen to 200;
	subtype bvec_type is bit_vector(1 to 10);
	subtype bvec_type2 is bvec_type(0 to 11);
	subtype bvec_type3 is bit_vector(1 to 3);
	signal clk : bit;
	signal int1 : positive;
	signal int2 : myint := 300;
	signal col1 : colors;
	signal col2 : colors2;
	signal sig1 : bit_vector(0 to 3);
	signal sig2 : bit_vector(0 to 3);

	signal ysig :  bvec2d;
	signal xsig : bit_vector(2 downto 0);
begin
	process (clk)
		variable t : time;
		constant creal : real := -1.0;
		variable cpos : positive;
		variable bbb : bvec_type3;
		
		function func return positive is 
			subtype myint2 is myint range 1 to 200;
			variable var : myint2;
		begin
			var := 0;
			return -1;
		end func;	
	begin
		case int1 is
		when 2 => clk <= not clk;	
		when 10 => clk <= not clk;	
		when 12 => clk <= not clk;	
		when 100 => clk <= not clk;
		end case;

		case int2 is
		when 100 to 140 => clk <= not clk;
		when 141 to 180 => clk <= not clk;
		end case;
	
		case col1 is
		when red => clk <= not clk;
		when red to black => clk <= not clk;
		end case;

		case col1 is
		when others => clk <= not clk;
		when red => clk <= not clk;
		end case;
		
		case col2 is
		when green => clk <= not clk;
		end case;

		t := time(int1);
		cpos := positive(creal);

		case bbb is
		when "001" => clk <= not clk;
		when "1001" => clk <= not clk;
		when "011" | "001" => clk <= not clk;
		when "011" to "001" => clk <= not clk;
		when others => clk <= not clk;
		end case;
	
		case bbb is
		when "001" => clk <= not clk;
		when "011" | "010" => clk <= not clk;
		end case;	

		bbb := "1111";
	end process;

qq2: entity ccc port map (
	a(0 to 2) => sig2(1 to 2),	
	a(0 to 1) => sig2,
	a(2 to 3) => sig2(1 to 2)
	);

qq1: entity ccc port map (
	a(0) => sig1(0), a(1) => sig1(1), a(2) => sig1(2), a(4) => sig1(3)
	);

qq3: entity adder
	generic map (
		gen1 => "11111",
		gen2(1) => '0',
		gen2(2) => '0',
		gen2(3) => '0',
		gen2(1) => '0'
	)
	port map(
		x(4) => xsig(0),
		x(1) => xsig(0),
		--x(2) => xsig(1),
		x(4) => xsig(0),
		x(3) => xsig(2),

		y(0,0) => ysig(0,0),
		--y(0,1) => ysig(0,1),
		y(1,0) => ysig(1,0),
		y(0,0) => ysig(0,0),
		y(1,1) => ysig(1,1)
		);
 
end arch;