File: model.vhdl

package info (click to toggle)
freehdl 0.0.8-2.2
  • links: PTS
  • area: main
  • in suites: buster, sid, stretch
  • size: 8,632 kB
  • ctags: 10,443
  • sloc: cpp: 45,275; sh: 11,405; yacc: 4,206; ansic: 2,026; lex: 486; perl: 430; makefile: 390; tcl: 100
file content (34 lines) | stat: -rw-r--r-- 677 bytes parent folder | download | duplicates (5)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
-- testbench to test the adder 
entity model is 
end model;

-- This is a comment
architecture struct of model is
	signal asig, bsig, qsig : bit_vector(0 to 7) := (3 | 4 | 6 => '1', others => '0');
	signal clk : bit := '0';
	--signal x : integer :=8;
begin

 clk <= not clk after 10 ns;

 process
	variable var : integer;

	procedure proc is
		variable v : integer := 1;
	begin
		report "this is another test message!";
		var := var + v;
	end proc;
 begin	
	-- Generate some test vectors for the
	-- adder
	asig <= (not asig(7)) & asig(0 to 6);
	bsig <= asig(1 to 7) & (not bsig(1));
	report "this is a test message!";
	proc;
	wait until clk = '1';
 end process;

end struct;