File: y.vhdl

package info (click to toggle)
freehdl 0.0.8-2.2
  • links: PTS
  • area: main
  • in suites: buster, sid, stretch
  • size: 8,632 kB
  • ctags: 10,443
  • sloc: cpp: 45,275; sh: 11,405; yacc: 4,206; ansic: 2,026; lex: 486; perl: 430; makefile: 390; tcl: 100
file content (75 lines) | stat: -rw-r--r-- 1,649 bytes parent folder | download | duplicates (5)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
-----------------------------------------------------------
-- Example VHDL file
-----------------------------------------------------------

-----------------------------------------------------------
-- Example VHDL file
-----------------------------------------------------------

-- A simple 8 bit adder


entity adder2 is 
 	-- Currently, no generics are supported
	generic (gen : integer := 10);
	port (a, b : in bit_vector(1 to 8);
	      q : out bit_vector(1 to 8));
end adder2;

architecture arch of adder2 is

begin
 p: process (a,b)
	variable ov : bit;
 begin
	ov := '0';
	for i in 8 downto 1 loop
		q(i) <= a(i) xor b(i) xor ov;
		if (a(i) = '1' and b(i) = '1') or
		   (ov = '1' and b(i) = '1') or
		   (a(i) = '1' and ov = '1') then
		 	ov := '1';
		else
			ov := '0';
		end if;
	end loop;
 end process;
end arch;

use WORK.adder2;
-- testbench to test the adder 
entity model is 
end model;

-- This is a comment
architecture struct of model is
	signal asig, bsig, qsig, qsig2 : bit_vector(1 to 8) := (3 | 4 | 6 => '1', others => '0');
	signal clk : bit := '0';
	--signal x : integer :=8;
	component adder2  
 	-- Currently, no generics are supported
	port (a, b : in bit_vector(1 to 8);
	      q : out bit_vector(1 to 8));
	end component;

begin

 -- Instantiate the adder circuit
 addcomp: adder2
	port map(a => asig, b => bsig, q => qsig);
 
 addselect: adder2 port map(a => asig, b => bsig, q => qsig2);

 clk <= not clk after 10 ns;

 process
 begin	
	-- Generate some test vectors for the
	-- adder
	asig <= (not asig(8)) & asig(1 to 7);
	bsig <= asig(2 to 8) & (not bsig(1));
	wait until clk = '1';
 end process;

end struct;