#! /bin/sh -e

# DP: Add niagara2 optimization support

if [ $# -eq 3 ] && [ "$2" = '-d' ]; then
    pdir="-d $3"
    dir="$3/"
elif [ $# -ne 1 ]; then
    echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
    exit 1
fi
case "$1" in
    -patch)
	patch $pdir -f --no-backup-if-mismatch -p0 < $0
        cd ${dir}libcpp && autoconf
	;;
    -unpatch)
	patch $pdir -f --no-backup-if-mismatch -R -p0 < $0
        cd ${dir}libcpp && autoconf
	;;
    *)
	echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
	exit 1;;
esac

exit 0

--- gcc/config.gcc.~1~	2007-09-26 18:09:21.000000000 -0700
+++ gcc/config.gcc	2007-09-26 18:09:47.000000000 -0700
@@ -2800,7 +2800,7 @@ case "${target}" in
 			"" | sparc | sparcv9 | sparc64 | sparc86x \
 			| v7 | cypress | v8 | supersparc | sparclite | f930 \
 			| f934 | hypersparc | sparclite86x | sparclet | tsc701 \
-			| v9 | ultrasparc | ultrasparc3 | niagara)
+			| v9 | ultrasparc | ultrasparc3 | niagara | niagara2)
 				# OK
 				;;
 			*)
--- gcc/config/sparc/linux64.h.~1~	2007-09-26 18:09:21.000000000 -0700
+++ gcc/config/sparc/linux64.h	2007-09-26 18:09:47.000000000 -0700
@@ -49,7 +49,8 @@ Boston, MA 02110-1301, USA.  */
 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
     || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
     || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
-    || TARGET_CPU_DEFAULT == TARGET_CPU_niagara
+    || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \
+    || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
 /* A 64 bit v9 compiler with stack-bias,
    in a Medium/Low code model environment.  */
 
--- gcc/config/sparc/niagara2.md.~1~	2007-09-26 18:09:30.000000000 -0700
+++ gcc/config/sparc/niagara2.md	2007-09-26 18:09:47.000000000 -0700
@@ -0,0 +1,91 @@
+;; Scheduling description for Niagara-2.
+;;   Copyright (C) 2007 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+;; Boston, MA 02110-1301, USA.
+
+;; Niagara-2 is a single-issue processor.
+
+(define_automaton "niagara2_0")
+
+(define_cpu_unit "niag2_pipe" "niagara2_0")
+
+(define_insn_reservation "niag2_25cycle" 25
+  (and (eq_attr "cpu" "niagara2")
+    (eq_attr "type" "flushw"))
+  "niag2_pipe*25")
+
+(define_insn_reservation "niag2_5cycle" 5
+  (and (eq_attr "cpu" "niagara2")
+    (eq_attr "type" "multi,flushw,iflush,trap"))
+  "niag2_pipe*5")
+
+(define_insn_reservation "niag2_6cycle" 4
+  (and (eq_attr "cpu" "niagara2")
+    (eq_attr "type" "savew"))
+  "niag2_pipe*4")
+
+/* Most basic operations are single-cycle. */
+(define_insn_reservation "niag2_ialu" 1
+ (and (eq_attr "cpu" "niagara2")
+   (eq_attr "type" "ialu,shift,compare,cmove"))
+ "niag2_pipe")
+
+(define_insn_reservation "niag2_imul" 5
+ (and (eq_attr "cpu" "niagara2")
+   (eq_attr "type" "imul"))
+ "niag2_pipe*5")
+
+(define_insn_reservation "niag2_idiv" 31
+ (and (eq_attr "cpu" "niagara2")
+   (eq_attr "type" "idiv"))
+ "niag2_pipe*31")
+
+(define_insn_reservation "niag2_branch" 5
+  (and (eq_attr "cpu" "niagara2")
+    (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch"))
+  "niag2_pipe*5")
+
+(define_insn_reservation "niag2_3cycle_load" 3
+  (and (eq_attr "cpu" "niagara2")
+    (eq_attr "type" "load,fpload"))
+  "niag2_pipe*3")
+
+(define_insn_reservation "niag2_1cycle_store" 1
+  (and (eq_attr "cpu" "niagara2")
+    (eq_attr "type" "store,fpstore"))
+  "niag2_pipe")
+
+(define_insn_reservation "niag2_fp" 3
+  (and (eq_attr "cpu" "niagara2")
+    (eq_attr "type" "fpmove,fpcmove,fpcrmove,fpcmp,fpmul"))
+  "niag2_pipe*3")
+
+(define_insn_reservation "niag2_fdivs" 19
+  (and (eq_attr "cpu" "niagara2")
+    (eq_attr "type" "fpdivs"))
+  "niag2_pipe*19")
+
+(define_insn_reservation "niag2_fdivd" 33
+  (and (eq_attr "cpu" "niagara2")
+    (eq_attr "type" "fpdivd"))
+  "niag2_pipe*33")
+
+(define_insn_reservation "niag2_vis" 6
+  (and (eq_attr "cpu" "niagara2")
+    (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist"))
+  "niag2_pipe*6")
--- gcc/config/sparc/sol2-bi.h.~1~	2007-09-26 18:09:21.000000000 -0700
+++ gcc/config/sparc/sol2-bi.h	2007-09-26 18:09:47.000000000 -0700
@@ -48,6 +48,15 @@
 #define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
 #endif
 
+#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
+#undef CPP_CPU64_DEFAULT_SPEC
+#define CPP_CPU64_DEFAULT_SPEC ""
+#undef ASM_CPU32_DEFAULT_SPEC
+#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb"
+#undef ASM_CPU64_DEFAULT_SPEC
+#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
+#endif
+
 #if DEFAULT_ARCH32_P
 #define DEF_ARCH32_SPEC(__str) "%{!m64:" __str "}"
 #define DEF_ARCH64_SPEC(__str) "%{m64:" __str "}"
@@ -66,7 +75,7 @@
 %{mcpu=sparclite|mcpu-f930|mcpu=f934:-D__sparclite__} \
 %{mcpu=v8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
 %{mcpu=supersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \
-%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3|mcpu=niagara:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
+%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3|mcpu=niagara|mcpu=niagara2:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
 "
 
@@ -76,7 +85,8 @@
 %{mcpu=ultrasparc:" DEF_ARCH32_SPEC("-xarch=v8plusa") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "a") "} \
 %{mcpu=ultrasparc3:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \
 %{mcpu=niagara:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \
-%{!mcpu=niagara:%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}}}} \
+%{mcpu=niagara2:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \
+%{!mcpu=niagara2:%{!mcpu=niagara:%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}}}}} \
 %{!mcpu*:%(asm_cpu_default)} \
 "
 
--- gcc/config/sparc/sol2.h.~1~	2007-09-26 18:09:21.000000000 -0700
+++ gcc/config/sparc/sol2.h	2007-09-26 18:09:47.000000000 -0700
@@ -46,12 +46,18 @@ Boston, MA 02110-1301, USA.  */
 #define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusb"
 #endif
 
+#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
+#undef ASM_CPU_DEFAULT_SPEC
+#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusb"
+#endif
+
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC "\
 %{mcpu=v9:-xarch=v8plus} \
 %{mcpu=ultrasparc:-xarch=v8plusa} \
 %{mcpu=ultrasparc3:-xarch=v8plusb} \
 %{mcpu=niagara:-xarch=v8plusb} \
+%{mcpu=niagara2:-xarch=v8plusb} \
 %{!mcpu*:%(asm_cpu_default)} \
 "
 
--- gcc/config/sparc/sparc.c.~1~	2007-09-26 18:09:21.000000000 -0700
+++ gcc/config/sparc/sparc.c	2007-09-26 18:09:47.000000000 -0700
@@ -220,6 +220,30 @@ struct processor_costs niagara_costs = {
   0, /* shift penalty */
 };
 
+static const
+struct processor_costs niagara2_costs = {
+  COSTS_N_INSNS (3), /* int load */
+  COSTS_N_INSNS (3), /* int signed load */
+  COSTS_N_INSNS (3), /* int zeroed load */
+  COSTS_N_INSNS (3), /* float load */
+  COSTS_N_INSNS (6), /* fmov, fneg, fabs */
+  COSTS_N_INSNS (6), /* fadd, fsub */
+  COSTS_N_INSNS (6), /* fcmp */
+  COSTS_N_INSNS (6), /* fmov, fmovr */
+  COSTS_N_INSNS (6), /* fmul */
+  COSTS_N_INSNS (19), /* fdivs */
+  COSTS_N_INSNS (33), /* fdivd */
+  COSTS_N_INSNS (19), /* fsqrts */
+  COSTS_N_INSNS (33), /* fsqrtd */
+  COSTS_N_INSNS (5), /* imul */
+  COSTS_N_INSNS (5), /* imulX */
+  0, /* imul bit factor */
+  COSTS_N_INSNS (31), /* idiv, average of 12 - 41 cycle range */
+  COSTS_N_INSNS (31), /* idivX, average of 12 - 41 cycle range */
+  COSTS_N_INSNS (1), /* movcc/movr */
+  0, /* shift penalty */
+};
+
 const struct processor_costs *sparc_costs = &cypress_costs;
 
 #ifdef HAVE_AS_RELAX_OPTION
@@ -621,6 +645,7 @@ sparc_override_options (void)
     { TARGET_CPU_ultrasparc, "ultrasparc" },
     { TARGET_CPU_ultrasparc3, "ultrasparc3" },
     { TARGET_CPU_niagara, "niagara" },
+    { TARGET_CPU_niagara2, "niagara2" },
     { 0, 0 }
   };
   const struct cpu_default *def;
@@ -658,6 +683,7 @@ sparc_override_options (void)
     { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
     /* UltraSPARC T1 */
     { "niagara", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
+    { "niagara2", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9},
     { 0, 0, 0, 0 }
   };
   const struct cpu_table *cpu;
@@ -768,7 +794,8 @@ sparc_override_options (void)
   if (align_functions == 0
       && (sparc_cpu == PROCESSOR_ULTRASPARC
 	  || sparc_cpu == PROCESSOR_ULTRASPARC3
-	  || sparc_cpu == PROCESSOR_NIAGARA))
+	  || sparc_cpu == PROCESSOR_NIAGARA
+	  || sparc_cpu == PROCESSOR_NIAGARA2))
     align_functions = 32;
 
   /* Validate PCC_STRUCT_RETURN.  */
@@ -820,6 +847,9 @@ sparc_override_options (void)
     case PROCESSOR_NIAGARA:
       sparc_costs = &niagara_costs;
       break;
+    case PROCESSOR_NIAGARA2:
+      sparc_costs = &niagara2_costs;
+      break;
     };
 
 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
@@ -7131,7 +7161,8 @@ sparc_initialize_trampoline (rtx tramp, 
   emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
   if (sparc_cpu != PROCESSOR_ULTRASPARC
       && sparc_cpu != PROCESSOR_ULTRASPARC3
-      && sparc_cpu != PROCESSOR_NIAGARA)
+      && sparc_cpu != PROCESSOR_NIAGARA
+      && sparc_cpu != PROCESSOR_NIAGARA2)
     emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
 						     plus_constant (tramp, 8)))));
 
@@ -7174,7 +7205,8 @@ sparc64_initialize_trampoline (rtx tramp
 
   if (sparc_cpu != PROCESSOR_ULTRASPARC
       && sparc_cpu != PROCESSOR_ULTRASPARC3
-      && sparc_cpu != PROCESSOR_NIAGARA)
+      && sparc_cpu != PROCESSOR_NIAGARA
+      && sparc_cpu != PROCESSOR_NIAGARA2)
     emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
 
   /* Call __enable_execute_stack after writing onto the stack to make sure
@@ -7354,7 +7386,8 @@ sparc_sched_init (FILE *dump ATTRIBUTE_U
 static int
 sparc_use_sched_lookahead (void)
 {
-  if (sparc_cpu == PROCESSOR_NIAGARA)
+  if (sparc_cpu == PROCESSOR_NIAGARA
+      || sparc_cpu == PROCESSOR_NIAGARA2)
     return 0;
   if (sparc_cpu == PROCESSOR_ULTRASPARC
       || sparc_cpu == PROCESSOR_ULTRASPARC3)
@@ -7372,6 +7405,7 @@ sparc_issue_rate (void)
   switch (sparc_cpu)
     {
     case PROCESSOR_NIAGARA:
+    case PROCESSOR_NIAGARA2:
     default:
       return 1;
     case PROCESSOR_V9:
--- gcc/config/sparc/sparc.h.~1~	2007-09-26 18:09:21.000000000 -0700
+++ gcc/config/sparc/sparc.h	2007-09-26 18:09:47.000000000 -0700
@@ -206,7 +206,8 @@ extern enum cmodel sparc_cmodel;
    which requires the following macro to be true if enabled.  Prior to V9,
    there are no instructions to even talk about memory synchronization.
    Note that the UltraSPARC III processors don't implement RMO, unlike the
-   UltraSPARC II processors.  Niagara does not implement RMO either.
+   UltraSPARC II processors.  Niagara and Niagara-2 do not implement RMO
+   either.
 
    Default to false; for example, Solaris never enables RMO, only ever uses
    total memory ordering (TMO).  */
@@ -239,11 +240,13 @@ extern enum cmodel sparc_cmodel;
 #define TARGET_CPU_ultrasparc	8
 #define TARGET_CPU_ultrasparc3	9
 #define TARGET_CPU_niagara	10
+#define TARGET_CPU_niagara2	11
 
 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
  || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
  || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
- || TARGET_CPU_DEFAULT == TARGET_CPU_niagara
+ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \
+ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
 
 #define CPP_CPU32_DEFAULT_SPEC ""
 #define ASM_CPU32_DEFAULT_SPEC ""
@@ -268,6 +271,10 @@ extern enum cmodel sparc_cmodel;
 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
 #endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
+#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
+#define ASM_CPU64_DEFAULT_SPEC "-Av9b"
+#endif
 
 #else
 
@@ -359,6 +366,7 @@ extern enum cmodel sparc_cmodel;
 %{mcpu=ultrasparc:-D__sparc_v9__} \
 %{mcpu=ultrasparc3:-D__sparc_v9__} \
 %{mcpu=niagara:-D__sparc_v9__} \
+%{mcpu=niagara2:-D__sparc_v9__} \
 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
 "
 #define CPP_ARCH32_SPEC ""
@@ -409,6 +417,7 @@ extern enum cmodel sparc_cmodel;
 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
 %{mcpu=niagara:%{!mv8plus:-Av9b}} \
+%{mcpu=niagara2:%{!mv8plus:-Av9b}} \
 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
 "
 
@@ -533,7 +542,8 @@ enum processor_type {
   PROCESSOR_V9,
   PROCESSOR_ULTRASPARC,
   PROCESSOR_ULTRASPARC3,
-  PROCESSOR_NIAGARA
+  PROCESSOR_NIAGARA,
+  PROCESSOR_NIAGARA2
 };
 
 /* This is set from -m{cpu,tune}=xxx.  */
@@ -2147,7 +2157,8 @@ do {                                    
     || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS)		\
    ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
        || sparc_cpu == PROCESSOR_ULTRASPARC3 \
-       || sparc_cpu == PROCESSOR_NIAGARA) ? 12 : 6) : 2)
+       || sparc_cpu == PROCESSOR_NIAGARA \
+       || sparc_cpu == PROCESSOR_NIAGARA2) ? 12 : 6) : 2)
 
 /* Provide the cost of a branch.  For pre-v9 processors we use
    a value of 3 to take into account the potential annulling of
@@ -2160,7 +2171,10 @@ do {                                    
    mispredicted branch.
 
    On Niagara, normal branches insert 3 bubbles into the pipe
-   and annulled branches insert 4 bubbles.  */
+   and annulled branches insert 4 bubbles.
+
+   On Niagara-2, a not-taken branch costs 1 cycle whereas a taken
+   branch costs 6 cycles.  */
 
 #define BRANCH_COST \
 	((sparc_cpu == PROCESSOR_V9 \
@@ -2170,17 +2184,21 @@ do {                                    
             ? 9 \
 	 : (sparc_cpu == PROCESSOR_NIAGARA \
 	    ? 4 \
-	 : 3)))
+	 : (sparc_cpu == PROCESSOR_NIAGARA2 \
+	    ? 5 \
+	 : 3))))
 
 #define PREFETCH_BLOCK \
 	((sparc_cpu == PROCESSOR_ULTRASPARC \
           || sparc_cpu == PROCESSOR_ULTRASPARC3 \
-	  || sparc_cpu == PROCESSOR_NIAGARA) \
+	  || sparc_cpu == PROCESSOR_NIAGARA \
+	  || sparc_cpu == PROCESSOR_NIAGARA2) \
          ? 64 : 32)
 
 #define SIMULTANEOUS_PREFETCHES \
 	((sparc_cpu == PROCESSOR_ULTRASPARC \
-	  || sparc_cpu == PROCESSOR_NIAGARA) \
+	  || sparc_cpu == PROCESSOR_NIAGARA \
+	  || sparc_cpu == PROCESSOR_NIAGARA2) \
          ? 2 \
          : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
             ? 8 : 3))
--- gcc/config/sparc/sparc.md.~1~	2007-09-26 18:09:21.000000000 -0700
+++ gcc/config/sparc/sparc.md	2007-09-26 18:09:47.000000000 -0700
@@ -91,7 +91,8 @@
    v9,
    ultrasparc,
    ultrasparc3,
-   niagara"
+   niagara,
+   niagara2"
   (const (symbol_ref "sparc_cpu_attr")))
 
 ;; Attribute for the instruction set.
@@ -313,6 +314,7 @@
 (include "ultra1_2.md")
 (include "ultra3.md")
 (include "niagara.md")
+(include "niagara2.md")
 
 
 ;; Operand and operator predicates.