1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
|
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_altivec_ok } */
/* { dg-options "-O2 -mdejagnu-cpu=power5 -mabi=altivec -mno-altivec -mno-vsx" } */
/* { dg-final { scan-assembler "\[ \t\]and " } } */
/* { dg-final { scan-assembler "\[ \t\]or " } } */
/* { dg-final { scan-assembler "\[ \t\]xor " } } */
/* { dg-final { scan-assembler "\[ \t\]nor " } } */
/* { dg-final { scan-assembler "\[ \t\]andc " } } */
/* { dg-final { scan-assembler "\[ \t\]eqv " } } */
/* { dg-final { scan-assembler "\[ \t\]orc " } } */
/* { dg-final { scan-assembler "\[ \t\]nand " } } */
/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */
/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */
/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */
/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */
/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */
/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */
/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */
/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */
/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */
/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */
/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */
/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */
/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */
#ifndef TYPE
typedef int v4si __attribute__ ((vector_size (16)));
#define TYPE v4si
#endif
#include "bool2.h"
|
