File: dform-3.c

package info (click to toggle)
gcc-arm-none-eabi 15%3A12.2.rel1-1
  • links: PTS, VCS
  • area: main
  • in suites: bookworm
  • size: 959,712 kB
  • sloc: cpp: 3,275,382; ansic: 2,061,766; ada: 840,956; f90: 208,513; makefile: 76,132; asm: 73,433; xml: 50,448; exp: 34,146; sh: 32,436; objc: 15,637; fortran: 14,012; python: 11,991; pascal: 6,787; awk: 4,779; perl: 3,054; yacc: 338; ml: 285; lex: 201; haskell: 122
file content (38 lines) | stat: -rw-r--r-- 982 bytes parent folder | download 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
 
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power9 -O2" } */

#ifndef TYPE
#define TYPE vector double
#endif

struct foo {
  TYPE a, b, c, d;
};

/* Test whether ISA 3.0 vector d-form instructions are implemented.  */
void
add (struct foo *p)
{
  p->b = p->c + p->d;
}

/* Make sure we don't use direct moves to get stuff into GPR registers.  */
void
gpr (struct foo *p)
{
  TYPE x = p->c;

  __asm__ (" # reg = %0" : "+r" (x));

  p->b = x;
}

/* { dg-final { scan-assembler     "lxv "      } } */
/* { dg-final { scan-assembler     "stxv "     } } */
/* { dg-final { scan-assembler-not "lxvx "     } } */
/* { dg-final { scan-assembler-not "stxvx "    } } */
/* { dg-final { scan-assembler-not "mfvsrd "   } } */
/* { dg-final { scan-assembler-not "mfvsrld "  } } */
/* { dg-final { scan-assembler     "l\[dq\] "  } } */
/* { dg-final { scan-assembler     "st\[dq\] " } } */