File: lhs-1.c

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gcc-arm-none-eabi 15%3A12.2.rel1-1
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -mdejagnu-cpu=power5" } */
/* { dg-final { scan-assembler-times "nop" 3 } } */

/* Test generation of nops in load hit store situation.  Make sure enough nop
   insns are generated to move the load to a new dispatch group.  With the
   simple stw/lwz pair below, that would be 3 nop insns for Power5.  */

unsigned int f (volatile unsigned int *u, unsigned int u2)
{
  *u = u2;
  return *u;
}