File: zero-extend-1.c

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gcc-arm-none-eabi 15%3A12.2.rel1-1
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/* { dg-do compile { target { riscv64*-*-* } } } */
/* { dg-options "-march=rv64gc -mabi=lp64" } */
unsigned long
sub1 (unsigned int i)
{
  return i >> 1;
}
/* { dg-final { scan-assembler-times "srliw" 1 } } */