File: gcc-3.3.6-m68hc1x-20060122.diffs

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diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/ChangeLog.M68HC11 gcc-3.3.6-m68hc1x/ChangeLog.M68HC11
--- gcc-3.3.6/ChangeLog.M68HC11	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/ChangeLog.M68HC11	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,4 @@
+2003-05-18  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* configure.in (m68hc11): Configure libstdcxx_version.
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/ChangeLog.M68HC11 gcc-3.3.6-m68hc1x/gcc/ChangeLog.M68HC11
--- gcc-3.3.6/gcc/ChangeLog.M68HC11	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/ChangeLog.M68HC11	Sun Jan 22 21:17:21 2006
@@ -0,0 +1,373 @@
+2006-01-22  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* version.c: Bump to 2006-01-22
+
+2006-01-22  Stephane Carrez  <stcarrez@nerim.fr>
+
+        PR savannah/13917
+	* config/m68hc11/m68hc11.c (nonimmediate_noinc_operand): New predicate.
+	* config/m68hc11/m68hc11-protos.h (nonimmediate_noinc_operand): Declare.
+	* config/m68hc11/m68hc11.h (PREDICATE_CODES): Register it.
+	* config/m68hc11/m68hc11.md ("addqi3"): Use it for operand 0, 1.
+	("uminqi3"): Likewise.
+	("umaxqi3"): Likewise.
+	("uminhi3"): Likewise.
+	("umaxhi3"): Likewise.
+	("negqi2"): Likewise.
+	("*ashlqi3_const1", "*ashrqi3_const1"): Likewise.
+	("lshrhi3_const", "*lshrqi3_const1"): Likewise.
+
+2006-01-20  Stephane Carrez  <stcarrez@nerim.fr>
+
+	savannah/15493
+	* config/m68hc11/m68hc11.c (m68hc11_gen_movqi): Must save register
+	A and copy X or Y in it for a move when both operands refer to X or Y.
+
+2005-11-05  Stephane Carrez  <stcarrez@nerim.fr>
+
+	PR savannah/13879
+	* expmed.c (make_tree): If we have a constant for SIGN_EXTEND or
+	ZERO_EXTEND, use the mode from the extend node; the constant is VOIDmode
+	and it will crash.
+
+2005-11-05  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* expmed.c (store_bit_field): Must apply a correction for big-endian
+	target when the bitfield contains less word than the source constant.
+
+2005-05-15  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.h (REG_VALID_P): The macro can be used with
+	signed numbers passed as argument.
+	* version.c: Bump to 20050515
+
+2005-05-08  Stephane Carrez  <stcarrez@nerim.fr>
+
+	PR savannah/12572
+	* config/m68hc11/m68hc11.md ("movhi"): Sign extend the constants in
+	the range 32768..65535 so that the generated set is recognized.
+
+2005-05-08  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md ("mulqi3"): Use general_operand for operand
+	1 and fix constraints.
+	("mulqihi3")" Use general_operand for operand 2.
+	* config/m68hc11/m68hc11.c (m68hc11_gen_movqi): Use pula and pulb
+	instead of lda and ldb for 68HC12.
+
+2005-05-08  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11-protos.h (m68hc11_hard_regno_rename_ok): Pass
+	the mode.
+	* config/m68hc11/m68hc11.h (HARD_REGNO_RENAME_OK): Likewise.
+	* config/m68hc11/m68hc11.c (m68hc11_hard_regno_rename_ok): Likewise.
+	* regrename.c (regrename_optimize): Pass the mode in which the register
+	is used.
+
+2005-04-03  Stephane Carrez  <stcarrez@nerim.fr>
+
+	PR savannah/12297
+	* config/m68hc11/m68hc11.c (m68hc11_z_replacement): Use emit_insn_after
+	when adding the save Z instruction so that it is part of the good BB.
+
+2005-02-13  Stephane Carrez  <stcarrez@nerim.fr>
+
+	PR target/17551
+	* gcse.c (handle_avail_expr): Use gen_move_insn() instead of
+	gen_rtx_SET()
+
+2005-02-13  Stephane Carrez  <stcarrez@nerim.fr>
+
+	PR target/16925
+	* config/m68hc11/m68hc11.c (m68hc11_gen_highpart): Handle split of
+	64-bit constants on 64-bit hosts.
+	(m68hc11_split_logical): Simplify.
+	(m68hc11_split_move): Likewise.
+
+2005-02-12  Stephane Carrez  <stcarrez@nerim.fr>
+
+	PR savannah/11813
+	* config/m68hc11/m68hc11.c (reg_or_some_mem_operand): Do not allow
+	the 68HC12 address indirect addressing mode as it is not supported
+	by bset and bclr.
+
+2005-01-29  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* version.c (version_string): Bump to 2005-01-29.
+	* config/udivmodsi4.c (__udivmodsi4): Rewrite ediv as it didn't
+	passed the gcc validation.
+
+2005-01-28  Stephane Carrez  <stcarrez@nerim.fr>
+
+	From philipljohnson@comcast.net:
+
+	Patch savannah/3626
+	* config/udivmodsi4.c (__udivmodsi4): Use 68HC12 ediv instruction to
+	compute division and modulus.
+
+2004-08-30  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.c (m68hc11_gen_movhi): Fix invalid generation
+	of indexed indirect addressing with movw
+
+2004-08-29  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* version.c (version_string): Bump to 2004-08-29.
+
+2004-08-29  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* final.c (alter_subreg): Adjust the offset of paradoxical subreg
+	so that we load the correct value.
+
+2004-08-06  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md ("movhi_const0"): Use this pattern only
+	for 68HC11.
+
+2004-08-01  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* version.c (version_string): Bump to 2004-08-01 and use gcc 3.3.4.
+
+2004-06-06  Stephane Carrez  <stcarrez@nerim.fr>
+
+	PR target/14542
+	* config/m68hc11/m68hc11.md (move peephole2): Emit a use note to avoid
+	a live change of a register after peephole replacement.
+
+2004-06-06  Stephane Carrez  <stcarrez@nerim.fr>
+
+	PR target/14457
+	* config/m68hc11/m68hc11.c (splitable_operand): New predicate.
+	* config/m68hc11/m68hc11-protos.h (splitable_operand): Declare.
+	* config/m68hc11/m68hc11.h (PREDICATE_CODES): Register it.
+	(inhibit_libc): Must define.
+	* config/m68hc11/m68hc11.md ("movhi_const0"): Use splitable_operand.
+	("*andhi3_gen", "iorhi3", "*iorhi3_gen"): Likewise.
+	("xorhi3"): Likewise.
+
+2004-04-25  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md ("iorqi3_gen"): Use general_operand for
+	first operand.
+	("*andqi3_gen", "xorqi3"): Likewise.
+	("subqi3", "*subhi3"): Likewise.
+	("*addhi3_zext"): Likewise.
+
+2004-04-25  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.h (ASM_OUTPUT_LABELREF): Redefine to strip
+	any name encoding.
+
+2004-03-07  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md ("*lshrsi3_const"): Disable for 68HC12.
+	("*lshrsi3"): Also accept an immediate for 68HC12.
+	("*ashrsi3_const"): Likewise.
+	("*ashrsi3"): Likewise.
+	("*ashlsi3_const"): Likewise.
+	("*ashlsi3"): Likewise.
+	("cmphi_1_hc12"): Compare two hard register by pushing them and
+	comparing with a pop; don't use a split for that.
+	("cmphi split"): Disable compare split for 68HC12.
+
+2004-03-06  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md ("*lshrsi3_const1"): Allow a memory for
+	operand 1 when operand 0 is a soft register.
+	("*ashlsi3_const1"): Likewise.
+
+2004-03-06  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.c (m68hc11_gen_movhi): Use 2,-sp to push
+	the stack register.
+
+2004-03-06  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* doc/extend.texi (Function Attributes): Document page0, trap and
+	update far documentation.
+
+2004-03-06  Stephane Carrez  <stcarrez@nerim.fr>
+
+	PR savannah/4987:
+	* doc/invoke.texi (M68hc1x Options): Document -mrelax
+
+2004-03-06  Stephane Carrez  <stcarrez@nerim.fr>
+
+	PR savannah/8028:
+	* config/m68hc11/m68hc11.c (expand_prologue): Don't make an interrupt
+	or a trap handler a far symbol.
+	(m68hc11_initial_elimination_offset): Likewise.
+
+2004-03-06  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md ("*lshrsi3_const1"): Tune constraints
+	to optimize more case where we don't need a scratch register.
+	("*ashlsi3_const1"): Likewise.
+	("*pushdi_internal"): New insn and split
+	to separate push from moves.
+	("*pushdf_internal"): Likewise.
+	("*pushsf_internal"): Likewise.
+	("*pushsi_internal"): Likewise.
+	("movdi_internal"): Use define_insn_and_split; non push operand.
+	("movdf_internal"): Likewise.
+	("movsf_internal"): Likewise.
+	("movsi_internal"): Likewise.
+
+2004-03-02  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.c (m68hc11_addr_mode): New variable.
+	(m68hc11_mov_addr_mode): Likewise.
+	(m68hc11_override_options): Initialize them based on target.
+	(register_indirect_p): Allow a MEM for indirect addressing modes and
+	use flags to control what is allowed.
+	(m68hc11_small_indexed_indirect_p): Use m68hc11_mov_addr_mode for
+	supported addressing modes.
+	(m68hc11_register_indirect_p): Use m68hc11_addr_mode.
+	(go_if_legitimate_address_internal): Likewise.
+	(m68hc11_indirect_p): Likewise and check the mode.
+	(print_operand): Allow a (MEM (MEM)) and generate indirect addressing.
+
+2004-02-22  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* version.c: Bump to 20040222 and use gcc 3.3.3.
+
+2003-11-16  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* version.c: Bump to 200311116.
+
+2003-11-10  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11-protos.h (m68hc11_page0_symbol_p): Declare.
+	* config/m68hc11/m68hc11.c (m68hc11_page0_symbol_p): New predicate.
+	(m68hc11_indirect_p): Use it.
+	(print_operand): Likewise.
+	(m68hc11_handle_page0_attribute): New function to handle page0
+	attribute
+	(m68hc11_attribute_table): New attribute page0
+	(m68hc11_encode_section_info): Check page0 attribute.
+	* config/m68hc11/m68hc11.md: Use define_insn_and_split
+	(peephole2): New peephole to generate bset/bclr.
+	(peephole): New peephole to optimize compare in few cases and
+	setting of 2 registers from memory.
+
+2003-10-04  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* version.c: Bump to 20031004.
+
+2003-10-04  Stephane Carrez  <stcarrez@nerim.fr>
+
+	PR savannah/3432:
+	* config/m68hc11/t-m68hc11-gas (MULTILIB_MATCHES): m68hcs12 is
+	identical to m68hc12 for libraries.
+
+2003-10-01  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* version.c: Bump to 20031001.
+
+2003-09-30  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md ("*ashldi3_const32"): Adjust first operand
+	if it uses stack pointer register.
+
+2003-09-30  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md (peephole2 "remove one load"): Make sure
+	that register operand 3 does not appear in operand 2.
+
+2003-08-08  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* version.c: Bump to 20030808
+
+2003-08-02  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md (peephole2 "leas 2,sp"): Enable it
+	and add a use rtx.
+	(peephole2): New peephole to optimize moves on stack.
+
+2003-07-19  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md (peephole2 abx): Use m68hc11_gen_lowpart
+	to make sure the constant has the appropriate QImode.
+
+2003-07-08  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.h (HAVE_AS_DWARF2_DEBUG_LINE): Don't define
+	as .file/.loc directives are incompatible with linker relaxation.
+
+2003-05-19  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md ("*movqi" split): Don't split when source
+	or destination is d, b or a register.
+
+2003-05-18  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md ("*logicalhi3_zexthi_ashift8): Allow
+	address registers for operand 1 and 2.
+
+2003-05-18  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* reload.c (find_reloads_toplev): Do not reload the paradoxical
+	subreg with its wider mode but the register itself.
+
+2003-05-18  Stephane Carrez  <stcarrez@nerim.fr>
+
+	Merge 3.0.4-20030501 patchs in 3.3
+
+	2003-03-12  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md
+	("movdi_internal", "movdf_internal"): Fix constraints.
+	("movsi_internal", "movsf_internal"): Likewise.
+	(peephole2): New peephole2 to optimize the address computations
+	by using 'abx' and 'aby'.
+	(peephole2): New peephole2 to optimize 32-bit shift and use only
+	one hard register instead of two.
+	(peephole2): New peephole2 to avoid loading the same value in two
+	different registers.
+
+	2003-03-12  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md (split "logicalsi3_silshl16_zext"): Split
+	after reload but reject the particular case that generates a xgdx 
+	pattern, it must be handled after Z register replacement.
+
+	2003-03-10  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md ("*addhi3_68hc12"): Accept any constant
+	when adding to X and Y since leax/leay are fast.
+	("*addhi3"): Accept 'I' constraint when adding to address register.
+
+	2003-02-27  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md ("*logicalsi3_silshr16"): Accept D reg
+	on all operands.
+
+	2003-01-10  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* config/m68hc11/m68hc11.md ("*logicalsi3_silshl16_zext"): New split.
+	("*logicalsi3_silshr16"): Fix constraints.
+
+	2002-02-27  Stephane Carrez  <Stephane.Carrez@worldnet.fr>
+
+	* reload.c (find_reloads): Change to RELOAD_FOR_OTHER_ADDRESS any
+	RELOAD_FOR_OPERAND_ADDRESS reloads which is used by a RELOAD_FOR_OTHER
+	reload (ensures correct order of reload insns).
+
+	2001-07-09  Stephane Carrez  <Stephane.Carrez@worldnet.fr>
+
+	* reload1.c (merge_assigned_reloads): After a RELOAD_OTHER merge,
+	fix setting of the reloads of that reload to RELOAD_FOR_OTHER_ADDRESS.
+
+	2001-06-22  Stephane Carrez  <Stephane.Carrez@worldnet.fr>
+
+	* config/m68hc11/m68hc11.h (MAX_BITS_PER_WORD): Define to 32.
+
+	2001-03-01  Stephane Carrez  <Stephane.Carrez@worldnet.fr>
+
+	* reload1.c (merge_assigned_reloads): Change the type of the
+	reload to emit it at the good place after the merge.
+
+	2001-02-24  Stephane Carrez  <Stephane.Carrez@worldnet.fr>
+
+        * reload.c (find_reloads_subreg_address): Call find_reloads_address
+        with the same reload type.
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/collect2.c gcc-3.3.6-m68hc1x/gcc/collect2.c
--- gcc-3.3.6/gcc/collect2.c	Mon Dec  8 20:02:39 2003
+++ gcc-3.3.6-m68hc1x/gcc/collect2.c	Sat Nov  5 19:17:25 2005
@@ -74,6 +74,10 @@ Software Foundation, 59 Temple Place - S
 #undef REAL_STRIP_FILE_NAME
 #endif
 
+#ifdef WIN32
+# define USE_POPEN
+#endif
+
 /* If we cannot use a special method, use the ordinary one:
    run nm to find what symbols are present.
    In a cross-compiler, this means you need a cross nm,
@@ -444,7 +448,11 @@ handler (signo)
 #endif
 
   signal (signo, SIG_DFL);
+#ifndef WIN32
   kill (getpid (), signo);
+#else
+  exit(3);
+#endif
 }
 
 
@@ -2081,6 +2089,31 @@ scan_prog_file (prog_name, which_pass)
   if (nm_file_name == 0)
     fatal ("cannot find `nm'");
 
+#ifdef USE_POPEN
+  p = (char*) xmalloc (strlen (nm_file_name)
+                       + strlen (NM_FLAGS)
+                       + strlen (prog_name)
+                       + 10);
+  strcpy (p, nm_file_name);
+  strcat (p, " ");
+  if (NM_FLAGS[0] != '\0')
+    {
+      strcat (p, NM_FLAGS);
+      strcat (p, " ");
+    }
+  strcat (p, prog_name);
+  inf = popen (p, "r");
+  if (inf == NULL)
+    fatal_perror ("can't popen `%s'", p);
+
+  /* Trace if needed.  */
+  if (vflag)
+    fprintf (stderr, " %s\n", p);
+
+  free (p);
+  fflush (stdout);
+  fflush (stderr);
+#else
   nm_argv[argc++] = nm_file_name;
   if (NM_FLAGS[0] != '\0')
     nm_argv[argc++] = NM_FLAGS;
@@ -2142,6 +2175,7 @@ scan_prog_file (prog_name, which_pass)
 
   if (debug)
     fprintf (stderr, "\nnm output with constructors/destructors.\n");
+#endif
 
   /* Read each line of nm output.  */
   while (fgets (buf, sizeof buf, inf) != (char *) 0)
@@ -2215,7 +2249,11 @@ scan_prog_file (prog_name, which_pass)
   if (fclose (inf) != 0)
     fatal_perror ("fclose");
 
+#ifdef USE_POPEN
+  pclose (inf);
+#else
   do_wait (nm_file_name);
+#endif
 
   signal (SIGINT,  int_handler);
 #ifdef SIGQUIT
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/combine.c gcc-3.3.6-m68hc1x/gcc/combine.c
--- gcc-3.3.6/gcc/combine.c	Tue Jan 18 09:39:05 2005
+++ gcc-3.3.6-m68hc1x/gcc/combine.c	Sat Nov  5 19:17:25 2005
@@ -6553,7 +6553,7 @@ make_compound_operation (x, in_code)
      address, we stay there.  If we have a comparison, set to COMPARE,
      but once inside, go back to our default of SET.  */
 
-  next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
+  next_code = (code == MEM /* SCz: || code == PLUS || code == MINUS */ ? MEM
 	       : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
 		  && XEXP (x, 1) == const0_rtx) ? COMPARE
 	       : in_code == COMPARE ? SET : in_code);
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/config/divmod.c gcc-3.3.6-m68hc1x/gcc/config/divmod.c
--- gcc-3.3.6/gcc/config/divmod.c	Thu Nov 30 09:25:58 2000
+++ gcc-3.3.6-m68hc1x/gcc/config/divmod.c	Sat Nov  5 19:17:25 2005
@@ -1,4 +1,5 @@
-long udivmodsi4 ();
+extern unsigned long __udivmodsi4 (unsigned long num, unsigned long den,
+                                   unsigned long *mod);
 
 long
 __divsi3 (long a, long b)
@@ -18,7 +19,7 @@ __divsi3 (long a, long b)
       neg = !neg;
     }
 
-  res = udivmodsi4 (a, b, 0);
+  res = __udivmodsi4 (a, b, 0);
 
   if (neg)
     res = -res;
@@ -41,7 +42,7 @@ __modsi3 (long a, long b)
   if (b < 0)
     b = -b;
 
-  res = udivmodsi4 (a, b, 1);
+  __udivmodsi4 (a, b, (unsigned long*) &res);
 
   if (neg)
     res = -res;
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/config/m68hc11/m68hc11-crt0.S gcc-3.3.6-m68hc1x/gcc/config/m68hc11/m68hc11-crt0.S
--- gcc-3.3.6/gcc/config/m68hc11/m68hc11-crt0.S	Wed Aug 14 09:32:52 2002
+++ gcc-3.3.6-m68hc1x/gcc/config/m68hc11/m68hc11-crt0.S	Sat Nov  5 19:17:25 2005
@@ -79,7 +79,7 @@ _start:
 ;; 
 ;;	int __premain(void);
 ;; 
-	jsr	__premain
+	bsr	__premain
 	
 ;;
 ;; 
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/config/m68hc11/m68hc11-protos.h gcc-3.3.6-m68hc1x/gcc/config/m68hc11/m68hc11-protos.h
--- gcc-3.3.6/gcc/config/m68hc11/m68hc11-protos.h	Sat Apr 12 23:53:41 2003
+++ gcc-3.3.6-m68hc1x/gcc/config/m68hc11/m68hc11-protos.h	Sun Jan 22 20:57:38 2006
@@ -1,5 +1,6 @@
 /* Prototypes for exported functions defined in m68hc11.c
-   Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+   Copyright (C) 1999, 2000, 2001, 2002, 2003,
+   2005, 2006 Free Software Foundation, Inc.
    Contributed by Stephane Carrez (stcarrez@nerim.fr)
 
 This file is part of GNU CC.
@@ -24,7 +25,7 @@ extern int m68hc11_override_options PARA
 extern int m68hc11_optimization_options PARAMS((int,int));
 extern void m68hc11_conditional_register_usage PARAMS((void));
 extern int hard_regno_mode_ok PARAMS((int, enum machine_mode));
-extern int m68hc11_hard_regno_rename_ok PARAMS((int, int));
+extern int m68hc11_hard_regno_rename_ok PARAMS((int, int, int));
 
 extern int m68hc11_total_frame_size PARAMS((void));
 extern int m68hc11_initial_frame_pointer_offset PARAMS((void));
@@ -105,6 +106,7 @@ extern int go_if_legitimate_address2 PAR
 extern int reg_or_indexed_operand PARAMS((rtx,enum machine_mode));
 extern int tst_operand PARAMS((rtx,enum machine_mode));
 extern int cmp_operand PARAMS((rtx,enum machine_mode));
+extern int nonimmediate_noinc_operand PARAMS((rtx,enum machine_mode));
 extern int memory_indexed_operand PARAMS((rtx, enum machine_mode));
 
 extern void m68hc11_split_logical PARAMS((enum machine_mode, int, rtx*));
@@ -147,6 +149,7 @@ extern void m68hc11_function_epilogue PA
 
 extern int m68hc11_is_far_symbol PARAMS((rtx));
 extern int m68hc11_is_trap_symbol PARAMS((rtx));
+extern int m68hc11_page0_symbol_p (rtx x);
 
 #endif /* TREE_CODE */
 
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/config/m68hc11/m68hc11.c gcc-3.3.6-m68hc1x/gcc/config/m68hc11/m68hc11.c
--- gcc-3.3.6/gcc/config/m68hc11/m68hc11.c	Sat Apr 12 23:53:41 2003
+++ gcc-3.3.6-m68hc1x/gcc/config/m68hc11/m68hc11.c	Sun Jan 22 21:12:58 2006
@@ -1,21 +1,22 @@
 /* Subroutines for code generation on Motorola 68HC11 and 68HC12.
-   Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+   Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+   Free Software Foundation, Inc.
    Contributed by Stephane Carrez (stcarrez@nerim.fr)
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.
 
@@ -70,6 +71,7 @@ static int autoinc_mode PARAMS ((rtx));
 static int m68hc11_make_autoinc_notes PARAMS ((rtx*, void*));
 static int m68hc11_auto_inc_p PARAMS ((rtx));
 static tree m68hc11_handle_fntype_attribute PARAMS ((tree *, tree, tree, int, bool *));
+static tree m68hc11_handle_page0_attribute PARAMS ((tree *, tree, tree, int, bool *));
 const struct attribute_spec m68hc11_attribute_table[];
 
 void create_regs_rtx PARAMS ((void));
@@ -79,6 +81,7 @@ static void m68hc11_output_function_epil
 static void m68hc11_asm_out_constructor PARAMS ((rtx, int));
 static void m68hc11_asm_out_destructor PARAMS ((rtx, int));
 static void m68hc11_encode_section_info PARAMS((tree, int));
+static const char *m68hc11_strip_name_encoding (const char* str);
 
 /* Must be set to 1 to produce debug messages.  */
 int debug_m6811 = 0;
@@ -129,6 +132,16 @@ unsigned char m68hc11_reg_valid_for_inde
    This is 1 for 68HC11 and 0 for 68HC12.  */
 int m68hc11_sp_correction;
 
+#define ADDR_STRICT       0x01  /* Accept only registers in class A_REGS  */
+#define ADDR_INCDEC       0x02  /* Post/Pre inc/dec */
+#define ADDR_INDEXED      0x04  /* D-reg index */
+#define ADDR_OFFSET       0x08
+#define ADDR_INDIRECT     0x10  /* Accept (mem (mem ...)) for [n,X] */
+#define ADDR_CONST        0x20  /* Accept const and symbol_ref  */
+
+int m68hc11_addr_mode;
+int m68hc11_mov_addr_mode;
+
 /* Comparison operands saved by the "tstxx" and "cmpxx" expand patterns.  */
 rtx m68hc11_compare_op0;
 rtx m68hc11_compare_op1;
@@ -227,6 +240,9 @@ static int nb_soft_regs;
 #undef TARGET_ENCODE_SECTION_INFO
 #define TARGET_ENCODE_SECTION_INFO  m68hc11_encode_section_info
 
+#undef TARGET_STRIP_NAME_ENCODING
+#define TARGET_STRIP_NAME_ENCODING m68hc11_strip_name_encoding
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 int
@@ -264,6 +280,8 @@ m68hc11_override_options ()
       m68hc11_reg_valid_for_base[HARD_Z_REGNUM] = 1;
       m68hc11_sp_correction = 1;
       m68hc11_tmp_regs_class = D_REGS;
+      m68hc11_addr_mode = ADDR_OFFSET;
+      m68hc11_mov_addr_mode = 0;
       if (m68hc11_soft_reg_count == 0 && !TARGET_M6812)
 	m68hc11_soft_reg_count = "4";
     }
@@ -283,6 +301,10 @@ m68hc11_override_options ()
       m68hc11_reg_valid_for_index[HARD_D_REGNUM] = 1;
       m68hc11_sp_correction = 0;
       m68hc11_tmp_regs_class = TMP_REGS;
+      m68hc11_addr_mode = ADDR_INDIRECT | ADDR_OFFSET | ADDR_CONST
+        | (TARGET_AUTO_INC_DEC ? ADDR_INCDEC : 0);
+      m68hc11_mov_addr_mode = ADDR_OFFSET | ADDR_CONST
+        | (TARGET_AUTO_INC_DEC ? ADDR_INCDEC : 0);
       target_flags &= ~MASK_M6811;
       target_flags |= MASK_NO_DIRECT_MODE;
       if (m68hc11_soft_reg_count == 0)
@@ -316,7 +338,7 @@ m68hc11_conditional_register_usage ()
   /* For 68HC12, the Z register emulation is not necessary when the
      frame pointer is not used.  The frame pointer is eliminated and
      replaced by the stack register (which is a BASE_REG_CLASS).  */
-  if (TARGET_M6812 && flag_omit_frame_pointer && optimize)
+  if (TARGET_M6812 && flag_omit_frame_pointer && optimize && 0)
     {
       fixed_regs[HARD_Z_REGNUM] = 1;
     }
@@ -385,8 +407,9 @@ hard_regno_mode_ok (regno, mode)
 }
 
 int
-m68hc11_hard_regno_rename_ok (reg1, reg2)
+m68hc11_hard_regno_rename_ok (reg1, reg2, mode)
      int reg1, reg2;
+     int mode;
 {
   /* Don't accept renaming to Z register.  We will replace it to
      X,Y or D during machine reorg pass.  */
@@ -398,6 +421,11 @@ m68hc11_hard_regno_rename_ok (reg1, reg2
       && (D_REGNO_P (reg1) || X_REGNO_P (reg1)))
     return 0;
 
+  /* Don't rename D as if it holds a 8-bit value, the code will be
+     bigger.  */
+  if (mode == QImode && D_REGNO_P (reg1))
+    return 0;
+
   return 1;
 }
 
@@ -522,21 +550,25 @@ preferred_reload_class (operand, class)
    For 68hc11:  n,r    with n in [0..255] and r in A_REGS class
    For 68hc12:  n,r    no constraint on the constant, r in A_REGS class.  */
 static int
-register_indirect_p (operand, mode, strict)
-     rtx operand;
-     enum machine_mode mode;
-     int strict;
+register_indirect_p (rtx operand, enum machine_mode mode, int addr_mode)
 {
   rtx base, offset;
 
   switch (GET_CODE (operand))
     {
+    case MEM:
+      if ((addr_mode & ADDR_INDIRECT) && GET_MODE_SIZE (mode) <= 2)
+        return register_indirect_p (XEXP (operand, 0), mode,
+                                    addr_mode & (ADDR_STRICT | ADDR_OFFSET));
+      return 0;
+
     case POST_INC:
     case PRE_INC:
     case POST_DEC:
     case PRE_DEC:
-      if (TARGET_M6812 && TARGET_AUTO_INC_DEC)
-	return register_indirect_p (XEXP (operand, 0), mode, strict);
+      if (addr_mode & ADDR_INCDEC)
+	return register_indirect_p (XEXP (operand, 0), mode,
+                                    addr_mode & ADDR_STRICT);
       return 0;
 
     case PLUS:
@@ -548,36 +580,57 @@ register_indirect_p (operand, mode, stri
       if (GET_CODE (offset) == MEM)
 	return 0;
 
+      /* Indexed addressing mode with 2 registers.  */
+      if (GET_CODE (base) == REG && GET_CODE (offset) == REG)
+        {
+          if (!(addr_mode & ADDR_INDEXED))
+            return 0;
+
+          addr_mode &= ADDR_STRICT;
+          if (REGNO_OK_FOR_BASE_P2 (REGNO (base), addr_mode)
+              && REGNO_OK_FOR_INDEX_P2 (REGNO (offset), addr_mode))
+            return 1;
+
+          if (REGNO_OK_FOR_BASE_P2 (REGNO (offset), addr_mode)
+              && REGNO_OK_FOR_INDEX_P2 (REGNO (base), addr_mode))
+            return 1;
+
+          return 0;
+        }
+
+      if (!(addr_mode & ADDR_OFFSET))
+        return 0;
+
       if (GET_CODE (base) == REG)
 	{
-	  if (!VALID_CONSTANT_OFFSET_P (offset, mode))
+          if (!VALID_CONSTANT_OFFSET_P (offset, mode))
 	    return 0;
 
-	  if (strict == 0)
+	  if (!(addr_mode & ADDR_STRICT))
 	    return 1;
 
-	  return REGNO_OK_FOR_BASE_P2 (REGNO (base), strict);
+	  return REGNO_OK_FOR_BASE_P2 (REGNO (base), 1);
 	}
+
       if (GET_CODE (offset) == REG)
 	{
 	  if (!VALID_CONSTANT_OFFSET_P (base, mode))
 	    return 0;
 
-	  if (strict == 0)
+	  if (!(addr_mode & ADDR_STRICT))
 	    return 1;
 
-	  return REGNO_OK_FOR_BASE_P2 (REGNO (offset), strict);
+	  return REGNO_OK_FOR_BASE_P2 (REGNO (offset), 1);
 	}
       return 0;
 
     case REG:
-      return REGNO_OK_FOR_BASE_P2 (REGNO (operand), strict);
+      return REGNO_OK_FOR_BASE_P2 (REGNO (operand), addr_mode & ADDR_STRICT);
 
     case CONST_INT:
-      if (TARGET_M6811)
-        return 0;
-
-      return VALID_CONSTANT_OFFSET_P (operand, mode);
+      if (addr_mode & ADDR_CONST)
+        return VALID_CONSTANT_OFFSET_P (operand, mode);
+      return 0;
 
     default:
       return 0;
@@ -592,6 +645,7 @@ m68hc11_small_indexed_indirect_p (operan
      enum machine_mode mode;
 {
   rtx base, offset;
+  int addr_mode;
 
   if (GET_CODE (operand) == REG && reload_in_progress
       && REGNO (operand) >= FIRST_PSEUDO_REGISTER
@@ -611,7 +665,8 @@ m68hc11_small_indexed_indirect_p (operan
   if (PUSH_POP_ADDRESS_P (operand))
     return 1;
 
-  if (!register_indirect_p (operand, mode, reload_completed))
+  addr_mode = m68hc11_mov_addr_mode | (reload_completed ? ADDR_STRICT : 0);
+  if (!register_indirect_p (operand, mode, addr_mode))
     return 0;
 
   if (TARGET_M6812 && GET_CODE (operand) == PLUS
@@ -654,12 +709,21 @@ m68hc11_register_indirect_p (operand, mo
      rtx operand;
      enum machine_mode mode;
 {
+  int addr_mode;
+
+  if (GET_CODE (operand) == REG && reload_in_progress
+      && REGNO (operand) >= FIRST_PSEUDO_REGISTER
+      && reg_equiv_memory_loc[REGNO (operand)])
+    {
+      operand = reg_equiv_memory_loc[REGNO (operand)];
+      operand = eliminate_regs (operand, 0, NULL_RTX);
+    }
   if (GET_CODE (operand) != MEM)
     return 0;
 
   operand = XEXP (operand, 0);
-  return register_indirect_p (operand, mode,
-                              (reload_completed | reload_in_progress));
+  addr_mode = m68hc11_addr_mode | (reload_completed ? ADDR_STRICT : 0);
+  return register_indirect_p (operand, mode, addr_mode);
 }
 
 static int
@@ -668,6 +732,8 @@ go_if_legitimate_address_internal (opera
      enum machine_mode mode;
      int strict;
 {
+  int addr_mode;
+
   if (CONSTANT_ADDRESS_P (operand) && TARGET_M6812)
     {
       /* Reject the global variables if they are too wide.  This forces
@@ -677,7 +743,8 @@ go_if_legitimate_address_internal (opera
 
       return 1;
     }
-  if (register_indirect_p (operand, mode, strict))
+  addr_mode = m68hc11_addr_mode | (strict ? ADDR_STRICT : 0);
+  if (register_indirect_p (operand, mode, addr_mode))
     {
       return 1;
     }
@@ -930,6 +997,27 @@ cmp_operand (operand, mode)
   return general_operand (operand, mode);
 }
 
+/* Predicate for nonimmediate operands but which rejects the
+   auto-increment/decrement modes.  We must use this predicate
+   for operand 0 (and sometimes operand 1) when an insn can have
+   an operand that would create a RELOAD_OTHER in which a reload
+   part (RELOAD_FOR_OUTPUT_ADDRESS) could be created.  When this
+   happens, the RELOAD_FOR_OUTPUT_ADDRESS is emitted after the RELOAD_OTHER
+   and this will not be valid.  */
+int
+nonimmediate_noinc_operand (operand, mode)
+     rtx operand;
+     enum machine_mode mode;
+{
+  if (GET_CODE (operand) == MEM)
+    {
+      rtx addr = XEXP (operand, 0);
+      if (m68hc11_auto_inc_p (addr))
+	return 0;
+    }
+  return nonimmediate_operand (operand, mode);
+}
+
 int
 non_push_operand (operand, mode)
      rtx operand;
@@ -944,6 +1032,43 @@ non_push_operand (operand, mode)
 }
 
 int
+splitable_operand (operand, mode)
+     rtx operand;
+     enum machine_mode mode;
+{
+  if (general_operand (operand, mode) == 0)
+    return 0;
+
+  if (push_operand (operand, mode) == 1)
+    return 0;
+
+  /* Reject a (MEM (MEM X)) because the patterns that use non_push_operand
+     need to split such addresses to access the low and high part but it
+     is not possible to express a valid address for the low part.  */
+  if (mode != QImode && GET_CODE (operand) == MEM
+      && GET_CODE (XEXP (operand, 0)) == MEM)
+    return 0;
+  return 1;
+}
+
+int
+push_or_splitable_operand (operand, mode)
+     rtx operand;
+     enum machine_mode mode;
+{
+  if (general_operand (operand, mode) == 0)
+    return 0;
+
+  /* Reject a (MEM (MEM X)) because the patterns that use non_push_operand
+     need to split such addresses to access the low and high part but it
+     is not possible to express a valid address for the low part.  */
+  if (mode != QImode && GET_CODE (operand) == MEM
+      && GET_CODE (XEXP (operand, 0)) == MEM)
+    return 0;
+  return 1;
+}
+
+int
 reg_or_some_mem_operand (operand, mode)
      rtx operand;
      enum machine_mode mode;
@@ -951,6 +1076,7 @@ reg_or_some_mem_operand (operand, mode)
   if (GET_CODE (operand) == MEM)
     {
       rtx op = XEXP (operand, 0);
+      int addr_mode;
 
       if (symbolic_memory_operand (op, mode))
 	return 1;
@@ -958,10 +1084,20 @@ reg_or_some_mem_operand (operand, mode)
       if (IS_STACK_PUSH (operand))
 	return 1;
 
-      if (m68hc11_register_indirect_p (operand, mode))
-	return 1;
+      if (GET_CODE (operand) == REG && reload_in_progress
+          && REGNO (operand) >= FIRST_PSEUDO_REGISTER
+          && reg_equiv_memory_loc[REGNO (operand)])
+         {
+            operand = reg_equiv_memory_loc[REGNO (operand)];
+            operand = eliminate_regs (operand, 0, NULL_RTX);
+         }
+      if (GET_CODE (operand) != MEM)
+         return 0;
 
-      return 0;
+      operand = XEXP (operand, 0);
+      addr_mode = m68hc11_addr_mode | (reload_completed ? ADDR_STRICT : 0);
+      addr_mode &= ~ADDR_INDIRECT;
+      return register_indirect_p (operand, mode, addr_mode);
     }
 
   return register_operand (operand, mode);
@@ -987,18 +1123,23 @@ m68hc11_indirect_p (operand, mode)
      rtx operand;
      enum machine_mode mode;
 {
-  if (GET_CODE (operand) == MEM)
+  if (GET_CODE (operand) == MEM && GET_MODE (operand) == mode)
     {
       rtx op = XEXP (operand, 0);
+      int addr_mode;
+
+      if (m68hc11_page0_symbol_p (op))
+        return 1;
 
       if (symbolic_memory_operand (op, mode))
-	return 0;
+	return TARGET_M6812;
 
       if (reload_in_progress)
         return 1;
 
       operand = XEXP (operand, 0);
-      return register_indirect_p (operand, mode, reload_completed);
+      addr_mode = m68hc11_addr_mode | (reload_completed ? ADDR_STRICT : 0);
+      return register_indirect_p (operand, mode, addr_mode);
     }
   return 0;
 }
@@ -1234,6 +1375,31 @@ m68hc11_initialize_trampoline (tramp, fn
 
 /* Declaration of types.  */
 
+/* Handle an "tiny_data" attribute; arguments as in
+   struct attribute_spec.handler.  */
+static tree
+m68hc11_handle_page0_attribute (node, name, args, flags, no_add_attrs)
+     tree *node;
+     tree name;
+     tree args ATTRIBUTE_UNUSED;
+     int flags ATTRIBUTE_UNUSED;
+     bool *no_add_attrs;
+{
+  tree decl = *node;
+
+  if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
+    {
+      DECL_SECTION_NAME (decl) = build_string (6, ".page0");
+    }
+  else
+    {
+      warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
+      *no_add_attrs = true;
+    }
+
+  return NULL_TREE;
+}
+
 const struct attribute_spec m68hc11_attribute_table[] =
 {
   /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
@@ -1241,6 +1407,7 @@ const struct attribute_spec m68hc11_attr
   { "trap",      0, 0, false, true,  true,  m68hc11_handle_fntype_attribute },
   { "far",       0, 0, false, true,  true,  m68hc11_handle_fntype_attribute },
   { "near",      0, 0, false, true,  true,  m68hc11_handle_fntype_attribute },
+  { "page0",     0, 0, false, false, false, m68hc11_handle_page0_attribute },
   { NULL,        0, 0, false, false, false, NULL }
 };
 
@@ -1271,6 +1438,52 @@ m68hc11_handle_fntype_attribute (node, n
 
   return NULL_TREE;
 }
+/* Undo the effects of the above.  */
+
+static const char *
+m68hc11_strip_name_encoding (str)
+     const char *str;
+{
+  return str + (*str == '*' || *str == '@' || *str == '&');
+}
+
+static void
+m68hc11_encode_label (tree decl)
+{
+  const char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
+  int len = strlen (str);
+  char *newstr = alloca (len + 2);
+
+  newstr[0] = '@';
+  strcpy (&newstr[1], str);
+
+  XSTR (XEXP (DECL_RTL (decl), 0), 0) = ggc_alloc_string (newstr, len + 1);
+}
+
+/* Return 1 if this is a symbol in page0  */
+int
+m68hc11_page0_symbol_p (rtx x)
+{
+  switch (GET_CODE (x))
+    {
+    case SYMBOL_REF:
+      return XSTR (x, 0) != 0 && XSTR (x, 0)[0] == '@';
+
+    case CONST:
+      return m68hc11_page0_symbol_p (XEXP (x, 0));
+
+    case PLUS:
+      if (!m68hc11_page0_symbol_p (XEXP (x, 0)))
+        return 0;
+
+      return GET_CODE (XEXP (x, 1)) == CONST_INT
+        && INTVAL (XEXP (x, 1)) < 256
+        && INTVAL (XEXP (x, 1)) >= 0;
+
+    default:
+      return 0;
+    }
+}
 
 /* We want to recognize trap handlers so that we handle calls to traps
    in a special manner (by issuing the trap).  This information is stored
@@ -1286,6 +1499,13 @@ m68hc11_encode_section_info (decl, first
   int is_far = 0;
   rtx rtl;
   
+  if (TREE_CODE (decl) == VAR_DECL)
+    {
+      if (lookup_attribute ("page0", DECL_ATTRIBUTES (decl)) != 0)
+        m68hc11_encode_label (decl);
+      return;
+    }
+
   if (TREE_CODE (decl) != FUNCTION_DECL)
     return;
 
@@ -1372,15 +1592,19 @@ m68hc11_initial_elimination_offset (from
   /* For a trap handler, we must take into account the registers which
      are pushed on the stack during the trap (except the PC).  */
   func_attr = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl));
+  current_function_interrupt = lookup_attribute ("interrupt",
+						 func_attr) != NULL_TREE;
+  trap_handler = lookup_attribute ("trap", func_attr) != NULL_TREE;
 
   if (lookup_attribute ("far", func_attr) != 0)
     current_function_far = 1;
   else if (lookup_attribute ("near", func_attr) != 0)
     current_function_far = 0;
   else
-    current_function_far = TARGET_LONG_CALLS != 0;
+    current_function_far = (TARGET_LONG_CALLS != 0
+                            && !current_function_interrupt
+                            && !trap_handler);
 
-  trap_handler = lookup_attribute ("trap", func_attr) != NULL_TREE;
   if (trap_handler && from == ARG_POINTER_REGNUM)
     size = 7;
 
@@ -1679,7 +1903,9 @@ expand_prologue ()
   else if (lookup_attribute ("near", func_attr) != NULL_TREE)
     current_function_far = 0;
   else
-    current_function_far = TARGET_LONG_CALLS != 0;
+    current_function_far = (TARGET_LONG_CALLS != 0
+                            && !current_function_interrupt
+                            && !current_function_trap);
 
   /* Get the scratch register to build the frame and push registers.
      If the first argument is a 32-bit quantity, the D+X registers
@@ -2014,6 +2240,14 @@ m68hc11_gen_highpart (mode, x)
 	{
 	  return gen_int_mode (val >> 16, HImode);
 	}
+      else if (mode == SImode)
+       {
+#if HOST_BITS_PER_WIDE_INT > 32
+         return gen_int_mode (val >> 32, SImode);
+#else
+         return (val >= 0) ? const0_rtx : constm1_rtx;
+#endif
+       }
     }
   if (mode == QImode && D_REG_P (x))
     return gen_rtx (REG, mode, HARD_A_REGNUM);
@@ -2307,7 +2541,21 @@ print_operand (file, op, letter)
 	    abort ();
 	  break;
 
+        case MEM:
+          if (TARGET_M6812)
+            {
+              fprintf (file, "[");
+              print_operand_address (file, XEXP (base, 0));
+              fprintf (file, "]");
+            }
+          else
+            abort ();
+          break;
+
 	default:
+          if (m68hc11_page0_symbol_p (base))
+            fprintf (file, "*");
+
 	  output_address (base);
 	  break;
 	}
@@ -2349,7 +2597,7 @@ print_operand (file, op, letter)
 }
 
 /* Returns true if the operand 'op' must be printed with parenthesis
-   arround it.  This must be done only if there is a symbol whose name
+   around it.  This must be done only if there is a symbol whose name
    is a processor register.  */
 static int
 must_parenthesize (op)
@@ -2903,15 +3151,7 @@ m68hc11_split_move (to, from, scratch)
   high_to = m68hc11_gen_highpart (mode, to);
 
   low_from = m68hc11_gen_lowpart (mode, from);
-  if (mode == SImode && GET_CODE (from) == CONST_INT)
-    {
-      if (INTVAL (from) >= 0)
-	high_from = const0_rtx;
-      else
-	high_from = constm1_rtx;
-    }
-  else
-    high_from = m68hc11_gen_highpart (mode, from);
+  high_from = m68hc11_gen_highpart (mode, from);
 
   if (offset)
     {
@@ -3104,26 +3344,8 @@ m68hc11_split_logical (mode, code, opera
   low[2] = m68hc11_gen_lowpart (mode, operands[2]);
 
   high[0] = m68hc11_gen_highpart (mode, operands[0]);
-
-  if (mode == SImode && GET_CODE (operands[1]) == CONST_INT)
-    {
-      if (INTVAL (operands[1]) >= 0)
-	high[1] = const0_rtx;
-      else
-	high[1] = constm1_rtx;
-    }
-  else
-    high[1] = m68hc11_gen_highpart (mode, operands[1]);
-
-  if (mode == SImode && GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) >= 0)
-	high[2] = const0_rtx;
-      else
-	high[2] = constm1_rtx;
-    }
-  else
-    high[2] = m68hc11_gen_highpart (mode, operands[2]);
+  high[1] = m68hc11_gen_highpart (mode, operands[1]);
+  high[2] = m68hc11_gen_highpart (mode, operands[2]);
 
   low[3] = operands[3];
   high[3] = operands[3];
@@ -3236,10 +3458,13 @@ m68hc11_gen_movhi (insn, operands)
 
   if (TARGET_M6812)
     {
-      if (IS_STACK_PUSH (operands[0]) && H_REG_P (operands[1]))
+      rtx from = operands[1];
+      rtx to = operands[0];
+
+      if (IS_STACK_PUSH (to) && H_REG_P (from))
 	{
           cc_status = cc_prev_status;
-	  switch (REGNO (operands[1]))
+	  switch (REGNO (from))
 	    {
 	    case HARD_X_REGNUM:
 	    case HARD_Y_REGNUM:
@@ -3247,17 +3472,17 @@ m68hc11_gen_movhi (insn, operands)
 	      output_asm_insn ("psh%1", operands);
 	      break;
             case HARD_SP_REGNUM:
-              output_asm_insn ("sts\t-2,sp", operands);
+              output_asm_insn ("sts\t2,-sp", operands);
               break;
 	    default:
 	      abort ();
 	    }
 	  return;
 	}
-      if (IS_STACK_POP (operands[1]) && H_REG_P (operands[0]))
+      if (IS_STACK_POP (from) && H_REG_P (to))
 	{
           cc_status = cc_prev_status;
-	  switch (REGNO (operands[0]))
+	  switch (REGNO (to))
 	    {
 	    case HARD_X_REGNUM:
 	    case HARD_Y_REGNUM:
@@ -3278,17 +3503,6 @@ m68hc11_gen_movhi (insn, operands)
 	{
 	  if (SP_REG_P (operands[0]))
 	    output_asm_insn ("lds\t%1", operands);
-	  else if (0 /* REG_WAS_0 note is boggus;  don't rely on it.  */
-                   && !D_REG_P (operands[0])
-                   && GET_CODE (operands[1]) == CONST_INT
-                   && (INTVAL (operands[1]) == 1 || INTVAL (operands[1]) == -1)
-                   && find_reg_note (insn, REG_WAS_0, 0))
-            {
-              if (INTVAL (operands[1]) == 1)
-                output_asm_insn ("in%0", operands);
-              else
-                output_asm_insn ("de%0", operands);
-            }
 	  else
 	    output_asm_insn ("ld%0\t%1", operands);
 	}
@@ -3299,11 +3513,52 @@ m68hc11_gen_movhi (insn, operands)
 	  else
 	    output_asm_insn ("st%1\t%0", operands);
 	}
+
+      /* The 68hc12 does not support (MEM:HI (MEM:HI)) with the movw
+         instruction.  We have to use a scratch register as temporary location.
+         Trying to use a specific pattern or constrain failed.  */
+      else if (GET_CODE (to) == MEM && GET_CODE (XEXP (to, 0)) == MEM)
+        {
+          rtx ops[4];
+
+          ops[0] = to;
+          ops[2] = from;
+          ops[3] = 0;
+          if (dead_register_here (insn, d_reg))
+            ops[1] = d_reg;
+          else if (dead_register_here (insn, ix_reg))
+            ops[1] = ix_reg;
+          else if (dead_register_here (insn, iy_reg))
+            ops[1] = iy_reg;
+          else
+            {
+              ops[1] = d_reg;
+              ops[3] = d_reg;
+              output_asm_insn ("psh%3", ops);
+            }
+
+          ops[0] = to;
+          ops[2] = from;
+          output_asm_insn ("ld%1\t%2", ops);
+          output_asm_insn ("st%1\t%0", ops);
+          if (ops[3])
+            output_asm_insn ("pul%3", ops);
+        }
+
+      /* Use movw for non-null constants or when we are clearing
+         a volatile memory reference.  However, this is possible
+         only if the memory reference has a small offset or is an
+         absolute address.  */
+      else if (GET_CODE (from) == CONST_INT
+               && INTVAL (from) == 0
+               && (MEM_VOLATILE_P (to) == 0
+                   || m68hc11_small_indexed_indirect_p (to, HImode) == 0))
+        {
+          output_asm_insn ("clr\t%h0", operands);
+          output_asm_insn ("clr\t%b0", operands);
+        }
       else
 	{
-	  rtx from = operands[1];
-	  rtx to = operands[0];
-
 	  if ((m68hc11_register_indirect_p (from, GET_MODE (from))
 	       && !m68hc11_small_indexed_indirect_p (from, GET_MODE (from)))
 	      || (m68hc11_register_indirect_p (to, GET_MODE (to))
@@ -3320,6 +3575,7 @@ m68hc11_gen_movhi (insn, operands)
 		  ops[0] = to;
 		  ops[1] = operands[2];
 		  m68hc11_gen_movhi (insn, ops);
+                  return;
 		}
 	      else
 		{
@@ -3327,19 +3583,11 @@ m68hc11_gen_movhi (insn, operands)
                   fatal_insn ("move insn not handled", insn);
 		}
 	    }
-	  else
-	    {
-	      if (GET_CODE (from) == CONST_INT && INTVAL (from) == 0)
-		{
-		  output_asm_insn ("clr\t%h0", operands);
-		  output_asm_insn ("clr\t%b0", operands);
-		}
-	      else
-		{
-                  m68hc11_notice_keep_cc (operands[0]);
-		  output_asm_insn ("movw\t%1,%0", operands);
-		}
-	    }
+          else
+            {
+              m68hc11_notice_keep_cc (operands[0]);
+              output_asm_insn ("movw\t%1,%0", operands);
+            }
 	}
       return;
     }
@@ -3472,16 +3720,6 @@ m68hc11_gen_movhi (insn, operands)
 	      cc_status = cc_prev_status;
 	      output_asm_insn ("tsx", operands);
 	    }
-	  else if (0 /* REG_WAS_0 note is boggus;  don't rely on it.  */
-                   && GET_CODE (operands[1]) == CONST_INT
-                   && (INTVAL (operands[1]) == 1 || INTVAL (operands[1]) == -1)
-                   && find_reg_note (insn, REG_WAS_0, 0))
-            {
-              if (INTVAL (operands[1]) == 1)
-                output_asm_insn ("in%0", operands);
-              else
-                output_asm_insn ("de%0", operands);
-            }
 	  else
 	    {
 	      output_asm_insn ("ldx\t%1", operands);
@@ -3530,16 +3768,6 @@ m68hc11_gen_movhi (insn, operands)
 	      cc_status = cc_prev_status;
 	      output_asm_insn ("tsy", operands);
 	    }
-	  else if (0 /* REG_WAS_0 note is boggus;  don't rely on it.  */
-                   && GET_CODE (operands[1]) == CONST_INT
-                   && (INTVAL (operands[1]) == 1 || INTVAL (operands[1]) == -1)
-                   && find_reg_note (insn, REG_WAS_0, 0))
-            {
-              if (INTVAL (operands[1]) == 1)
-                output_asm_insn ("in%0", operands);
-              else
-                output_asm_insn ("de%0", operands);
-            }
           else
 	    {
 	      output_asm_insn ("ldy\t%1", operands);
@@ -3689,8 +3917,10 @@ m68hc11_gen_movqi (insn, operands)
 	}
       else if (H_REG_P (operands[0]))
 	{
-	  if (Q_REG_P (operands[0]))
-	    output_asm_insn ("lda%0\t%b1", operands);
+          if (IS_STACK_POP (operands[1]))
+            output_asm_insn ("pul%b0", operands);
+	  else if (Q_REG_P (operands[0]))
+            output_asm_insn ("lda%0\t%b1", operands);
 	  else if (D_REG_P (operands[0]))
 	    output_asm_insn ("ldab\t%b1", operands);
 	  else
@@ -3780,16 +4010,6 @@ m68hc11_gen_movqi (insn, operands)
 		  output_asm_insn ("ldab\t%T0", operands);
 		}
 	    }
-	  else if (0 /* REG_WAS_0 note is boggus;  don't rely on it.  */
-                   && GET_CODE (operands[1]) == CONST_INT
-                   && (INTVAL (operands[1]) == 1 || INTVAL (operands[1]) == -1)
-                   && find_reg_note (insn, REG_WAS_0, 0))
-            {
-              if (INTVAL (operands[1]) == 1)
-                output_asm_insn ("inc%b0", operands);
-              else
-                output_asm_insn ("dec%b0", operands);
-            }          
 	  else if (!DB_REG_P (operands[1]) && !D_REG_P (operands[1])
 		   && !DA_REG_P (operands[1]))
 	    {
@@ -3935,11 +4155,34 @@ m68hc11_gen_movqi (insn, operands)
 	  break;
 
 	case HARD_X_REGNUM:
-	  output_asm_insn ("xgdx\n\tstab\t%b0\n\txgdx", operands);
-	  break;
-
-	case HARD_Y_REGNUM:
-	  output_asm_insn ("xgdy\n\tstab\t%b0\n\txgdy", operands);
+        case HARD_Y_REGNUM:
+	  if (!reg_mentioned_p (operands[1], operands[0]))
+	    {
+              output_asm_insn ("xgd%1\n\tstab\t%b0\n\txgd%1", operands);
+            }
+          else if (TARGET_M6811)
+            {
+              int dead = dead_register_here (insn, d_reg);
+	      output_asm_insn ("st%1\t%t1", operands);
+              if (!dead)
+                output_asm_insn ("psha", operands);
+	      output_asm_insn ("ldaa\t%T1", operands);
+	      output_asm_insn ("staa\t%0", operands);
+              if (!dead)
+                output_asm_insn ("pula", operands);
+	      CC_STATUS_INIT;
+            }
+          else
+            {
+              int dead = dead_register_here (insn, d_reg);
+              if (!dead)
+                output_asm_insn ("psha", operands);
+	      output_asm_insn ("tfr\t%1,a", operands);
+	      output_asm_insn ("staa\t%0", operands);
+              if (!dead)
+                output_asm_insn ("pulb", operands);
+	      CC_STATUS_INIT;
+            }
 	  break;
 
 	default:
@@ -4136,6 +4379,12 @@ m68hc11_notice_update_cc (exp, insn)
       && cc_status.value2
       && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
     cc_status.value2 = 0;
+
+  else if (cc_status.value1 && side_effects_p (cc_status.value1))
+    cc_status.value1 = 0;
+
+  else if (cc_status.value2 && side_effects_p (cc_status.value2))
+    cc_status.value2 = 0;
 }
 
 /* The current instruction does not affect the flags but changes
@@ -4306,8 +4555,10 @@ m68hc11_check_z_replacement (insn, info)
 	{
 	  if ((GET_CODE (src) == REG && REGNO (src) == HARD_Z_REGNUM)
 	      || (GET_CODE (src) == COMPARE &&
-		  (rtx_equal_p (XEXP (src, 0), z_reg)
-		   || rtx_equal_p (XEXP (src, 1), z_reg))))
+		  ((rtx_equal_p (XEXP (src, 0), z_reg)
+                    && H_REG_P (XEXP (src, 1)))
+		   || (rtx_equal_p (XEXP (src, 1), z_reg)
+                       && H_REG_P (XEXP (src, 0))))))
 	    {
 	      if (insn == info->first)
 		{
@@ -4905,7 +5156,7 @@ m68hc11_find_z_replacement (insn, info)
 /* The insn uses the Z register.  Find a replacement register for it
    (either X or Y) and replace it in the insn and the next ones until
    the flow changes or the replacement register is used.  Instructions
-   are emited before and after the Z-block to preserve the value of
+   are emitted before and after the Z-block to preserve the value of
    Z and of the replacement register.  */
 
 static void
@@ -5067,9 +5318,11 @@ m68hc11_z_replacement (insn)
       if (info.save_before_last)
 	save_pos_insn = PREV_INSN (save_pos_insn);
 
-      emit_insn_before (gen_movhi (gen_rtx (REG, HImode, SOFT_Z_REGNUM),
-				   gen_rtx (REG, HImode, info.regno)),
-			save_pos_insn);
+      /* Use emit_insn_after () to ensure the new insn is part of
+         the good basic block.  */
+      emit_insn_after (gen_movhi (gen_rtx (REG, HImode, SOFT_Z_REGNUM),
+                                  gen_rtx (REG, HImode, info.regno)),
+                       PREV_INSN (save_pos_insn));
     }
 
   if (info.must_push_reg && info.last)
@@ -5108,8 +5361,8 @@ m68hc11_z_replacement (insn)
       else
 	dst = gen_rtx (REG, HImode, SOFT_SAVED_XY_REGNUM);
 
-      emit_insn_before (gen_movhi (gen_rtx (REG, HImode, info.regno),
-				   dst), insn);
+      emit_insn_after (gen_movhi (gen_rtx (REG, HImode, info.regno),
+                                  dst), PREV_INSN (insn));
     }
 
 }
@@ -5176,6 +5429,13 @@ m68hc11_reassign_regs (first)
 }
 
 
+/* Machine-dependent reorg pass.
+   Specific optimizations are defined here:
+    - this pass changes the Z register into either X or Y
+      (it preserves X/Y previous values in a memory slot in page0).
+
+   When this pass is finished, the global variable
+   'z_replacement_completed' is set to 2.  */
 void
 m68hc11_reorg (first)
      rtx first;
@@ -5204,7 +5464,7 @@ m68hc11_reorg (first)
   z_replacement_completed = 1;
   m68hc11_reassign_regs (first);
 
-  /* After some splitting, there are some oportunities for CSE pass.
+  /* After some splitting, there are some opportunities for CSE pass.
      This happens quite often when 32-bit or above patterns are split.  */
   if (optimize > 0 && split_done)
     {
@@ -5355,7 +5615,7 @@ m68hc11_address_cost (addr)
       break;
 
     case SYMBOL_REF:
-      cost = 8;
+      cost = m68hc11_page0_symbol_p (addr) ? 0 : 8;
       break;
 
     case LABEL_REF:
@@ -5388,7 +5648,7 @@ m68hc11_address_cost (addr)
 	    break;
 
 	  case SYMBOL_REF:
-	    cost = 8;
+	    cost = m68hc11_page0_symbol_p (addr) ? 0 : 8;
 	    break;
 
 	  case CONST:
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/config/m68hc11/m68hc11.h gcc-3.3.6-m68hc1x/gcc/config/m68hc11/m68hc11.h
--- gcc-3.3.6/gcc/config/m68hc11/m68hc11.h	Tue Jul  8 23:07:33 2003
+++ gcc-3.3.6-m68hc1x/gcc/config/m68hc11/m68hc11.h	Sun Jan 22 19:56:29 2006
@@ -1,22 +1,23 @@
 /* Definitions of target machine for GNU compiler.
    Motorola 68HC11 and 68HC12.
-   Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+   Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004,
+   2005, 2006 Free Software Foundation, Inc.
    Contributed by Stephane Carrez (stcarrez@nerim.fr)
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.
 
@@ -52,7 +53,7 @@ Note:
 #endif
 
 /* We need to tell the linker the target elf format.  Just pass an
-   emulation option.  This can be overriden by -Wl option of gcc.  */
+   emulation option.  This can be overridden by -Wl option of gcc.  */
 #ifndef LINK_SPEC
 #define LINK_SPEC                                               \
 "%{m68hc12:-m m68hc12elf}"                                      \
@@ -277,6 +278,10 @@ extern const struct processor_costs *m68
 /* Define this if most significant word of a multiword number is numbered.  */
 #define WORDS_BIG_ENDIAN 	1
 
+/* Use a MAX_BITS_PER_WORD equivalent to SImode so that
+   several SI patterns can be used (mostly shift & add).  */
+/* #define MAX_BITS_PER_WORD       32  */
+
 /* Width of a word, in units (bytes).  */
 #define UNITS_PER_WORD		2
 
@@ -804,8 +809,8 @@ extern enum reg_class m68hc11_tmp_regs_c
 /* A C expression that is nonzero if hard register number REGNO2 can be
    considered for use as a rename register for REGNO1 */
 
-#define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
-  m68hc11_hard_regno_rename_ok ((REGNO1), (REGNO2))
+#define HARD_REGNO_RENAME_OK(REGNO1,REGNO2,MODE)            \
+  m68hc11_hard_regno_rename_ok ((REGNO1), (REGNO2), (MODE))
 
 /* A C expression whose value is nonzero if pseudos that have been
    assigned to registers of class CLASS would likely be spilled
@@ -874,7 +879,9 @@ extern enum reg_class m68hc11_tmp_regs_c
 		 && VALUE == CONST0_RTX (GET_MODE (VALUE))) : 0) 
 
 /* 'U' represents certain kind of memory indexed operand for 68HC12.
-   and any memory operand for 68HC11.  */
+   and any memory operand for 68HC11.
+   'R' represents indexed addressing mode or access to page0 for 68HC11.
+   For 68HC12, it represents any memory operand.  */
 #define EXTRA_CONSTRAINT(OP, C)                         \
 ((C) == 'U' ? m68hc11_small_indexed_indirect_p (OP, GET_MODE (OP)) \
  : (C) == 'Q' ? m68hc11_symbolic_p (OP, GET_MODE (OP)) \
@@ -963,7 +970,7 @@ extern enum reg_class m68hc11_tmp_regs_c
    followed by "to".  Eliminations of the same "from" register are listed
    in order of preference.
 
-   We have two registers that are eliminated on the 6811. The psuedo arg
+   We have two registers that are eliminated on the 6811. The pseudo arg
    pointer and pseudo frame pointer registers can always be eliminated;
    they are replaced with either the stack or the real frame pointer.  */
 
@@ -1215,7 +1222,7 @@ extern enum reg_class m68hc11_index_reg_
 
 
 /* Internal macro, return 1 if REGNO is a valid base register.  */
-#define REG_VALID_P(REGNO) (1)	/* ? */
+#define REG_VALID_P(REGNO) ((REGNO) >= 0)
 
 extern unsigned char m68hc11_reg_valid_for_base[FIRST_PSEUDO_REGISTER];
 #define REG_VALID_FOR_BASE_P(REGNO) \
@@ -1489,7 +1496,7 @@ extern unsigned char m68hc11_reg_valid_f
    macro is used in only one place: `find_reloads_address' in reload.c.
 
    For M68HC11, we handle large displacements of a base register
-   by splitting the addend accors an addhi3 insn.
+   by splitting the addend across an addhi3 insn.
 
    For M68HC12, the 64K offset range is available.
    */
@@ -1690,7 +1697,7 @@ do {                                    
 
 /* Assembler Commands for Exception Regions.  */
 
-/* Default values provided by GCC should be ok. Assumming that DWARF-2
+/* Default values provided by GCC should be ok. Assuming that DWARF-2
    frame unwind info is ok for this platform.  */
 
 #undef PREFERRED_DEBUGGING_TYPE
@@ -1719,6 +1726,12 @@ do {                                    
 #define IMMEDIATE_PREFIX "#"
 #define GLOBAL_ASM_OP   "\t.globl\t"
 
+/* This is how to output a reference to a user-level label named NAME.
+   `assemble_name' uses this.  */
+#undef  ASM_OUTPUT_LABELREF
+#define ASM_OUTPUT_LABELREF(FILE, NAME) \
+  asm_fprintf (FILE, "%U%s", (*targetm.strip_name_encoding) (NAME))
+
 
 /* Miscellaneous Parameters.  */
 
@@ -1737,8 +1750,10 @@ do {                                    
 {"m68hc11_shift_operator",   {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT}},\
 {"m68hc11_eq_compare_operator", {EQ, NE}},                              \
 {"non_push_operand",         {SUBREG, REG, MEM}},			\
+{"splitable_operand",        {SUBREG, REG, MEM}},			\
 {"reg_or_some_mem_operand",  {SUBREG, REG, MEM}},			\
 {"tst_operand",              {SUBREG, REG, MEM}},			\
+{"nonimmediate_noinc_operand", {SUBREG, REG, MEM}},			\
 {"cmp_operand",              {SUBREG, REG, MEM, SYMBOL_REF, LABEL_REF,	\
 			     CONST_INT, CONST_DOUBLE}},
 
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/config/m68hc11/m68hc11.md gcc-3.3.6-m68hc1x/gcc/config/m68hc11/m68hc11.md
--- gcc-3.3.6/gcc/config/m68hc11/m68hc11.md	Sat Apr 12 23:25:37 2003
+++ gcc-3.3.6-m68hc1x/gcc/config/m68hc11/m68hc11.md	Sun Jan 22 21:06:16 2006
@@ -1,21 +1,22 @@
 ;;- Machine description file for Motorola 68HC11 and 68HC12.
-;;- Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+;;- Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
+;;- Free Software Foundation, Inc.
 ;;- Contributed by Stephane Carrez (stcarrez@nerim.fr)
 
-;; This file is part of GNU CC.
+;; This file is part of GCC.
 
-;; GNU CC is free software; you can redistribute it and/or modify
+;; GCC is free software; you can redistribute it and/or modify
 ;; it under the terms of the GNU General Public License as published by
 ;; the Free Software Foundation; either version 2, or (at your option)
 ;; any later version.
 
-;; GNU CC is distributed in the hope that it will be useful,
+;; GCC is distributed in the hope that it will be useful,
 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ;; GNU General Public License for more details.
 
 ;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
+;; along with GCC; see the file COPYING.  If not, write to
 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
 ;; Boston, MA 02111-1307, USA.
 
@@ -93,7 +94,7 @@
 ;; Operands modifiers:
 ;;
 ;;     %b	Get the low part of the operand (to obtain a QImode)
-;;		This modified must always be used for QImode operations
+;;		This modifier must always be used for QImode operations
 ;;		because a correction must be applied when the operand
 ;;		is a soft register (ex: *ZD1). Otherwise, we generate
 ;;		*ZD1 and this is the high part of the register. For other
@@ -143,7 +144,9 @@
    (A_REGNUM        5)		; A (high part of D)
    (B_REGNUM        6)		; B (low part of D)
    (CC_REGNUM       7)		; Condition code register
-   (SOFT_Z_REGNUM  11)          ; Z soft register
+   (SOFT_TMP_REGNUM 10)         ; TMP soft register
+   (SOFT_Z_REGNUM   11)         ; Z soft register
+   (SOFT_XY_REGNUM  12)         ; XY soft register
 ])
 
 ;;--------------------------------------------------------------------
@@ -247,19 +250,13 @@
 ;; avoid problems with the flow+cse register pass which are made
 ;; after Z register replacement.
 ;;
-(define_insn "tstqi_z_used"
+(define_insn_and_split "tstqi_z_used"
   [(set (cc0)
 	(match_operand:QI 0 "tst_operand" "m"))
    (use (match_operand:HI 1 "hard_reg_operand" "dxy"))
-   (use (reg:HI 11))]
-  ""
-  "#")
-
-(define_split /* "tstqi_z_used" */
-  [(set (cc0)
-	(match_operand:QI 0 "tst_operand" ""))
-   (use (match_operand:HI 1 "hard_reg_operand" ""))
    (use (reg:HI SOFT_Z_REGNUM))]
+  ""
+  "#"
   "z_replacement_completed == 2"
   [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 1))
    (set (match_dup 1) (match_dup 2))
@@ -300,12 +297,24 @@
   [(set (cc0)
 	(compare (match_operand:HI 0 "hard_reg_operand" "")
 		 (match_operand:HI 1 "hard_reg_operand" "")))]
-  "reload_completed"
+  "TARGET_M6811
+   && reload_completed && !(Z_REG_P (operands[0]) || Z_REG_P (operands[1]))"
   [(set (match_dup 2) (match_dup 1))
    (set (cc0)
         (compare (match_dup 0) (match_dup 2)))]
   "operands[2] = gen_rtx (REG, HImode, SOFT_TMP_REGNUM);")
 
+(define_split
+  [(set (cc0)
+	(compare (match_operand:HI 0 "hard_reg_operand" "")
+		 (match_operand:HI 1 "hard_reg_operand" "")))]
+  "0 && TARGET_M6812
+   && reload_completed && !(Z_REG_P (operands[0]) || Z_REG_P (operands[1]))"
+  [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 1))
+   (set (cc0)
+        (compare (match_dup 0) (mem:HI (post_inc:HI (reg:HI SP_REGNUM)))))]
+  "")
+
 (define_expand "cmphi"
   [(set (cc0)
 	(compare (match_operand:HI 0 "tst_operand" "")
@@ -325,7 +334,7 @@
   [(set (cc0)
 	(compare (match_operand:HI 0 "tst_operand" 
 				"d,?xy,xyd,?xy,d,m,!u,dxy,dxy")
-		 (match_operand:HI 1 "cmp_operand"
+		 (match_operand:HI 1 "general_operand"
 				"i,i,!u,m,m,dxy,dxy,?*d*A,!*w")))]
   "TARGET_M6812"
   "*
@@ -335,8 +344,10 @@
       cc_status.flags |= CC_REVERSED;
       return \"cp%1\\t%0\";
     }
+  else if (SP_REG_P (operands[1]))
+    return \"sts\\t2,-sp\n\\tcp%0\\t2,sp+\";
   else if (H_REG_P (operands[1]))
-    return \"#\";
+    return \"psh%1\n\\tcp%0\\t2,sp+\";
   else
     return \"cp%0\\t%1\";
 }")
@@ -344,9 +355,9 @@
 (define_insn "cmphi_1_hc11"
   [(set (cc0)
 	(compare (match_operand:HI 0 "tst_operand" 
-				"dx,y,xyd,?xy,d,m,!u,dxy,dxy")
+				"dx,y,xyd,?xy,d,m,m,dxy,dxy,?u*z,dxy,*z")
 		 (match_operand:HI 1 "cmp_operand"
-				"i,i,!u,m,m,dxy,dxy,?*d*A,!*w")))]
+				"i,i,!u,m,m,?xy,d,?*d*A,?u,dxy,!*w,i")))]
   "TARGET_M6811"
   "*
 {
@@ -361,21 +372,14 @@
     return \"cp%0\\t%1\";
 }")
 
-(define_insn "cmphi_z_used"
+(define_insn_and_split "cmphi_z_used"
   [(set (cc0)
 	(compare (match_operand:HI 0 "tst_operand" "dxy,m")
-		 (match_operand:HI 1 "cmp_operand" "m,dxy")))
+		 (match_operand:HI 1 "cmp_operand" "mi,dxy")))
    (use (match_operand:HI 2 "hard_reg_operand" "dxy,dxy"))
    (use (reg:HI SOFT_Z_REGNUM))]
   ""
-  "#")
-  
-(define_split /* "cmphi_z_used" */
-  [(set (cc0)
-	(compare (match_operand:HI 0 "tst_operand" "")
-		 (match_operand:HI 1 "cmp_operand" "")))
-   (use (match_operand:HI 2 "hard_reg_operand" ""))
-   (use (reg:HI SOFT_Z_REGNUM))]
+  "#"
   "z_replacement_completed == 2"
   [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 2))
    (set (match_dup 2) (match_dup 3))
@@ -452,21 +456,14 @@
    operands[3] = gen_rtx (REG, HImode, SOFT_TMP_REGNUM);
    operands[4] = gen_rtx (REG, QImode, SOFT_TMP_REGNUM);")
 
-(define_insn "bitcmpqi_z_used"
+(define_insn_and_split "bitcmpqi_z_used"
   [(set (cc0)
 	(and:QI (match_operand:QI 0 "tst_operand" "d,m")
 		(match_operand:QI 1 "cmp_operand" "m,d")))
    (use (match_operand:HI 2 "hard_reg_operand" "xy,xy"))
    (use (reg:HI SOFT_Z_REGNUM))]
   ""
-  "#")
-  
-(define_split /* "bitcmpqi_z_used" */
-  [(set (cc0)
-	(and:QI (match_operand:QI 0 "tst_operand" "")
-		(match_operand:QI 1 "cmp_operand" "")))
-   (use (match_operand:HI 2 "hard_reg_operand" ""))
-   (use (reg:HI SOFT_Z_REGNUM))]
+  "#"
   "z_replacement_completed == 2"
   [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 2))
    (set (match_dup 2) (match_dup 3))
@@ -542,21 +539,14 @@
    return \"cmpb\\t%b0\";
 }")
 
-(define_insn "cmpqi_z_used"
+(define_insn_and_split "cmpqi_z_used"
   [(set (cc0)
 	(compare (match_operand:QI 0 "tst_operand" "dxy,m")
 		 (match_operand:QI 1 "cmp_operand" "m,dxy")))
    (use (match_operand:HI 2 "hard_reg_operand" "dxy,dxy"))
    (use (reg:HI SOFT_Z_REGNUM))]
   ""
-  "#")
-  
-(define_split /* cmpqi_z_used */
-  [(set (cc0)
-	(compare (match_operand:QI 0 "tst_operand" "")
-		 (match_operand:QI 1 "cmp_operand" "")))
-   (use (match_operand:HI 2 "hard_reg_operand" ""))
-   (use (reg:HI SOFT_Z_REGNUM))]
+  "#"
   "z_replacement_completed == 2"
   [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 2))
    (set (match_dup 2) (match_dup 3))
@@ -573,41 +563,29 @@
 ;; (strict_low_part ...) information.  This is correct for our machine
 ;; description but not for GCC optimization passes.
 ;;
-(define_insn "movstrictsi"
+(define_insn_and_split "movstrictsi"
   [(set (strict_low_part (match_operand:SI 0 "non_push_operand" "+um,D,D"))
 	(match_operand:SI 1 "general_operand" "D,Dim,uD"))]
   ""
-  "#")
-
-(define_split
-  [(set (strict_low_part (match_operand:SI 0 "non_push_operand" ""))
-	(match_operand:SI 1 "general_operand" ""))]
+  "#"
   "z_replacement_completed == 2"
   [(set (match_dup 0) (match_dup 1))]
   "")
 
-(define_insn "movstricthi"
+(define_insn_and_split "movstricthi"
   [(set (strict_low_part (match_operand:HI 0 "non_push_operand" "+um,dA,dA"))
 	(match_operand:HI 1 "general_operand" "dA,dAim,u"))]
   ""
-  "#")
-
-(define_split
-  [(set (strict_low_part (match_operand:HI 0 "non_push_operand" ""))
-	(match_operand:HI 1 "general_operand" ""))]
+  "#"
   "z_replacement_completed == 2"
   [(set (match_dup 0) (match_dup 1))]
   "")
 
-(define_insn "movstrictqi"
+(define_insn_and_split "movstrictqi"
   [(set (strict_low_part (match_operand:QI 0 "non_push_operand" "+mu,!dA"))
 	(match_operand:QI 1 "general_operand" "d,imudA"))]
   ""
-  "#")
-
-(define_split
-  [(set (strict_low_part (match_operand:QI 0 "non_push_operand" ""))
-	(match_operand:QI 1 "general_operand" ""))]
+  "#"
   "z_replacement_completed == 2"
   [(set (match_dup 0) (match_dup 1))]
   "")
@@ -651,17 +629,26 @@
     }
 ")
 
-(define_insn "movdi_internal"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=ou,U,!u,U,m,m,!u")
+;; Separate push from normal moves to avoid reloading problems
+;; The 'clr' is not able to push on 68HC11 so we really need a scratch.
+;; We can also accept more scratch registers.
+(define_insn_and_split "*pushdi_internal"
+  [(set (match_operand:DI 0 "push_operand" "=<,<,<,<")
+	(match_operand:DI 1 "general_operand" "i,U,m,!u"))
+   (clobber (match_scratch:HI 2 "=&dA,&d,&d,&dA"))]
+  ""
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "m68hc11_split_move (operands[0], operands[1], operands[2]);
+   DONE;")
+
+(define_insn_and_split "movdi_internal"
+  [(set (match_operand:DI 0 "non_push_operand" "=m!u,U,!u,U,m,m,!u")
 	(match_operand:DI 1 "general_operand" "K,iU,iU,!u,mi,!u,!mu"))
    (clobber (match_scratch:HI 2 "=X,&d,&d,&d,&d,&d,&d"))]
   ""
-  "#")
-
-(define_split
-  [(set (match_operand:DI 0 "nonimmediate_operand" "")
-	(match_operand:DI 1 "general_operand" ""))
-   (clobber (match_scratch:HI 2 ""))]
+  "#"
   "reload_completed"
   [(const_int 0)]
   "m68hc11_split_move (operands[0], operands[1], operands[2]);
@@ -687,17 +674,24 @@
     }
 ")
 
-(define_insn "movdf_internal"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=ou,U,!u,U,m,m,!u")
+;; See pushdi_internal
+(define_insn_and_split "*pushdf_internal"
+  [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
+	(match_operand:DF 1 "general_operand" "i,U,m,!u"))
+   (clobber (match_scratch:HI 2 "=&dA,&d,&d,&dA"))]
+  ""
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "m68hc11_split_move (operands[0], operands[1], operands[2]);
+   DONE;")
+
+(define_insn_and_split "movdf_internal"
+  [(set (match_operand:DF 0 "non_push_operand" "=mu,U,!u,U,m,m,!u")
 	(match_operand:DF 1 "general_operand" "G,iU,iU,!u,mi,!u,!mu"))
    (clobber (match_scratch:HI 2 "=X,&d,&d,&d,&d,&d,&d"))]
   ""
-  "#")
-
-(define_split
-  [(set (match_operand:DF 0 "nonimmediate_operand" "")
-	(match_operand:DF 1 "general_operand" ""))
-   (clobber (match_scratch:HI 2 ""))]
+  "#"
   "reload_completed"
   [(const_int 0)]
   "m68hc11_split_move (operands[0], operands[1], operands[2]);
@@ -732,17 +726,23 @@
     }
 ")
 
-(define_insn "movsi_internal"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=ou,mu,?D,m,?D,?u,?u,!u,D")
-	(match_operand:SI 1 "general_operand"      "K,imu,im,?D,!u,?D,mi,!u,!D"))
-   (clobber (match_scratch:HI 2                    "=X,&d,X,X,X,X,&d,&d,X"))]
+(define_insn_and_split "*pushsi_internal"
+  [(set (match_operand:SI 0 "push_operand" "=<,<,<,<,<")
+	(match_operand:SI 1 "general_operand" "!D,i,U,m,!u"))
+   (clobber (match_scratch:HI 2 "=X,&dA,&d,&d,&dA"))]
   ""
-  "#")
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "m68hc11_split_move (operands[0], operands[1], operands[2]);
+   DONE;")
 
-(define_split
-  [(set (match_operand:SI 0 "nonimmediate_operand" "")
-	(match_operand:SI 1 "general_operand" ""))
-   (clobber (match_scratch:HI 2 ""))]
+(define_insn_and_split "movsi_internal"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=mu,mu,?D,m,?D,?u,?u,!u,D")
+	(match_operand:SI 1 "general_operand" "K,imu,im,?D,!u,?D,mi,!u,!D"))
+   (clobber (match_scratch:HI 2               "=X,&d,X,X,X,X,&d,&d,X"))]
+  ""
+  "#"
   "reload_completed"
   [(const_int 0)]
   "m68hc11_split_move (operands[0], operands[1], operands[2]);
@@ -768,17 +768,23 @@
     }
 ")
 
-(define_insn "movsf_internal"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=o!u,m,D,m,D,!u,!u,!u,D")
+(define_insn_and_split "*pushsf_internal"
+  [(set (match_operand:SF 0 "push_operand" "=<,<,<,<,<")
+	(match_operand:SF 1 "general_operand" "!D,i,U,m,!u"))
+   (clobber (match_scratch:HI 2 "=X,&dA,&d,&d,&dA"))]
+  ""
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "m68hc11_split_move (operands[0], operands[1], operands[2]);
+   DONE;")
+
+(define_insn_and_split "movsf_internal"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=m!u,m,D,m,D,!u,!u,!u,D")
 	(match_operand:SF 1 "general_operand" "G,im,im,D,!u,D,mi,!u,!D"))
    (clobber (match_scratch:HI 2 "=X,&d,X,X,X,X,&d,&d,X"))]
   ""
-  "#")
-
-(define_split
-  [(set (match_operand:SF 0 "nonimmediate_operand" "")
-	(match_operand:SF 1 "general_operand" ""))
-   (clobber (match_scratch:HI 2 ""))]
+  "#"
   "reload_completed"
   [(const_int 0)]
   "m68hc11_split_move (operands[0], operands[1], operands[2]);
@@ -849,6 +855,18 @@
           DONE;
         }
     }
+
+  /* The doloop optimization can emit a move with a constant > 32767.
+     This will fail later on because the move instruction is not recognized
+     eg: (set (reg:HI 53) (const_int 0x8000))
+     because for some reason gcc expects the constant to be sign extended
+     ie, it only recognize: (set (reg:HI 53) (const_int 0xffff8000))
+     Do the sign extension here.  */
+  if (GET_CODE (operands[1]) == CONST_INT
+      && INTVAL (operands[1]) > 0x7fffL && INTVAL (operands[1]) <= 0x0ffffL)
+    {
+      operands[1] = GEN_INT ((INTVAL (operands[1])) | (-1L << 16));
+    }
   if (TARGET_M6811 && (reload_in_progress | reload_completed) == 0)
     {
       if (GET_CODE (operands[0]) == MEM &&
@@ -878,18 +896,9 @@
     }
 }")
 
-(define_insn "movhi_const0"
-  [(set (match_operand:HI 0 "non_push_operand" "=d,A,um")
-	(const_int 0))]
-  ""
-  "@
-   clra\\n\\tclrb
-   ld%0\\t#0
-   clr\\t%b0\\n\\tclr\\t%h0")
-
 (define_insn "*movhi_68hc12"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=U,dAw,U,U,m,!u")
-	(match_operand:HI 1 "general_operand" "U,rim,dAwi,!u,dAw,riU"))]
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=U,dAw,dAw,m,U,U,m,!u")
+	(match_operand:HI 1 "general_operand" "U,dAwim,!u,K,dAwi,!u,dAw,riU"))]
   "TARGET_M6812"
   "*
 {
@@ -897,6 +906,15 @@
   return \"\";
 }")
 
+(define_insn "movhi_const0"
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,A,um")
+	(const_int 0))]
+  "TARGET_M6811"
+  "@
+   clra\\n\\tclrb
+   ld%0\\t#0
+   clr\\t%b0\\n\\tclr\\t%h0")
+
 (define_insn "*movhi_m68hc11"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=dAw,!u,m,m,dAw,!*u")
 	(match_operand:HI 1 "general_operand" "dAwim,dAw,dA,?Aw,!*u,dAw"))]
@@ -936,9 +954,9 @@
 (define_split
   [(set (match_operand:QI 0 "hard_addr_reg_operand" "")
         (match_operand:QI 1 "general_operand" ""))]
-  "z_replacement_completed == 2 && GET_MODE (operands[0]) == QImode
+  "z_replacement_completed == 2
    && !reg_mentioned_p (operands[0], operands[1])
-   && !D_REG_P (operands[1])"
+   && !(D_REG_P (operands[1]) || Q_REG_P (operands[1]))"
   [(parallel [(set (reg:HI D_REGNUM) (match_dup 2))
               (set (match_dup 2) (reg:HI D_REGNUM))])
    (set (reg:QI D_REGNUM) (match_dup 1))
@@ -952,9 +970,9 @@
 (define_split
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
         (match_operand:QI 1 "hard_addr_reg_operand" ""))]
-  "z_replacement_completed == 2 && GET_MODE (operands[1]) == QImode
+  "z_replacement_completed == 2
    && !reg_mentioned_p (operands[1], operands[0])
-   && !D_REG_P (operands[0])"
+   && !(D_REG_P (operands[0]) || Q_REG_P (operands[0]))"
   [(parallel [(set (reg:HI D_REGNUM) (match_dup 2))
               (set (match_dup 2) (reg:HI D_REGNUM))])
    (set (match_dup 0) (reg:QI D_REGNUM))
@@ -1664,8 +1682,8 @@
 ;;- Min and Max instructions (68HC12).
 ;;--------------------------------------------------------------------
 (define_insn "uminqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
-	(umin:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
+  [(set (match_operand:QI 0 "nonimmediate_noinc_operand" "=d,m")
+	(umin:QI (match_operand:QI 1 "nonimmediate_noinc_operand" "%0,0")
 		 (match_operand:QI 2 "general_operand" "m,d")))]
   "TARGET_M6812 && TARGET_MIN_MAX"
   "*
@@ -1686,8 +1704,8 @@
 }")
 
 (define_insn "umaxqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
-	(umax:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
+  [(set (match_operand:QI 0 "nonimmediate_noinc_operand" "=d,m")
+	(umax:QI (match_operand:QI 1 "nonimmediate_noinc_operand" "%0,0")
 		 (match_operand:QI 2 "general_operand" "m,d")))]
   "TARGET_M6812 && TARGET_MIN_MAX"
   "*
@@ -1708,8 +1726,8 @@
 }")
 
 (define_insn "uminhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
-	(umin:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
+  [(set (match_operand:HI 0 "nonimmediate_noinc_operand" "=d,m")
+	(umin:HI (match_operand:HI 1 "nonimmediate_noinc_operand" "%0,0")
 		 (match_operand:HI 2 "general_operand" "m,d")))]
   "TARGET_M6812 && TARGET_MIN_MAX"
   "*
@@ -1727,8 +1745,8 @@
 }")
 
 (define_insn "umaxhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
-	(umax:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
+  [(set (match_operand:HI 0 "nonimmediate_noinc_operand" "=d,m")
+	(umax:HI (match_operand:HI 1 "nonimmediate_noinc_operand" "%0,0")
 		 (match_operand:HI 2 "general_operand" "m,d")))]
   "TARGET_M6812 && TARGET_MIN_MAX"
   "*
@@ -2090,8 +2108,8 @@
 }")
 
 (define_insn "*addhi3_68hc12"
-  [(set (match_operand:HI 0 "register_operand" "=xyd,d,xy*z*w,xy*z*w,xy*z")
-        (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,xy*zw,0")
+  [(set (match_operand:HI 0 "register_operand" "=d*A,d,xy*A*w,xy*A*w,xy*A")
+        (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,xy*Aw,0")
                  (match_operand:HI 2 "general_operand" "i,m*A*wu,id,id,!mu*A")))]
   "TARGET_M6812"
   "*
@@ -2279,9 +2297,9 @@
 }")
 
 (define_insn "*addhi3"
-  [(set (match_operand:HI 0 "hard_reg_operand" "=A,dA,d,!A,d*A,!d*A")
-	(plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0,0,0")
-		 (match_operand:HI 2 "general_operand" "N,I,i,I,mi*A*d,!u*d*w")))]
+  [(set (match_operand:HI 0 "hard_reg_operand" "=A,dA,d,!A,d*A,d,!d*A")
+	(plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0,0,0,0")
+		 (match_operand:HI 2 "general_operand" "N,I,i,I,mi*A*d,*u,!u*d*w")))]
   "TARGET_M6811"
   "*
 {
@@ -2374,7 +2392,7 @@
   [(set (match_operand:HI 0 "hard_reg_operand" "=A,d")
 	(plus:HI (zero_extend:HI 
 		     (match_operand:QI 1 "nonimmediate_operand" "d,um*A"))
-		 (match_operand:HI 2 "hard_reg_operand" "0,0")))]
+		 (match_operand:HI 2 "general_operand" "0,0")))]
   ""
   "*
 {
@@ -2401,8 +2419,8 @@
   "")
 
 (define_insn "addqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=!d*rm,dq,!*A")
-        (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
+  [(set (match_operand:QI 0 "nonimmediate_noinc_operand" "=!d*rm,dq,!*A")
+        (plus:QI (match_operand:QI 1 "nonimmediate_noinc_operand" "%0,0,0")
                  (match_operand:QI 2 "general_operand" "N,ium*A*d,ium*A*d")))]
   ""
   "*
@@ -2707,9 +2725,9 @@
 
 
 (define_insn "*subhi3"
-  [(set (match_operand:HI 0 "register_operand" "=d,*A,d*A")
-	(minus:HI (match_operand:HI 1 "register_operand" "0,0,0")
-		  (match_operand:HI 2 "general_operand" "im*A*d,im*d*A,!u")))]
+  [(set (match_operand:HI 0 "register_operand" "=d,*A,d,*A")
+	(minus:HI (match_operand:HI 1 "general_operand" "0,0,0,0")
+		  (match_operand:HI 2 "general_operand" "im*A*d,im*d*A,u,!u")))]
   ""
   "*
 {
@@ -2723,7 +2741,7 @@
 
 (define_insn "*subhi3_zext"
   [(set (match_operand:HI 0 "hard_reg_operand" "=d,d")
-	(minus:HI (match_operand:HI 1 "hard_reg_operand" "0,0")
+	(minus:HI (match_operand:HI 1 "general_operand" "0,0")
            (zero_extend:HI (match_operand:QI 2 "general_operand" "mi*A,!u"))))]
   ""
   "*
@@ -2743,7 +2761,7 @@
 
 (define_insn "subqi3"
   [(set (match_operand:QI 0 "hard_reg_operand" "=dq,!*x*y")
-        (minus:QI (match_operand:QI 1 "hard_reg_operand" "0,0")
+        (minus:QI (match_operand:QI 1 "general_operand" "0,0")
                   (match_operand:QI 2 "general_operand" "uim*A*d,uim*A*d")))]
   ""
   "*
@@ -2837,6 +2855,32 @@
   return \"emul\\n\\texg\\tx,y\";
 }")
 
+(define_insn "umulhisi3_hc11"
+  [(set (match_operand:SI 0 "register_operand" "=D,D")
+        (mult:SI (zero_extend:SI
+		     (match_operand:HI 1 "register_operand" "%d,Amu"))
+		 (zero_extend:SI
+	             (match_operand:HI 2 "register_operand" "Amu,d"))))
+   (clobber (match_scratch:HI 3 "=y,y"))]
+  "TARGET_M6811"
+  "*
+{
+  CC_STATUS_INIT;
+  if (!H_REG_P (operands[1]))
+    output_asm_insn (\"ldx\\t%1\", operands);
+  if (!H_REG_P (operands[2]))
+    output_asm_insn (\"ldx\\t%2\", operands);
+
+  if (Y_REG_P (operands[1]) || Y_REG_P (operands[2]))
+    output_asm_insn (\"pshy\", operands);
+  else if (X_REG_P (operands[1]) || X_REG_P (operands[2])
+           || !H_REG_P (operands[1]) || !H_REG_P (operands[2]))
+    output_asm_insn (\"pshx\", operands);
+
+  output_asm_insn (\"bsr\\t__mulhi32\", operands);
+  return \"ins\\n\\tins\";
+}")
+
 (define_insn "mulhisi3"
   [(set (match_operand:SI 0 "register_operand" "=D,D")
         (mult:SI (sign_extend:SI
@@ -2896,8 +2940,8 @@
 
 (define_insn "mulqi3"
   [(set (match_operand:QI 0 "register_operand" "=d,*x,*y")
-        (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%dum,0,0")
-		 (match_operand:QI 2 "general_operand" "dium,*xium,*yium")))]
+        (mult:QI (match_operand:QI 1 "general_operand" "%di*um,0,0")
+		 (match_operand:QI 2 "general_operand" "di*um,*xium,*yium")))]
   ""
   "*
 {
@@ -2952,11 +2996,11 @@
   ")
 
 (define_insn "mulqihi3"
-  [(set (match_operand:HI 0 "register_operand" "=d,d")
+  [(set (match_operand:HI 0 "register_operand" "=d,d,d")
         (mult:HI (sign_extend:HI
-			(match_operand:QI 1 "register_operand" "%0,0"))
+			(match_operand:QI 1 "register_operand" "%0,0,0"))
 		 (sign_extend:HI
-                        (match_operand:QI 2 "nonimmediate_operand" "dm,*A"))))]
+                        (match_operand:QI 2 "general_operand" "mi*u,*A,0"))))]
   ""
   "*
 {
@@ -3054,21 +3098,29 @@
 ;;- and instructions.
 ;;--------------------------------------------------------------------
 
-(define_insn "anddi3"
+(define_insn_and_split "anddi3"
   [(set (match_operand:DI 0 "reg_or_some_mem_operand" "=m,u")
 	(and:DI (match_operand:DI 1 "reg_or_some_mem_operand" "%imu,imu")
 		(match_operand:DI 2 "general_operand" "imu,imu")))
    (clobber (match_scratch:HI 3 "=d,d"))]
   ""
-  "#")
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "m68hc11_split_logical (SImode, AND, operands);
+   DONE;")
 
-(define_insn "andsi3"
+(define_insn_and_split "andsi3"
   [(set (match_operand:SI 0 "register_operand" "=D,!u")
 	(and:SI (match_operand:SI 1 "register_operand" "%0,0")
 		(match_operand:SI 2 "general_operand" "Dimu,imu")))
    (clobber (match_scratch:HI 3 "=X,d"))]
   ""
-  "#")
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "m68hc11_split_logical (HImode, AND, operands);
+   DONE;")
 
 (define_expand "andhi3"
   [(set (match_operand:HI 0 "register_operand" "")
@@ -3078,10 +3130,10 @@
   "")
 
 (define_insn "*andhi3_mem"
-  [(set (match_operand:HI 0 "memory_operand" "=Q,R")
+  [(set (match_operand:HI 0 "memory_operand" "=R,Q")
 	(and:HI (match_dup 0)
 	        (match_operand:HI 1 "immediate_operand" "i,i")))
-   (clobber (match_scratch:HI 2 "=xy,X"))]
+   (clobber (match_scratch:HI 2 "=X,xy"))]
   "TARGET_RELAX && !TARGET_M6812"
   "*
 {
@@ -3101,7 +3153,7 @@
   /* When destination is a global variable, generate a .relax instruction
      and load the address in the clobber register.  That load can be
      eliminated by the linker if the address is in page0.  */
-  if (which_alternative == 0)
+  if (which_alternative == 1)
     {
       rtx ops[3];
 
@@ -3216,8 +3268,8 @@
 
 (define_insn "*andhi3_gen"
   [(set (match_operand:HI 0 "register_operand" "=d,d,!*A")
-	(and:HI (match_operand:HI 1 "register_operand" "%0,0,0")
-		(match_operand:HI 2 "general_operand" "mi,!u*A,!um*A")))]
+	(and:HI (match_operand:HI 1 "splitable_operand" "%0,0,0")
+		(match_operand:HI 2 "splitable_operand" "mi,!u*A,!um*Ai")))]
   ""
   "*
 {
@@ -3236,10 +3288,10 @@
   "")
 
 (define_insn "*andqi3_mem"
-  [(set (match_operand:QI 0 "memory_operand" "=Q,R")
+  [(set (match_operand:QI 0 "memory_operand" "=R,Q")
 	(and:QI (match_dup 0)
 	        (match_operand:QI 1 "const_int_operand" "i,i")))
-   (clobber (match_scratch:HI 2 "=xy,X"))]
+   (clobber (match_scratch:HI 2 "=X,xy"))]
   "TARGET_RELAX && !TARGET_M6812"
   "*
 {
@@ -3257,7 +3309,7 @@
   /* When destination is a global variable, generate a .relax instruction
      and load the address in the clobber register.  That load can be
      eliminated by the linker if the address is in page0.  */
-  if (which_alternative == 0)
+  if (which_alternative == 1)
     {
       rtx ops[3];
 
@@ -3310,8 +3362,8 @@
 
 (define_insn "*andqi3_gen"
   [(set (match_operand:QI 0 "register_operand" "=d,d,d,?*A,?*A,!*q")
-        (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0")
-             (match_operand:QI 2 "general_operand" "mi,!u,?*A,!um,?*A*d,!um*A")))]
+        (and:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0")
+             (match_operand:QI 2 "general_operand" "mi,!*u,?*A,!*um,?*A*d,!*um*A")))]
   ""
   "*
 {
@@ -3330,34 +3382,42 @@
 ;;- Bit set or instructions.
 ;;--------------------------------------------------------------------
 
-(define_insn "iordi3"
+(define_insn_and_split "iordi3"
   [(set (match_operand:DI 0 "reg_or_some_mem_operand" "=m,u")
 	(ior:DI (match_operand:DI 1 "reg_or_some_mem_operand" "%imu,imu")
 		(match_operand:DI 2 "general_operand" "imu,imu")))
    (clobber (match_scratch:HI 3 "=d,d"))]
   ""
-  "#")
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "m68hc11_split_logical (SImode, IOR, operands);
+   DONE;")
 
-(define_insn "iorsi3"
+(define_insn_and_split "iorsi3"
   [(set (match_operand:SI 0 "register_operand" "=D,!u")
 	(ior:SI (match_operand:SI 1 "register_operand" "%0,0")
 		(match_operand:SI 2 "general_operand" "Dimu,imu")))
    (clobber (match_scratch:HI 3 "=X,d"))]
   ""
-  "#")
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "m68hc11_split_logical (HImode, IOR, operands);
+   DONE;")
 
 (define_expand "iorhi3"
   [(set (match_operand:HI 0 "register_operand" "")
 	(ior:HI (match_operand:HI 1 "register_operand" "")
-		(match_operand:HI 2 "general_operand" "")))]
+		(match_operand:HI 2 "splitable_operand" "")))]
   ""
   "")
 
 (define_insn "*iorhi3_mem"
-  [(set (match_operand:HI 0 "memory_operand" "=Q,R")
+  [(set (match_operand:HI 0 "memory_operand" "=R,Q")
 	(ior:HI (match_dup 0)
 	        (match_operand:HI 1 "const_int_operand" "")))
-   (clobber (match_scratch:HI 2 "=xy,X"))]
+   (clobber (match_scratch:HI 2 "=X,xy"))]
   "TARGET_RELAX && !TARGET_M6812"
   "*
 {
@@ -3369,7 +3429,7 @@
       return \"\";
     }
   CC_STATUS_INIT;
-  if (which_alternative == 0)
+  if (which_alternative == 1)
     {
       rtx ops[3];
 
@@ -3437,8 +3497,8 @@
 
 (define_insn "*iorhi3_gen"
   [(set (match_operand:HI 0 "register_operand" "=d,d,!*A")
-	(ior:HI (match_operand:HI 1 "register_operand" "%0,0,0")
-		(match_operand:HI 2 "general_operand" "mi,!u*A,!um*A")))]
+	(ior:HI (match_operand:HI 1 "splitable_operand" "%0,0,0")
+		(match_operand:HI 2 "splitable_operand" "mi,!u*A,!um*Ai")))]
   ""
   "*
 {
@@ -3457,10 +3517,10 @@
   "")
 
 (define_insn "*iorqi3_mem"
-  [(set (match_operand:QI 0 "memory_operand" "=Q,R")
+  [(set (match_operand:QI 0 "memory_operand" "=R,Q")
 	(ior:QI (match_dup 0)
 	        (match_operand:QI 1 "const_int_operand" "")))
-   (clobber (match_scratch:HI 2 "=xy,X"))]
+   (clobber (match_scratch:HI 2 "=X,xy"))]
   "TARGET_RELAX && !TARGET_M6812"
   "*
 {
@@ -3471,7 +3531,7 @@
       cc_status = cc_prev_status;
       return \"\";
     }
-  if (which_alternative == 0)
+  if (which_alternative == 1)
     {
       rtx ops[3];
 
@@ -3520,8 +3580,8 @@
 
 (define_insn "*iorqi3_gen"
   [(set (match_operand:QI 0 "register_operand" "=d,d,d,?*A,?*A,!*q")
-	(ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0")
-	     (match_operand:QI 2 "general_operand" "mi,!u,!*A,!um,?*A*d,!um*A")))]
+	(ior:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0")
+	     (match_operand:QI 2 "general_operand" "mi,!*u,!*A,!*um,?*A*d,!*um*A")))]
   ""
   "*
 {
@@ -3541,26 +3601,34 @@
 ;;- xor instructions.
 ;;--------------------------------------------------------------------
 
-(define_insn "xordi3"
+(define_insn_and_split "xordi3"
   [(set (match_operand:DI 0 "reg_or_some_mem_operand" "=m,u")
 	(xor:DI (match_operand:DI 1 "reg_or_some_mem_operand" "%imu,imu")
 		(match_operand:DI 2 "general_operand" "imu,imu")))
    (clobber (match_scratch:HI 3 "=d,d"))]
   ""
-  "#")
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "m68hc11_split_logical (SImode, XOR, operands);
+   DONE;")
 
-(define_insn "xorsi3"
+(define_insn_and_split "xorsi3"
   [(set (match_operand:SI 0 "register_operand" "=D,!u")
 	(xor:SI (match_operand:SI 1 "register_operand" "%0,0")
 		(match_operand:SI 2 "general_operand" "Dimu,imu")))
    (clobber (match_scratch:HI 3 "=X,d"))]
   ""
-  "#")
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "m68hc11_split_logical (HImode, XOR, operands);
+   DONE;")
 
 (define_insn "xorhi3"
   [(set (match_operand:HI 0 "register_operand" "=d,d,!*A")
-	(xor:HI (match_operand:HI 1 "register_operand" "%0,0,0")
-		(match_operand:HI 2 "general_operand" "im,!u*A,!ium*A")))]
+	(xor:HI (match_operand:HI 1 "splitable_operand" "%0,0,0")
+		(match_operand:HI 2 "splitable_operand" "im,!u*A,!ium*A")))]
   ""
   "*
 {
@@ -3604,8 +3672,8 @@
 
 (define_insn "xorqi3"
   [(set (match_operand:QI 0 "register_operand" "=d,d,d,?*A,?*A,!*q")
-        (xor:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0")
-             (match_operand:QI 2 "general_operand" "im,!u,!*A,!ium,?*A*d,!ium*A")))]
+        (xor:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0")
+             (match_operand:QI 2 "general_operand" "im,!*u,!*A,!i*um,?*A*d,!i*um*A")))]
   ""
   "*
 {
@@ -3641,30 +3709,47 @@
 ;;- Bit set or instructions.
 ;;--------------------------------------------------------------------
 
-(define_insn "*logicalsi3_zexthi"
+(define_insn_and_split "*logicalsi3_zexthi"
   [(set (match_operand:SI 0 "register_operand" "=D")
 	(match_operator:SI 3 "m68hc11_logical_operator"
 		[(zero_extend:SI
 		     (match_operand:HI 1 "general_operand" "imudA"))
 		 (match_operand:SI 2 "general_operand" "Dimu")]))]
   ""
-  "#")
+  "#"
+  "reload_completed"
+  [(set (reg:HI D_REGNUM) (match_dup 4))
+   (set (reg:HI D_REGNUM) (match_op_dup 3 [(reg:HI D_REGNUM) (match_dup 5)]))
+   (set (reg:HI X_REGNUM) (match_dup 6))]
+  "PUT_MODE (operands[3], HImode);
+   if (X_REG_P (operands[2]))
+     {
+       operands[5] = operands[1];
+       /* Make all the (set (REG:x) (REG:y)) a nop set.  */
+       operands[4] = gen_rtx (REG, HImode, HARD_D_REGNUM);
+       operands[6] = gen_rtx (REG, HImode, HARD_X_REGNUM);
+     }
+   else
+     {
+       operands[4] = operands[1];
+       operands[5] = m68hc11_gen_lowpart (HImode, operands[2]);
+       operands[6] = m68hc11_gen_highpart (HImode, operands[2]);
+     }
+   /* For an AND, make sure the high 16-bit part is cleared.  */
+   if (GET_CODE (operands[3]) == AND)
+     {
+       operands[6] = const0_rtx;
+     }
+   ")
 
-(define_insn "*logicalsi3_zextqi"
+(define_insn_and_split "*logicalsi3_zextqi"
   [(set (match_operand:SI 0 "register_operand" "=D,D,D")
 	(match_operator:SI 3 "m68hc11_logical_operator"
 		[(zero_extend:SI
 		     (match_operand:QI 1 "general_operand" "d,*A,imu"))
 		 (match_operand:SI 2 "general_operand" "imu,imu,0")]))]
   ""
-  "#")
-
-(define_split /* logicalsi3_zextqi */
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_operator:SI 3 "m68hc11_logical_operator"
-	         [(zero_extend:SI
-		     (match_operand:QI 1 "general_operand" ""))
-		  (match_operand:SI 2 "general_operand" "")]))]
+  "#"
   "z_replacement_completed == 2"
   [(set (reg:QI A_REGNUM) (match_dup 4))
    (set (reg:QI D_REGNUM) (match_dup 7))
@@ -3695,63 +3780,47 @@
      }
    ")
 
-(define_split /* logicalsi3_zexthi */
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_operator:SI 3 "m68hc11_logical_operator"
-	         [(zero_extend:SI
-		     (match_operand:HI 1 "general_operand" ""))
-		  (match_operand:SI 2 "general_operand" "")]))]
-  "reload_completed"
-  [(set (reg:HI D_REGNUM) (match_dup 4))
-   (set (reg:HI D_REGNUM) (match_op_dup 3 [(reg:HI D_REGNUM) (match_dup 5)]))
-   (set (reg:HI X_REGNUM) (match_dup 6))]
-  "PUT_MODE (operands[3], HImode);
-   if (X_REG_P (operands[2]))
-     {
-       operands[5] = operands[1];
-       /* Make all the (set (REG:x) (REG:y)) a nop set.  */
-       operands[4] = gen_rtx (REG, HImode, HARD_D_REGNUM);
-       operands[6] = gen_rtx (REG, HImode, HARD_X_REGNUM);
-     }
-   else
-     {
-       operands[4] = operands[1];
-       operands[5] = m68hc11_gen_lowpart (HImode, operands[2]);
-       operands[6] = m68hc11_gen_highpart (HImode, operands[2]);
-     }
-   /* For an AND, make sure the high 16-bit part is cleared.  */
-   if (GET_CODE (operands[3]) == AND)
-     {
-       operands[6] = const0_rtx;
-     }
-   ")
-
-(define_insn "*logicalhi3_zexthi_ashift8"
+(define_insn_and_split "*logicalhi3_zexthi_ashift8"
   [(set (match_operand:HI 0 "register_operand" "=d")
 	(match_operator:HI 3 "m68hc11_logical_operator"
 		[(zero_extend:HI
-		     (match_operand:QI 1 "general_operand" "imud"))
+		     (match_operand:QI 1 "general_operand" "imud*A"))
 		 (ashift:HI
-		     (match_operand:HI 2 "general_operand" "dimu")
+		     (match_operand:HI 2 "general_operand" "imud*A")
 		     (const_int 8))]))]
   ""
-  "#")
+  "#"
+  "z_replacement_completed == 2"
+  [(set (reg:QI A_REGNUM) (match_dup 4))
+   (set (reg:QI B_REGNUM) (match_dup 5))]
+  "
+   if (GET_CODE (operands[3]) == AND)
+     {
+       emit_insn (gen_movhi (operands[0], const0_rtx));
+       DONE;
+     }
+   else
+     {
+       operands[5] = operands[1];
+       if (D_REG_P (operands[2]))
+         {
+           operands[4] = gen_rtx (REG, QImode, HARD_B_REGNUM);
+         }
+       else
+         {
+           operands[4] = m68hc11_gen_lowpart (QImode, operands[2]);
+         }
+     }
+  ")
 
-(define_insn "*logicalhi3_zexthi"
+(define_insn_and_split "*logicalhi3_zexthi"
   [(set (match_operand:HI 0 "register_operand" "=d,d")
 	(match_operator:HI 3 "m68hc11_logical_operator"
 		[(zero_extend:HI
 		     (match_operand:QI 1 "general_operand" "imd*A,?u"))
 		 (match_operand:HI 2 "general_operand" "dim,?dimu")]))]
   ""
-  "#")
-
-(define_split /* logicalhi3_zexthi */
-  [(set (match_operand:HI 0 "register_operand" "")
-	(match_operator:HI 3 "m68hc11_logical_operator"
-		[(zero_extend:HI
-		     (match_operand:QI 1 "general_operand" ""))
-		 (match_operand:HI 2 "general_operand" "")]))]
+  "#"
   "z_replacement_completed == 2"
   [(set (reg:QI B_REGNUM) (match_dup 6))
    (set (reg:QI A_REGNUM) (match_dup 4))
@@ -3780,63 +3849,25 @@
      }
   ")
 
-(define_split /* logicalhi3_zexthi_ashift8 */
-  [(set (match_operand:HI 0 "register_operand" "")
-	(match_operator:HI 3 "m68hc11_logical_operator"
-		[(zero_extend:HI
-		     (match_operand:QI 1 "general_operand" ""))
-		 (ashift:HI
-		     (match_operand:HI 2 "general_operand" "")
-		     (const_int 8))]))]
-  "z_replacement_completed == 2"
-  [(set (reg:QI A_REGNUM) (match_dup 4))
-   (set (reg:QI B_REGNUM) (match_dup 5))]
-  "
-   if (GET_CODE (operands[3]) == AND)
+
+(define_insn_and_split "*logicalsi3_silshr16"
+  [(set (match_operand:SI 0 "register_operand" "=D,D,D,?D")
+          (match_operator:SI 3 "m68hc11_logical_operator"
+	      [(lshiftrt:SI 
+		   (match_operand:SI 1 "general_operand" "uim,uim,0,0")
+		   (const_int 16))
+		(match_operand:SI 2 "general_operand" "uim,0,uim,0")]))]
+  ""
+  "#"
+  "reload_completed"
+  [(set (reg:HI D_REGNUM) (match_dup 4))
+   (set (reg:HI D_REGNUM) (match_op_dup 3 [(reg:HI D_REGNUM) (match_dup 5)]))
+   (set (reg:HI X_REGNUM) (match_dup 6))]
+  "operands[5] = m68hc11_gen_highpart (HImode, operands[1]);
+   if (X_REG_P (operands[2]))
      {
-       emit_insn (gen_movhi (operands[0], const0_rtx));
-       DONE;
-     }
-   else
-     {
-       operands[5] = operands[1];
-       if (D_REG_P (operands[2]))
-         {
-           operands[4] = gen_rtx (REG, QImode, HARD_B_REGNUM);
-         }
-       else
-         {
-           operands[4] = m68hc11_gen_lowpart (QImode, operands[2]);
-         }
-     }
-  ")
-
-(define_insn "*logicalsi3_silshr16"
-  [(set (match_operand:SI 0 "register_operand" "=D,D,D")
-          (match_operator:SI 3 "m68hc11_logical_operator"
-	      [(lshiftrt:SI 
-		   (match_operand:SI 1 "general_operand" "uim,uim,?D")
-		   (const_int 16))
-		(match_operand:SI 2 "general_operand" "uim,0,0")]))]
-  ""
-  "#")
-
-(define_split /* logicalsi3_silshr16 */
-  [(set (match_operand:SI 0 "register_operand" "")
-          (match_operator:SI 3 "m68hc11_logical_operator"
-		[(lshiftrt:SI 
-			(match_operand:SI 1 "general_operand" "")
-			(const_int 16))
-		 (match_operand:SI 2 "general_operand" "")]))]
-  "reload_completed"
-  [(set (reg:HI D_REGNUM) (match_dup 4))
-   (set (reg:HI D_REGNUM) (match_op_dup 3 [(reg:HI D_REGNUM) (match_dup 5)]))
-   (set (reg:HI X_REGNUM) (match_dup 6))]
-  "operands[5] = m68hc11_gen_highpart (HImode, operands[1]);
-   if (X_REG_P (operands[2]))
-     {
-       operands[4] = gen_rtx (REG, HImode, HARD_D_REGNUM);
-       operands[6] = gen_rtx (REG, HImode, HARD_X_REGNUM);
+       operands[4] = gen_rtx (REG, HImode, HARD_D_REGNUM);
+       operands[6] = gen_rtx (REG, HImode, HARD_X_REGNUM);
      }
    else
      {
@@ -3852,7 +3883,7 @@
      }
 ")
 
-(define_insn "*logicalsi3_silshl16"
+(define_insn_and_split "*logicalsi3_silshl16"
   [(set (match_operand:SI 0 "register_operand" "=D,D")
           (match_operator:SI 3 "m68hc11_logical_operator"
 	      [(ashift:SI 
@@ -3860,15 +3891,7 @@
 		   (const_int 16))
 		(match_operand:SI 2 "general_operand" "0,0")]))]
   ""
-  "#")
-
-(define_split /* logicalsi3_silshl16 */
-  [(set (match_operand:SI 0 "register_operand" "")
-          (match_operator:SI 3 "m68hc11_logical_operator"
-		[(ashift:SI 
-			(match_operand:SI 1 "general_operand" "")
-			(const_int 16))
-		 (match_operand:SI 2 "general_operand" "")]))]
+  "#"
   "z_replacement_completed == 2"
   [(set (reg:HI X_REGNUM) (match_op_dup 3 [(reg:HI X_REGNUM) (match_dup 4)]))
    (set (reg:HI D_REGNUM) (match_dup 5))]
@@ -3881,48 +3904,45 @@
      operands[5] = gen_rtx (REG, HImode, HARD_D_REGNUM);
    ")
 
-
-;;--------------------------------------------------------------------
-;;- 64/32-bit Logical Operations.  Patterns are defined so that GCC
-;; can optimize correctly.  These insns are split by the `final'
-;; pass (# pattern).  They are split to fall in the corresponding
-;; 16-bit logical patterns.
-;;--------------------------------------------------------------------
-
-;; Split 64-bit logical operations: anddi3, iordi3, xordi3
-(define_split
-  [(set (match_operand:DI 0 "reg_or_some_mem_operand" "")
-	(match_operator:DI 4 "m68hc11_logical_operator"
-	     [(match_operand:DI 1 "reg_or_some_mem_operand" "")
-	      (match_operand:DI 2 "general_operand" "")]))
-   (clobber (match_scratch:HI 3 ""))]
+(define_insn_and_split "*logicalsi3_silshl16_zext"
+  [(set (match_operand:SI 0 "register_operand" "=D,D,D")
+          (match_operator:SI 3 "m68hc11_logical_operator"
+	      [(ashift:SI
+	          (zero_extend:SI
+		     (match_operand:HI 1 "general_operand" "uim,udA,!dA"))
+		  (const_int 16))
+	    (zero_extend:SI (match_operand:HI 2 "general_operand" "uidA,um,!dA"))]))]
+  ""
+  "#"
+  ;; Must split before z register replacement
   "reload_completed"
-  [(const_int 0)]
-  "m68hc11_split_logical (SImode, GET_CODE (operands[4]), operands);
-   DONE;")
-
-;; Split 32-bit logical operations: andsi3, iorsi3, xorsi3
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_operator:SI 3 "m68hc11_logical_operator"
-	     [(match_operand:SI 1 "register_operand" "")
-	      (match_operand:SI 2 "general_operand" "")]))]
-  "0 && reload_completed"
-  [(const_int 0)]
-  "m68hc11_split_logical (HImode, GET_CODE (operands[3]), operands);
-   DONE;")
+  [(set (match_dup 4) (match_dup 5))
+   (set (match_dup 6) (match_dup 7))]
+  "
+    /* set (X_REGNUM) (d), set (D_REGNUM) (1) */
+   if (GET_CODE (operands[1]) == HARD_D_REGNUM
+       && GET_CODE (operands[3]) != AND)
+     {
+       /* This particular case is too early to be split before
+          Z register replacement because the cse-reg pass we do
+	  does not recognize the 'swap_areg'.  It is ok to handle
+	  this case after.  */
+       if (z_replacement_completed != 2)
+         {
+	   FAIL;
+	 }
+       emit_move_insn (gen_rtx (REG, HImode, HARD_X_REGNUM), operands[2]);
+       emit_insn (gen_swap_areg (gen_rtx (REG, HImode, HARD_D_REGNUM),
+			         gen_rtx (REG, HImode, HARD_X_REGNUM)));
+     }
+   operands[4] = gen_rtx (REG, HImode, HARD_D_REGNUM);
+   operands[6] = gen_rtx (REG, HImode, HARD_X_REGNUM);
+   operands[5] = operands[2];
+   operands[7] = operands[1];
 
-;; Split 32-bit logical operations: andsi3, iorsi3, xorsi3
-(define_split
-  [(set (match_operand:SI 0 "reg_or_some_mem_operand" "")
-	(match_operator:SI 4 "m68hc11_logical_operator"
-	     [(match_operand:SI 1 "reg_or_some_mem_operand" "")
-	      (match_operand:SI 2 "general_operand" "")]))
-   (clobber (match_scratch:HI 3 ""))]
-  "reload_completed"
-  [(const_int 0)]
-  "m68hc11_split_logical (HImode, GET_CODE (operands[4]), operands);
-   DONE;")
+   if (GET_CODE (operands[3]) == AND)
+     operands[5] = operands[7] = const0_rtx;
+   ")
 
 ;;--------------------------------------------------------------------
 ;; 16-bit Arithmetic and logical operations on X and Y:
@@ -4323,8 +4343,8 @@
    xgd%0\\n\\tcoma\\n\\tcomb\\n\\txgd%0\\n\\tin%0")
 
 (define_insn "negqi2"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m,!u,!*A")
-	(neg:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,0,0")))]
+  [(set (match_operand:QI 0 "nonimmediate_noinc_operand" "=d,m,!u,!*A")
+	(neg:QI (match_operand:QI 1 "nonimmediate_noinc_operand" "0,0,0,0")))]
   ""
   "@
    negb
@@ -4421,19 +4441,13 @@
     }
 }")
 
-(define_insn "*ashldi3_const32"
+(define_insn_and_split "*ashldi3_const32"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=<,m,u")
 	(ashift:DI (match_operand:DI 1 "general_operand" "umi,umi,umi")
 		   (const_int 32)))
    (clobber (match_scratch:HI 2 "=&A,d,d"))]
    ""
-   "#")
-
-(define_split
-  [(set (match_operand:DI 0 "nonimmediate_operand" "")
-	(ashift:DI (match_operand:DI 1 "general_operand" "")
-		   (const_int 32)))
-   (clobber (match_scratch:HI 2 ""))]
+   "#"
    "reload_completed"
    [(const_int 0)]
    "/* Move the lowpart in the highpart first in case the shift
@@ -4442,6 +4456,13 @@
       {
          m68hc11_split_move (m68hc11_gen_lowpart (SImode, operands[0]),
 			     const0_rtx, operands[2]);
+
+         /* Adjust first operand if it uses SP so that we take into
+            account the above push.  Can occur only for 68HC12.  */
+         if (reg_mentioned_p (gen_rtx (REG, HImode, HARD_SP_REGNUM),
+	                      operands[1]))
+           operands[1] = adjust_address (operands[1],
+	                                 GET_MODE (operands[0]), 4);
       }
     m68hc11_split_move (m68hc11_gen_highpart (SImode, operands[0]),
 		        m68hc11_gen_lowpart (SImode, operands[1]),
@@ -4453,19 +4474,13 @@
       }
     DONE;")
 
-(define_insn "*ashldi3_const1"
+(define_insn_and_split "*ashldi3_const1"
   [(set (match_operand:DI 0 "non_push_operand" "=m,m,u")
 	(ashift:DI (match_operand:DI 1 "general_operand" "mi,u,umi")
 		   (const_int 1)))
    (clobber (match_scratch:HI 2 "=d,d,d"))]
    ""
-   "#")
-
-(define_split
-  [(set (match_operand:DI 0 "non_push_operand" "")
-	(ashift:DI (match_operand:DI 1 "general_operand" "")
-		   (const_int 1)))
-   (clobber (match_scratch:HI 2 ""))]
+   "#"
    "z_replacement_completed == 2"
    [(set (match_dup 2) (match_dup 3))
     (set (match_dup 2) (ashift:HI (match_dup 2) (const_int 1)))
@@ -4505,10 +4520,10 @@
     operands[8] = m68hc11_gen_lowpart (HImode, operands[8]);")
 
 (define_insn "addsi_silshr16"
-  [(set (match_operand:SI 0 "register_operand" "=D,D")
-          (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "!*uim,0")
+  [(set (match_operand:SI 0 "register_operand" "=D,D,!D")
+          (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "!*uim,0,0")
 				(const_int 16))
-		   (match_operand:SI 2 "general_operand" "0,m!*u")))]
+		   (match_operand:SI 2 "general_operand" "0,m!*u,0")))]
   ""
   "#")
 
@@ -4530,14 +4545,24 @@
 				(const_int 16))
 		   (match_operand:SI 2 "general_operand" "")))]
   "z_replacement_completed == 2 && X_REG_P (operands[1])"
-  [(set (reg:HI D_REGNUM) (reg:HI X_REGNUM))
+  [(set (reg:HI D_REGNUM) (match_dup 5))
    (set (reg:HI X_REGNUM) (match_dup 3))
    (set (reg:HI D_REGNUM) (plus:HI (reg:HI D_REGNUM) (match_dup 4)))
    (set (reg:HI X_REGNUM) (plus:HI (plus:HI (reg:HI X_REGNUM)
 					    (const_int 0))
 				   (reg:HI CC_REGNUM)))]
   "operands[3] = m68hc11_gen_highpart (HImode, operands[2]);
-   operands[4] = m68hc11_gen_lowpart (HImode, operands[2]);")
+   if (X_REG_P (operands[2]))
+     {
+       operands[4] = gen_rtx (REG, HImode, HARD_X_REGNUM);
+       operands[5] = gen_rtx (REG, HImode, HARD_D_REGNUM);
+     }
+   else
+     {
+       operands[4] = m68hc11_gen_lowpart (HImode, operands[2]);
+       operands[5] = gen_rtx (REG, HImode, HARD_X_REGNUM);
+     }
+")
 
 (define_insn "addsi_ashift16"
   [(set (match_operand:SI 0 "register_operand" "=D")
@@ -4563,24 +4588,27 @@
   operands[4] = m68hc11_gen_lowpart (HImode, operands[2]);
 }")
 
-(define_insn "addsi_andshr16"
+(define_insn_and_split "addsi_andshr16"
   [(set (match_operand:SI 0 "register_operand" "=D")
           (plus:SI (and:SI (match_operand:SI 1 "general_operand" "%uim")
 			   (const_int 65535))
 		   (match_operand:SI 2 "general_operand" "0")))]
   ""
-  "#")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-          (plus:SI (and:SI (match_operand:SI 1 "general_operand" "")
-			   (const_int 65535))
-		   (match_operand:SI 2 "general_operand" "")))]
+  "#"
   "z_replacement_completed == 2"
   [(set (reg:HI D_REGNUM) (plus:HI (reg:HI D_REGNUM) (match_dup 3)))
    (set (reg:HI X_REGNUM) (plus:HI (plus:HI (reg:HI X_REGNUM) (const_int 0)) (reg:HI CC_REGNUM)))]
   "operands[3] = m68hc11_gen_lowpart (HImode, operands[1]);")
 
+(define_insn "subhi_ashlhi8"
+  [(set (match_operand:HI 0 "register_operand" "=d")
+          (minus:HI (match_operand:HI 1 "register_operand" "0")
+                    (mult:HI (match_operand:HI 2 "register_operand" "0")
+			     (const_int 256))))]
+  "0"
+  "@
+   sba")
+
 ;;
 ;; 32-bit shifts are made by a small library routine that uses
 ;; a specific passing convention for parameters (for efficiency reasons).
@@ -4622,31 +4650,24 @@
    ""
    "#")
 
-(define_insn "*ashlsi3_const16_zexthi"
+(define_insn_and_split "*ashlsi3_const16_zexthi"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=D")
 	(ashift:SI (zero_extend:HI 
 			(match_operand:HI 1 "general_operand" "duim*A"))
 	           (const_int 16)))
    (clobber (match_scratch:HI 2 "=X"))]
    ""
-   "#")
-
-(define_split /* "*ashlsi3_const16_zexthi"*/
-  [(set (match_operand:SI 0 "nonimmediate_operand" "")
-	(ashift:SI (zero_extend:HI 
-			(match_operand:HI 1 "general_operand" ""))
-	           (const_int 16)))
-   (clobber (match_scratch:HI 2 "=X"))]
+   "#"
    "reload_completed"
    [(set (reg:HI X_REGNUM) (match_dup 1))
     (set (reg:HI D_REGNUM) (const_int 0))]
    "")
 
 (define_insn "*ashlsi3_const1"
-  [(set (match_operand:SI 0 "non_push_operand" "=D,D,m,!*u,?*um")
-	(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,*um,0,0,*um")
+  [(set (match_operand:SI 0 "non_push_operand" "=D,D,D,m,*u,*u")
+	(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,m,*u,m,*u,m")
 	           (const_int 1)))
-   (clobber (match_scratch:HI 2 "=X,X,&d,&d,&d"))]
+   (clobber (match_scratch:HI 2 "=X,X,X,&d,&d,&d"))]
    ""
    "*
 {
@@ -4702,7 +4723,7 @@
 	(ashift:SI (match_dup 0)
 	           (match_operand:HI 1 "const_int_operand" "")))
    (clobber (match_scratch:HI 2 "=y"))]
-   ""
+   "TARGET_M6811 /* See *ashlsi3 note.  */"
    "*
 {
   CC_STATUS_INIT;
@@ -4712,7 +4733,7 @@
 (define_insn "*ashlsi3"
   [(set (match_operand:SI 0 "register_operand" "+D,D")
 	(ashift:SI (match_dup 0)
-	           (match_operand:HI 1 "general_operand" "y,m")))
+	           (match_operand:HI 1 "general_operand" "y,mi")))
    (clobber (match_scratch:HI 2 "=1,X"))]
    ""
    "*
@@ -4725,7 +4746,12 @@
      is not enough register in class A_REGS.
 
      Assuming that 'operands[1]' does not refer to the stack (which 
-     is true for 68hc11 only, we save temporary the value of Y.  */
+     is true for 68hc11 only, we save temporary the value of Y.
+
+     For 68HC12 we must also accept a constant because Z register is
+     disabled when compiling with -fomit-frame-pointer.  We can come up
+     with a reload problem and the *lshrsi3_const pattern was disabled
+     for that reason.  */
   if (!Y_REG_P (operands[2]))
     {
       rtx ops[1];
@@ -4861,8 +4887,8 @@
    "")
 
 (define_insn "*ashlqi3_const1"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m,!u,!*q,!*A")
-	(ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,0,0,0")
+  [(set (match_operand:QI 0 "nonimmediate_noinc_operand" "=d,m,!u,!*q,!*A")
+	(ashift:QI (match_operand:QI 1 "nonimmediate_noinc_operand" "0,0,0,0,0")
 	           (const_int 1)))]
   ""
   "@
@@ -5112,7 +5138,7 @@
 	(ashiftrt:SI (match_dup 0)
 	             (match_operand:HI 1 "const_int_operand" "")))
    (clobber (match_scratch:HI 2 "=y"))]
-   ""
+   "TARGET_M6811 /* See *ashrsi3 note.  */"
    "*
 {
   CC_STATUS_INIT;
@@ -5122,7 +5148,7 @@
 (define_insn "*ashrsi3"
   [(set (match_operand:SI 0 "register_operand" "+D,D")
 	(ashiftrt:SI (match_dup 0)
-	             (match_operand:HI 1 "general_operand" "y,m")))
+	             (match_operand:HI 1 "general_operand" "y,mi")))
    (clobber (match_scratch:HI 2 "=1,X"))]
    ""
    "*
@@ -5134,7 +5160,12 @@
      is not enough register in class A_REGS.
 
      Assuming that 'operands[1]' does not refer to the stack (which 
-     is true for 68hc11 only, we save temporary the value of Y.  */
+     is true for 68hc11 only, we save temporary the value of Y.
+
+     For 68HC12 we must also accept a constant because Z register is
+     disabled when compiling with -fomit-frame-pointer.  We can come up
+     with a reload problem and the *lshrsi3_const pattern was disabled
+     for that reason.  */
   if (!Y_REG_P (operands[2]))
     {
       rtx ops[1];
@@ -5162,8 +5193,8 @@
    "")
 
 (define_insn "*ashrqi3_const1"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m,!u,!*q,!*A")
-	(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,0,0,0")
+  [(set (match_operand:QI 0 "nonimmediate_noinc_operand" "=d,m,!u,!*q,!*A")
+	(ashiftrt:QI (match_operand:QI 1 "nonimmediate_noinc_operand" "0,0,0,0,0")
 		     (const_int 1)))]
   ""
   "@
@@ -5240,19 +5271,13 @@
     }
 }")
 
-(define_insn "*lshrdi3_const32"
+(define_insn_and_split "*lshrdi3_const32"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=<,m,u")
 	(lshiftrt:DI (match_operand:DI 1 "general_operand" "umi,umi,umi")
 		     (const_int 32)))
    (clobber (match_scratch:HI 2 "=&A,d,d"))]
    ""
-   "#")
-
-(define_split
-  [(set (match_operand:DI 0 "nonimmediate_operand" "")
-	(lshiftrt:DI (match_operand:DI 1 "general_operand" "")
-		     (const_int 32)))
-   (clobber (match_scratch:HI 2 "=&A,d"))]
+   "#"
    "reload_completed"
    [(const_int 0)]
    "m68hc11_split_move (m68hc11_gen_lowpart (SImode, operands[0]),
@@ -5322,19 +5347,13 @@
     operands[7] = m68hc11_gen_highpart (HImode, operands[6]);
     operands[6] = m68hc11_gen_lowpart (HImode, operands[6]);")
 
-(define_insn "*lshrdi_const1"
+(define_insn_and_split "*lshrdi_const1"
   [(set (match_operand:DI 0 "non_push_operand" "=m,u")
 	(lshiftrt:DI (match_operand:DI 1 "general_operand" "umi,umi")
 		     (const_int 1)))
    (clobber (match_scratch:HI 2 "=d,d"))]
    ""
-   "#")
-
-(define_split
-  [(set (match_operand:DI 0 "non_push_operand" "")
-	(lshiftrt:DI (match_operand:DI 1 "general_operand" "")
-		     (const_int 1)))
-   (clobber (match_scratch:HI 2 ""))]
+   "#"
    "z_replacement_completed == 2"
    [(set (match_dup 2) (match_dup 3))
     (set (match_dup 2) (lshiftrt:HI (match_dup 2) (const_int 1)))
@@ -5407,10 +5426,10 @@
     #")
 
 (define_insn "*lshrsi3_const1"
-  [(set (match_operand:SI 0 "non_push_operand" "=D,m,*u")
-	(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "D*um,*um,*um")
+  [(set (match_operand:SI 0 "non_push_operand" "=D,D,D,m,*u,*u")
+	(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,m,*u,m,*u,m")
 	             (const_int 1)))
-   (clobber (match_scratch:HI 2 "=X,&d,&d"))]
+   (clobber (match_scratch:HI 2 "=X,X,X,&d,&d,&d"))]
    ""
    "*
 {
@@ -5461,7 +5480,7 @@
 	(lshiftrt:SI (match_dup 0)
 	             (match_operand:HI 1 "const_int_operand" "")))
    (clobber (match_scratch:HI 2 "=y"))]
-   ""
+   "TARGET_M6811 /* See *lshrsi3 note.  */"
    "*
 {
   CC_STATUS_INIT;
@@ -5471,7 +5490,7 @@
 (define_insn "*lshrsi3"
   [(set (match_operand:SI 0 "register_operand" "+D,D")
 	(lshiftrt:SI (match_dup 0)
-	             (match_operand:HI 1 "general_operand" "y,m")))
+	             (match_operand:HI 1 "general_operand" "y,mi")))
    (clobber (match_scratch:HI 2 "=1,X"))]
    ""
    "*
@@ -5483,7 +5502,12 @@
      is not enough register in class A_REGS.
 
      Assuming that 'operands[1]' does not refer to the stack (which 
-     is true for 68hc11 only, we save temporary the value of Y.  */
+     is true for 68hc11 only, we save temporary the value of Y.
+
+     For 68HC12 we must also accept a constant because Z register is
+     disabled when compiling with -fomit-frame-pointer.  We can come up
+     with a reload problem and the *lshrsi3_const pattern was disabled
+     for that reason.  */
   if (!Y_REG_P (operands[2]))
     {
       rtx ops[1];
@@ -5544,8 +5568,8 @@
 }")
 
 (define_insn "lshrhi3_const"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,!*A,!*A")
-	(lshiftrt:HI (match_operand:HI 1 "general_operand" "dm*A,!u,dm,!u")
+  [(set (match_operand:HI 0 "nonimmediate_noinc_operand" "=d,d,!*A,!*A")
+	(lshiftrt:HI (match_operand:HI 1 "nonimmediate_noinc_operand" "dm*A,!u,dm,!u")
 		     (match_operand:HI 2 "const_int_operand" "i,i,i,i")))]
   ""
   "*
@@ -5649,8 +5673,8 @@
    "")
 
 (define_insn "*lshrqi3_const1"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d,!u,!*q,!*A")
-	(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,0,0,0")
+  [(set (match_operand:QI 0 "nonimmediate_noinc_operand" "=m,d,!u,!*q,!*A")
+	(lshiftrt:QI (match_operand:QI 1 "nonimmediate_noinc_operand" "0,0,0,0,0")
 		     (const_int 1)))]
   ""
   "@
@@ -5937,6 +5961,98 @@
   "")
 
 ;;--------------------------------------------------------------------
+;;-  Bit test and branch
+;;--------------------------------------------------------------------
+;; Logical and, test if zero and branch to use "brset/brclr" instruction
+;;
+(define_insn "brclr"
+  [(set (pc)
+	(if_then_else
+	  (eq (and:QI (match_operand:QI 0 "memory_operand" "R,Q")
+		      (match_operand:QI 1 "const_int_operand" ""))
+              (const_int 0))
+	 (label_ref (match_operand 2 "" ""))
+	 (pc)))
+   (clobber (match_scratch:HI 3 "=X,xy"))]
+  "0"
+  "*
+{
+  cc_status = cc_prev_status;
+  if (which_alternative == 0 || TARGET_M6812)
+    {
+      return \"brclr\\t%0,%1,%l2\";
+    }
+  else
+    {
+      rtx ops[3];
+
+      ops[0] = operands[3];
+      ops[1] = XEXP (operands[0], 0);
+      ops[2] = gen_label_rtx ();
+      output_asm_insn (\".relax\\t%l2\", ops);
+      m68hc11_gen_movhi (insn, ops);
+      output_asm_insn (\"brclr\\t0,%3,%1,%l2\", operands);
+      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
+				 CODE_LABEL_NUMBER (ops[2]));
+      return \"\";
+    }
+}")
+
+(define_insn "brset"
+  [(set (pc)
+	(if_then_else
+	  (eq (and:QI (not:QI (match_operand:QI 0 "memory_operand" "R,Q"))
+		      (match_operand:QI 1 "const_int_operand" ""))
+              (const_int 0))
+	 (label_ref (match_operand 2 "" ""))
+	 (pc)))
+   (clobber (match_scratch:HI 3 "=X,xy"))]
+  "0"
+  "*
+{
+  cc_status = cc_prev_status;
+  if (which_alternative == 0 || TARGET_M6812)
+    {
+      return \"brset\\t%0,%1,%l2\";
+    }
+  else
+    {
+      rtx ops[3];
+
+      ops[0] = operands[3];
+      ops[1] = XEXP (operands[0], 0);
+      ops[2] = gen_label_rtx ();
+      output_asm_insn (\".relax\\t%l2\", ops);
+      m68hc11_gen_movhi (insn, ops);
+      output_asm_insn (\"brset\\t0,%3,%1,%l2\", operands);
+      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
+				 CODE_LABEL_NUMBER (ops[2]));
+      return \"\";
+    }
+}")
+
+(define_peephole2
+  [(set (match_operand:QI 0 "hard_reg_operand" "")
+        (match_operand:QI 1 "memory_operand" "m"))
+   (set (cc0) (and:HI (match_operand:HI 2 "hard_reg_operand" "")
+	              (match_operand:HI 3 "const_int_operand" "")))
+   (set (pc)
+        (if_then_else (eq (cc0) (const_int 0))
+		      (label_ref (match_operand 4 "" ""))
+		      (pc)))]
+  "0 && REGNO (operands[0]) == REGNO (operands[2])
+   && peep2_reg_dead_p (2, operands[0])"
+  [(parallel [
+      (set (pc)
+        (if_then_else
+           (eq (and:QI (match_dup 1) (match_dup 3))
+               (const_int 0))
+	   (label_ref (match_dup 4))
+           (pc)))
+      (clobber (match_dup 5))])]
+  "operands[5] = gen_rtx_SCRATCH (HImode);")
+
+;;--------------------------------------------------------------------
 ;;-  68HC12 Decrement/Increment and branch
 ;;--------------------------------------------------------------------
 ;; These patterns are used by loop optimization as well as peephole2
@@ -5976,17 +6092,24 @@
     {
       FAIL;
     }
+
+  /* Note that for xxx_dbcc_dec_yy the gen_rtx_NE is only used to pass
+     the operator and its operands are not relevant.  */
   if (GET_MODE (operands[0]) == HImode)
     {
       emit_jump_insn (gen_m68hc12_dbcc_dec_hi (operands[0],
-					       gen_rtx (NE, HImode),
+					       gen_rtx (NE, HImode,
+						        operands[0],
+							operands[1]),
 					       operands[4]));
       DONE;
     }
   if (GET_MODE (operands[0]) == QImode)
     {
       emit_jump_insn (gen_m68hc12_dbcc_dec_qi (operands[0],
-					       gen_rtx (NE, QImode),
+					       gen_rtx (NE, QImode,
+						        operands[0],
+							operands[1]),
 					       operands[4]));
       DONE;
     }
@@ -6928,18 +7051,81 @@
 ;;
 ;; Replace "leas 2,sp" with a "pulx" or a "puly".
 ;; On 68HC12, this is one cycle slower but one byte smaller.
-;; pr target/6899: This peephole is not valid because a register CSE
-;; pass removes the pulx/puly.
+;; pr target/6899: This peephole was not valid because a register CSE
+;; pass removes the pulx/puly.  The 'use' clause ensure that the pulx is
+;; not removed.
 ;;
 (define_peephole2
   [(set (reg:HI SP_REGNUM) (plus:HI (reg:HI SP_REGNUM) (const_int 2)))
    (match_scratch:HI 0 "xy")]
-  "0 && TARGET_M6812 && optimize_size"
-  [(set (match_dup 0) (match_dup 1))]
+  "TARGET_M6812 && optimize_size"
+  [(set (match_dup 0) (match_dup 1))
+   (use (match_dup 0))]
   "operands[1] = gen_rtx (MEM, HImode,
 			  gen_rtx (POST_INC, HImode,
 				   gen_rtx_REG (HImode, HARD_SP_REGNUM)));")
 
+;; Replace: "pshx; tfr d,x; stx 0,sp" into "pshd; tfr d,x"
+;;
+;; PR 14542: emit a use to pretend we need the value of initial register.
+;; Otherwise verify_local_live_at_start will abort due to a live change
+;; of that register.
+;;
+(define_peephole2
+  [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM)))
+        (match_operand:HI 0 "hard_reg_operand" ""))
+   (set (match_dup 0)
+        (match_operand:HI 1 "hard_reg_operand" ""))
+   (set (mem:HI (reg:HI SP_REGNUM))
+        (match_dup 0))]
+  "TARGET_M6812"
+  [(use (match_dup 0))
+   (set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM)))
+        (match_dup 1))
+   (set (match_dup 0) (match_dup 1))]
+  "")
+
+;;
+;; Change: "ldd 0,sp; pulx" into  "puld"
+;; This sequence usually appears at end a functions.
+(define_peephole2
+  [(set (match_operand:HI 0 "hard_reg_operand" "")
+        (mem:HI (reg:HI SP_REGNUM)))
+   (use (match_dup 0))
+   (set (match_operand:HI 1 "hard_reg_operand" "")
+        (mem:HI (post_inc:HI (reg:HI SP_REGNUM))))]
+  "peep2_reg_dead_p (2, operands[1])"
+  [(set (match_dup 0) (mem:HI (post_inc:HI (reg:HI SP_REGNUM))))
+   (use (match_dup 0))]
+  "")
+
+;; Replace: "pshx; clr 0,sp; clr 1,sp" by "clr 1,-sp; clr 1,-sp"
+;; Appears to allocate local variables.
+(define_peephole2
+  [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM)))
+        (match_operand:HI 0 "hard_reg_operand" ""))
+   (set (mem:QI (plus:HI (reg:HI SP_REGNUM) (const_int 1)))
+        (const_int 0))
+   (set (mem:QI (reg:HI SP_REGNUM))
+        (const_int 0))]
+  "TARGET_M6812"
+  [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM)))
+        (const_int 0))]
+  "")
+
+;; Likewise for HI mode
+(define_peephole2
+  [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM)))
+        (match_operand:HI 0 "hard_reg_operand" ""))
+   (set (mem:HI (reg:HI SP_REGNUM))
+        (const_int 0))]
+  "TARGET_M6812"
+  [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM)))
+        (const_int 0))]
+  "")
+;;--------------------------------------------------------------------
+;;- 
+;;--------------------------------------------------------------------
 ;;
 ;; Optimize memory<->memory moves when the value is also loaded in
 ;; a register.
@@ -6989,6 +7175,32 @@
    (set (match_dup 0) (match_dup 2))]
   "")
 
+;;--------------------------------------------------------------------
+;;- 
+;;--------------------------------------------------------------------
+;; SCz 2005-05-08: this peephole2 is not finished.  I'm not sure it is
+;; valid in all cases.  Disabled but kept for documentation and futur fix.
+;; (optimize 8-bit move to/from the X or Y registers; the issue with
+;; the first (set) is that since operand 0 is either X or Y, we have to
+;; use the scratch _.tmp memory location; the peephole uses a stack location
+;; instead to save D and use D for the load)
+;;
+(define_peephole2
+  [(set (match_operand:QI 0 "hard_reg_operand" "")
+	(match_operand:QI 1 "memory_operand" ""))
+   (set (match_operand:QI 2 "memory_operand" "")
+        (match_dup 0))]
+  "0 && A_REG_P (operands[0]) && peep2_reg_dead_p (2, operands[0])
+   && !reg_mentioned_p (gen_rtx (REG, HImode, HARD_D_REGNUM), operands[1])
+   && !reg_mentioned_p (gen_rtx (REG, HImode, HARD_D_REGNUM), operands[1])
+   && !reg_mentioned_p (gen_rtx (REG, HImode, REGNO (operands[0])), operands[2])"
+  [(set (mem:QI (pre_dec:HI (reg:HI SP_REGNUM))) (reg:QI D_REGNUM))
+   (set (reg:QI D_REGNUM) (match_dup 1))
+   (set (match_dup 2) (reg:QI D_REGNUM))
+   (set (reg:QI D_REGNUM) (mem:QI (post_inc:HI (reg:HI SP_REGNUM))))
+   (use (reg:HI SP_REGNUM))]
+   "")
+
 ;;
 ;; Reorganize to optimize address computations.
 ;;
@@ -7004,6 +7216,36 @@
   "")
 
 ;;
+;; Replace: "ldx #N; xgdx; addd <var>; xgdx" by "ldab #N; ldx <var>; abx"
+;;
+(define_peephole2
+  [(set (match_operand:HI 0 "hard_reg_operand" "")
+	(match_operand:HI 1 "const_int_operand" ""))
+   (set (match_dup 0)
+	(plus:HI (match_dup 0)
+	         (match_operand:HI 2 "general_operand" "")))
+   (match_scratch:QI 3 "d")]
+  "TARGET_M6811 && (INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0x0ff)"
+  [(set (match_dup 3) (match_dup 4))
+   (set (match_dup 0) (match_dup 2))
+   (set (match_dup 0) (plus:HI (zero_extend:HI (match_dup 3)) (match_dup 0)))]
+  "operands[4] = m68hc11_gen_lowpart (QImode, operands[1]);")
+
+;;
+;; Replace: "ldx #N; xgdx; addd <var>; xgdx" by "ldab #N; ldx <var>; abx"
+;;
+(define_peephole2
+  [(set (match_operand:HI 0 "hard_reg_operand" "")
+	(match_operand:HI 1 "const_int_operand" ""))
+   (set (match_dup 0)
+	(plus:HI (match_dup 0)
+	         (match_operand:HI 2 "general_operand" "")))]
+  "TARGET_M6812"
+  [(set (match_dup 0) (match_dup 2))
+   (set (match_dup 0) (plus:HI (match_dup 0) (match_dup 1)))]
+  "")
+
+;;
 ;; Optimize an address register increment and a compare to use
 ;; a PRE_INC or PRE_DEC addressing mode (disabled on the tst insn
 ;; before reload, but can be enabled after).
@@ -7095,6 +7337,31 @@
   "")
 
 ;;
+;;
+;;
+(define_peephole2
+  [(parallel 
+     [(set (match_operand:SI 0 "hard_reg_operand" "")
+	(ashift:SI (match_operand:SI 1 "general_operand" "")
+		   (const_int 1)))
+      (clobber (match_scratch:HI 2 ""))])
+   (set (match_operand:HI 3 "nonimmediate_operand" "") (reg:HI D_REGNUM))
+   (set (match_operand:HI 4 "nonimmediate_operand" "") (reg:HI X_REGNUM))]
+  "!X_REG_P (operands[1])
+   && peep2_reg_dead_p (2, gen_rtx (REG, HImode, D_REGNUM))
+   && peep2_reg_dead_p (3, gen_rtx (REG, HImode, X_REGNUM))"
+  [(set (reg:HI D_REGNUM) (match_dup 5))
+   (set (reg:HI D_REGNUM) (ashift:HI (reg:HI D_REGNUM) (const_int 1)))
+   (set (match_dup 3) (reg:HI D_REGNUM))
+   (set (reg:HI D_REGNUM) (match_dup 6))
+   (parallel [(set (reg:HI D_REGNUM)
+		   (rotate:HI (reg:HI D_REGNUM) (const_int 1)))
+              (clobber (reg:HI CC_REGNUM))])
+   (set (match_dup 4) (reg:HI D_REGNUM))]
+  "operands[5] = m68hc11_gen_lowpart (HImode, operands[1]);
+   operands[6] = m68hc11_gen_highpart (HImode, operands[1]);")
+
+;;
 ;; Replace a "ldd <mem>; psha; pshb" with a "ldx <mem>; pshx".
 ;;
 (define_peephole2
@@ -7109,6 +7376,25 @@
   "")
 
 ;;
+;; Remove one load when copying a value to/from memory and also
+;; to a register.  Take care not cloberring a possible register used
+;; by operand 2.
+;; Replace: "ldd 0,y; std 2,y; ldx 0,y" into "ldx 0,y; stx 2,y"
+;;
+(define_peephole2
+  [(set (match_operand:HI 0 "hard_reg_operand" "")
+        (match_operand:HI 1 "general_operand" ""))
+   (set (match_operand:HI 2 "nonimmediate_operand" "") (match_dup 0))
+   (set (match_operand:HI 3 "hard_reg_operand" "") (match_dup 1))]
+  "peep2_reg_dead_p (2, operands[0])
+   && !side_effects_p (operands[1])
+   && !side_effects_p (operands[2])
+   && !reg_mentioned_p (operands[3], operands[2])"
+  [(set (match_dup 3) (match_dup 1))
+   (set (match_dup 2) (match_dup 3))]
+  "")
+
+;;
 ;; Replace a "ldd <mem>; addd #N; std <mem>" into a
 ;; "ldx <mem>; leax; stx <mem>" if we have a free X/Y register
 ;; and the constant is small.
@@ -7131,6 +7417,174 @@
   "if (reg_mentioned_p (operands[4], operands[1])) FAIL;
    if (reg_mentioned_p (operands[4], operands[3])) FAIL;")
 
+;;--------------------------------------------------------------------
+;;- Bset peephole2
+;;--------------------------------------------------------------------
+;; These peepholes try to replace some logical sequences by 'bset' and 'bclr'.
+;;
+;; Replace 'ldab <mem>; orab #N; stab <mem>' by 'bset <mem> #N'.
+;; Register D must be dead and there must be no register side effects for mem.
+;; The <mem> *can* be volatile this is why we must not use 'side_effects_p'.
+;; The good side effect is that it makes the sequence atomic.
+;;
+(define_peephole2
+  [(set (match_operand:QI 0 "hard_reg_operand" "")
+	(match_operand:QI 1 "nonimmediate_operand" ""))
+   (set (match_dup 0) (ior:QI (match_dup 0)
+			      (match_operand:QI 2 "const_int_operand" "")))
+   (set (match_dup 1) (match_dup 0))]
+  "(TARGET_M6812 || m68hc11_indirect_p (operands[1], QImode))
+   && (GET_CODE (operands[1]) != MEM || !auto_inc_p (XEXP (operands[1], 0)))
+   && peep2_reg_dead_p (3, operands[0])"
+  [(set (match_dup 1) (ior:QI (match_dup 1) (match_dup 2)))]
+  "")
+
+(define_peephole2
+  [(set (match_operand:HI 0 "hard_reg_operand" "")
+	(match_operand:HI 1 "nonimmediate_operand" ""))
+   (set (match_dup 0) (ior:HI (match_dup 0)
+			      (match_operand:HI 2 "const_int_operand" "")))
+   (set (match_dup 1) (match_dup 0))]
+  "(TARGET_M6812 || m68hc11_indirect_p (operands[1], HImode))
+   && (GET_CODE (operands[1]) != MEM || !auto_inc_p (XEXP (operands[1], 0)))
+   && peep2_reg_dead_p (3, operands[0])"
+  [(set (match_dup 1) (ior:HI (match_dup 1) (match_dup 2)))]
+  "")
+
+;;--------------------------------------------------------------------
+;;- Bclr peephole2
+;;--------------------------------------------------------------------
+;; Replace 'ldab <mem>; andab #N; stab <mem>' by 'bclr <mem> #N'.
+;; See Bset peephole2.
+;;
+(define_peephole2
+  [(set (match_operand:QI 0 "hard_reg_operand" "")
+	(match_operand:QI 1 "nonimmediate_operand" ""))
+   (set (match_dup 0) (and:QI (match_dup 0)
+			      (match_operand:QI 2 "const_int_operand" "")))
+   (set (match_dup 1) (match_dup 0))]
+  "(TARGET_M6812 || m68hc11_indirect_p (operands[1], QImode))
+   && (GET_CODE (operands[1]) != MEM || !auto_inc_p (XEXP (operands[1], 0)))
+   && peep2_reg_dead_p (3, operands[0])"
+  [(set (match_dup 1) (and:QI (match_dup 1) (match_dup 2)))]
+  "")
+
+(define_peephole2
+  [(set (match_operand:HI 0 "hard_reg_operand" "")
+	(match_operand:HI 1 "nonimmediate_operand" ""))
+   (set (match_dup 0) (and:HI (match_dup 0)
+			      (match_operand:HI 2 "const_int_operand" "")))
+   (set (match_dup 1) (match_dup 0))]
+  "(TARGET_M6812 || m68hc11_indirect_p (operands[1], HImode))
+   && (GET_CODE (operands[1]) != MEM || !auto_inc_p (XEXP (operands[1], 0)))
+   && peep2_reg_dead_p (3, operands[0])"
+  [(set (match_dup 1) (and:HI (match_dup 1) (match_dup 2)))]
+  "")
+
+
+;;--------------------------------------------------------------------
+;;- Compare peephole2
+;;--------------------------------------------------------------------
+(define_peephole2
+  [(set (match_operand:HI 0 "hard_reg_operand" "")
+	(match_operand:HI 1 "hard_reg_operand" ""))
+   (set (match_dup 1) (plus:HI (match_dup 1) 
+                               (match_operand:HI 2 "const_int_operand" "")))
+   (set (cc0) (match_dup 0))]
+  "peep2_reg_dead_p (3, operands[0]) && !Z_REG_P (operands[1])"
+  [(set (match_dup 1) (plus:HI (match_dup 1) (match_dup 2)))
+   (set (cc0) (compare (match_dup 1) (match_dup 2)))]
+  "")
+
+(define_peephole2
+  [(set (match_operand:HI 0 "hard_reg_operand" "")
+	(match_operand:HI 1 "hard_reg_operand" ""))
+   (set (match_operand:HI 2 "hard_reg_operand" "")
+        (plus:HI (match_dup 2) 
+                 (match_operand:HI 3 "const_int_operand" "")))
+   (set (match_operand:HI 4 "memory_operand" "") (match_dup 2))
+   (set (cc0) (match_operand:HI 5 "hard_reg_operand" ""))]
+  "peep2_reg_dead_p (4, operands[5]) && !Z_REG_P (operands[2])
+   && !reg_mentioned_p (operands[2], operands[4])
+
+   && ((rtx_equal_p (operands[5], operands[0])
+        && rtx_equal_p (operands[2], operands[1]))
+
+       || (rtx_equal_p (operands[5], operands[1])
+           && rtx_equal_p (operands[2], operands[0])))"
+  [(set (match_dup 2) (match_dup 1))
+   (set (match_dup 2) (plus:HI (match_dup 2) (match_dup 3)))
+   (set (match_dup 4) (match_dup 2))
+   (set (cc0) (compare (match_dup 2) (match_dup 3)))]
+  "")
+
+
+;;--------------------------------------------------------------------
+;;- Load peephole2
+;;--------------------------------------------------------------------
+;;
+;; Optimize initialization of 2 hard regs from the same memory location
+;; Since we can't copy easily X, Y and D to each other, load the 2 registers
+;; from the same memory location.
+;;
+(define_peephole2
+  [(set (match_operand:HI 0 "hard_reg_operand" "")
+	(match_operand:HI 1 "memory_operand" ""))
+   (set (match_operand:HI 2 "hard_reg_operand" "") (match_dup 0))]
+  "TARGET_M6811
+   && !side_effects_p (operands[1])
+   && !reg_mentioned_p (operands[0], operands[1])"
+  [(set (match_dup 0) (match_dup 1))
+   (set (match_dup 2) (match_dup 1))]
+  "")
+
+;; Replace "ldd #N; addd <op>" with "ldd <op>; addd #N".
+;;
+(define_peephole2
+  [(set (match_operand:HI 0 "nonimmediate_operand" "") (const_int 0))
+   (set (match_operand:HI 1 "nonimmediate_operand" "") (const_int 0))
+   (set (match_operand:HI 2 "nonimmediate_operand" "") (const_int 0))
+   (set (match_operand:HI 3 "nonimmediate_operand" "") (const_int 0))
+   (match_scratch:HI 4 "d")]
+  ""
+  [(set (match_dup 4) (const_int 0))
+   (set (match_dup 0) (match_dup 4))
+   (set (match_dup 1) (match_dup 4))
+   (set (match_dup 2) (match_dup 4))
+   (set (match_dup 3) (match_dup 4))]
+  "")
+
+;;
+;; Replace "ldd #N; addd <op>" with "ldd <op>; addd #N".
+;;
+(define_peephole2
+  [(set (match_operand:HI 0 "nonimmediate_operand" "") (const_int 0))
+   (set (match_operand:HI 1 "nonimmediate_operand" "") (const_int 0))
+   (set (match_operand:HI 2 "nonimmediate_operand" "") (const_int 0))
+   (match_scratch:HI 3 "d")]
+  ""
+  [(set (match_dup 3) (const_int 0))
+   (set (match_dup 0) (match_dup 3))
+   (set (match_dup 1) (match_dup 3))
+   (set (match_dup 2) (match_dup 3))]
+  "")
+
+;;
+;; Replace "ldd #N; addd <op>" with "ldd <op>; addd #N".
+;;
+(define_peephole2
+  [(set (match_operand:HI 0 "hard_reg_operand" "") (const_int 0))
+   (set (match_operand:HI 1 "push_operand" "") (match_dup 0))
+   (set (match_operand:HI 2 "push_operand" "") (match_dup 0))
+   (set (match_operand:HI 3 "push_operand" "") (match_dup 0))
+   (match_scratch:HI 4 "x")]
+  "TARGET_M6811 && D_REG_P (operands[0]) && peep2_reg_dead_p (4, operands[0])"
+  [(set (match_dup 4) (const_int 0))
+   (set (match_dup 1) (match_dup 4))
+   (set (match_dup 2) (match_dup 4))
+   (set (match_dup 3) (match_dup 4))]
+  "")
+
 ;;
 ;; This peephole catches the address computations generated by the reload
 ;; pass. 
@@ -7189,6 +7643,8 @@
 }
 ")
 
+;; SCz 2005-04-03: this peephole is not valid anymore because it appears
+;; we can't rely on the REG_DEAD note
 (define_peephole
   [(set (match_operand:HI 0 "hard_reg_operand" "h")
 	(match_operand:HI 1 "non_push_operand" "g"))
@@ -7279,7 +7735,7 @@
 
 ;;;
 ;;; Catch an xgdx/xgdy followed by a (set D X/Y). If X/Y is dead, we don't
-;;; need to emit anything. Otherwise, we just need an copy of D to X/Y.
+;;; need to emit anything. Otherwise, we just need a copy of D to X/Y.
 ;;;
 (define_peephole
   [(parallel [(set (reg:HI D_REGNUM) (match_operand:HI 0 "hard_reg_operand" "A"))
@@ -7295,7 +7751,7 @@
 
 ;;;
 ;;; Catch an xgdx/xgdy followed by a (set D X/Y). If X/Y is dead, we don't
-;;; need to emit anything. Otherwise, we just need an copy of D to X/Y.
+;;; need to emit anything. Otherwise, we just need a copy of D to X/Y.
 ;;;
 (define_peephole
   [(parallel [(set (reg:HI D_REGNUM) (match_operand:HI 0 "hard_reg_operand" "A"))
@@ -7400,3 +7856,41 @@
   return \"sts\\t%t0\\n\\tld%0\\t%t0\";
 }
 ")
+
+(define_peephole
+  [(set (match_operand:HI 0 "hard_reg_operand" "")
+	(match_operand:HI 1 "memory_operand" ""))
+   (set (match_operand:HI 2 "hard_reg_operand" "") (match_dup 0))]
+  "TARGET_M6811
+   && !side_effects_p (operands[1])
+   && !reg_mentioned_p (operands[0], operands[1])"
+  "*
+{
+  rtx ops[2];
+
+  ops[0] = operands[0];
+  ops[1] = operands[1];
+  m68hc11_gen_movhi (insn, ops);
+  ops[0] = operands[2];
+  m68hc11_gen_movhi (insn, ops);
+  return \"\";
+}")
+
+;; Peephole for Z register replacement.
+;; Avoid to use _.tmp register when comparing D and X if we can compare
+;; with soft register
+(define_peephole
+  [(set (match_operand:HI 0 "hard_reg_operand" "") (reg:HI SOFT_XY_REGNUM))
+   (set (reg:HI SOFT_TMP_REGNUM) (match_dup 0))
+   (set (cc0) (compare (match_operand:HI 2 "hard_reg_operand" "")
+                       (reg:HI SOFT_TMP_REGNUM)))]
+  "X_REG_P (operands[0]) || Y_REG_P (operands[0])"
+  "*
+{
+  rtx ops[2];
+
+  ops[0] = operands[0];
+  ops[1] = operands[1];
+  m68hc11_gen_movhi (insn, ops);
+  return \"cp%2\\t%1\";
+}")
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/config/m68hc11/t-m68hc11-gas gcc-3.3.6-m68hc1x/gcc/config/m68hc11/t-m68hc11-gas
--- gcc-3.3.6/gcc/config/m68hc11/t-m68hc11-gas	Fri Jan 28 23:21:39 2005
+++ gcc-3.3.6-m68hc1x/gcc/config/m68hc11/t-m68hc11-gas	Sat Nov  5 19:17:25 2005
@@ -37,7 +37,7 @@ LIB2FUNCS_EXTRA = $(srcdir)/config/udivm
 LIBGCC2_DEBUG_CFLAGS =-g
 LIBGCC2_CFLAGS = -Os -mrelax $(LIBGCC2_INCLUDES) $(TARGET_LIBGCC2_CFLAGS) $(LIBGCC2_DEBUG_CFLAGS) $(GTHREAD_FLAGS) -DIN_LIBGCC2
 
-MULTILIB_OPTIONS  = m68hc11/m68hc12 mshort fshort-double
+MULTILIB_OPTIONS  = m68hc11/m68hc12 mshort fshort-double mlong-calls
 MULTILIB_DIRNAMES =
 MULTILIB_MATCHES  = m68hc11=m6811 m68hc12=m6812 m68hc12=m68hcs12
 MULTILIB_EXCEPTIONS = -mnoshort -mno68hc11
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/config/udivmod.c gcc-3.3.6-m68hc1x/gcc/config/udivmod.c
--- gcc-3.3.6/gcc/config/udivmod.c	Thu Nov 30 09:25:58 2000
+++ gcc-3.3.6-m68hc1x/gcc/config/udivmod.c	Sat Nov  5 19:17:25 2005
@@ -1,14 +1,18 @@
-long udivmodsi4 ();
+extern unsigned long __udivmodsi4 (unsigned long num, unsigned long den,
+                                   unsigned long *mod);
 
-long
-__udivsi3 (long a, long b)
+unsigned long
+__udivsi3 (unsigned long a, unsigned long b)
 {
-  return udivmodsi4 (a, b, 0);
+  return __udivmodsi4 (a, b, 0);
 }
 
-long
-__umodsi3 (long a, long b)
+unsigned long
+__umodsi3 (unsigned long a, unsigned long b)
 {
-  return udivmodsi4 (a, b, 1);
+  unsigned long mod;
+
+  __udivmodsi4 (a, b, &mod);
+  return mod;
 }
 
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/config/udivmodsi4.c gcc-3.3.6-m68hc1x/gcc/config/udivmodsi4.c
--- gcc-3.3.6/gcc/config/udivmodsi4.c	Thu Nov 30 09:25:58 2000
+++ gcc-3.3.6-m68hc1x/gcc/config/udivmodsi4.c	Sat Nov  5 19:17:25 2005
@@ -1,10 +1,57 @@
 unsigned long
-udivmodsi4(unsigned long num, unsigned long den, int modwanted)
+__udivmodsi4 (unsigned long num, unsigned long den, unsigned long* mod)
 {
-  unsigned long bit = 1;
-  unsigned long res = 0;
+  unsigned long bit;
+  unsigned long res;
+  
+  if ((unsigned short) (den >> 16) == 0)
+    {
+#ifdef mc68hc11
+      if ((unsigned short) (num >> 16) == 0)
+        {
+          /* Both numbers are 16-bit quantities, use 16-bit div/mod.  */
+          unsigned short sden = (unsigned short) den;
+          unsigned short snum = (unsigned short) num;
+          unsigned short sres = snum / sden;
+          unsigned short smod = snum % sden;;
+
+          if (mod)
+            *mod = (unsigned long) smod;
+          return (unsigned long) sres;
+        }
+#endif
+#ifdef mc68hc12
+        {
+          /* To avoid to stress the gcc reload, use + operand modifier
+             and pass the input values in the same variables as the
+             outputs.  */
+          unsigned short status = (unsigned short) den;
+          unsigned short smod = (unsigned short) (num & 0x0ffff);
+          unsigned short sres = (unsigned short) (num >> 16);
 
-  while (den < num && bit && !(den & (1L<<31)))
+          __asm__ __volatile__ ("ediv\n"
+                                "tfr ccr,x"
+                                : "+x" (status), "+y" (sres),
+                                  "+d" (smod));
+          /* check for overflow */
+          if (!(status & 0x03))
+            {
+              if (mod)
+                *mod = (unsigned long) smod;
+              return (unsigned long) sres;
+            }
+        }
+#endif
+      if ((unsigned short) den == 0)
+        {
+          if (mod)
+            *mod = 0;
+          return 0;
+        }
+    }
+  bit = 1;
+  res = 0;
+  while (den < num && !((unsigned short) (den >> 16) & (1L<<15)))
     {
       den <<=1;
       bit <<=1;
@@ -19,6 +66,25 @@ udivmodsi4(unsigned long num, unsigned l
       bit >>=1;
       den >>=1;
     }
-  if (modwanted) return num;
+  if (mod)
+    *mod = num;
   return res;
 }
+
+#ifdef L_udivmodsi4
+unsigned long
+udivmodsi4 (unsigned long num, unsigned long den, int modwanted)
+{
+  unsigned long mod;
+
+  if (modwanted)
+    {
+      __udivmodsi4 (num, den, &mod);
+      return mod;
+    }
+  else
+    {
+      return __udivmodsi4 (num, den, 0);
+    }
+}
+#endif
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/cppdefault.c gcc-3.3.6-m68hc1x/gcc/cppdefault.c
--- gcc-3.3.6/gcc/cppdefault.c	Fri Nov  7 00:13:31 2003
+++ gcc-3.3.6-m68hc1x/gcc/cppdefault.c	Sat Nov  5 19:17:25 2005
@@ -76,10 +76,14 @@ const struct default_include cpp_include
 
 #ifdef GCC_INCLUDE_DIR
 const char cpp_GCC_INCLUDE_DIR[] = GCC_INCLUDE_DIR;
+#if GNU_HC1X_DONT_PATCH
 const size_t cpp_GCC_INCLUDE_DIR_len = sizeof GCC_INCLUDE_DIR - 8;
+#endif
 #else
 const char cpp_GCC_INCLUDE_DIR[] = "";
+#if GNU_HC1X_DONT_PATCH
 const size_t cpp_GCC_INCLUDE_DIR_len = 0;
+#endif
 #endif
 
 #ifdef TARGET_SYSTEM_ROOT
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/cppdefault.h gcc-3.3.6-m68hc1x/gcc/cppdefault.h
--- gcc-3.3.6/gcc/cppdefault.h	Fri Nov  7 00:13:31 2003
+++ gcc-3.3.6-m68hc1x/gcc/cppdefault.h	Sat Nov  5 19:17:25 2005
@@ -67,7 +67,17 @@ struct default_include
 
 extern const struct default_include cpp_include_defaults[];
 extern const char cpp_GCC_INCLUDE_DIR[];
+
+/* Don't use sizeof GCC_INCLUDE_DIR because for Mingw32 we patch the
+   executable to replace this path with the good path.  We must then
+   use strlen() to find the correct length.  */
+#undef GNU_HC1X_DONT_PATCH
+#if GNU_HC1X_DONT_PATCH
 extern const size_t cpp_GCC_INCLUDE_DIR_len;
+#else
+#define cpp_GCC_INCLUDE_DIR_len \
+(strlen (cpp_GCC_INCLUDE_DIR) > 7 ? strlen (cpp_GCC_INCLUDE_DIR) - 7 : 0)
+#endif
 
 extern const char *cpp_SYSROOT;
 
+timestamp
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/expmed.c gcc-3.3.6-m68hc1x/gcc/expmed.c
--- gcc-3.3.6/gcc/expmed.c	Sat Apr 30 18:01:29 2005
+++ gcc-3.3.6-m68hc1x/gcc/expmed.c	Sat Nov  5 22:00:59 2005
@@ -474,6 +474,15 @@ store_bit_field (str_rtx, bitsize, bitnu
 	 result in an abort.  */
       fieldmode = smallest_mode_for_size (nwords * BITS_PER_WORD, MODE_INT);
 
+      /* When the value is a constant, the constant_subword applies a
+         correction on big endian targets.  If the bitfield contains less words
+         than the value (fieldmode), the constant that is extracted is shifted
+         by the word difference.  Example: bitfield = 33, fieldmode = DImode
+         and constant_subword extracts word 1 2 3 instead of 0 1 2.  */
+      int correction = 0;
+      if (WORDS_BIG_ENDIAN && CONSTANT_P (value))
+        correction = GET_MODE_BITSIZE (fieldmode) / BITS_PER_WORD - nwords;
+
       for (i = 0; i < nwords; i++)
 	{
 	  /* If I is 0, use the low-order word in both field and target;
@@ -488,7 +497,7 @@ store_bit_field (str_rtx, bitsize, bitnu
 	  store_bit_field (op0, MIN (BITS_PER_WORD,
 				     bitsize - i * BITS_PER_WORD),
 			   bitnum + bit_offset, word_mode,
-			   operand_subword_force (value, wordnum,
+			   operand_subword_force (value, correction + wordnum,
 						  (GET_MODE (value) == VOIDmode
 						   ? fieldmode
 						   : GET_MODE (value))),
@@ -2142,7 +2151,7 @@ synth_mult (alg_out, t, cost_limit)
   if ((t & 1) == 0)
     {
       m = floor_log2 (t & -t);	/* m = number of low zero bits */
-      if (m < BITS_PER_WORD)
+      if (m < MAX_BITS_PER_WORD)
 	{
 	  q = t >> m;
 	  cost = shift_cost[m];
@@ -2227,7 +2236,7 @@ synth_mult (alg_out, t, cost_limit)
       unsigned HOST_WIDE_INT d;
 
       d = ((unsigned HOST_WIDE_INT) 1 << m) + 1;
-      if (t % d == 0 && t > d && m < BITS_PER_WORD)
+      if (t % d == 0 && t > d && m < MAX_BITS_PER_WORD)
 	{
 	  cost = MIN (shiftadd_cost[m], add_cost + shift_cost[m]);
 	  synth_mult (alg_in, t / d, cost_limit - cost);
@@ -2246,7 +2255,7 @@ synth_mult (alg_out, t, cost_limit)
 	}
 
       d = ((unsigned HOST_WIDE_INT) 1 << m) - 1;
-      if (t % d == 0 && t > d && m < BITS_PER_WORD)
+      if (t % d == 0 && t > d && m < MAX_BITS_PER_WORD)
 	{
 	  cost = MIN (shiftsub_cost[m], add_cost + shift_cost[m]);
 	  synth_mult (alg_in, t / d, cost_limit - cost);
@@ -2271,7 +2280,7 @@ synth_mult (alg_out, t, cost_limit)
       q = t - 1;
       q = q & -q;
       m = exact_log2 (q);
-      if (m >= 0 && m < BITS_PER_WORD)
+      if (m >= 0 && m < MAX_BITS_PER_WORD)
 	{
 	  cost = shiftadd_cost[m];
 	  synth_mult (alg_in, (t - 1) >> m, cost_limit - cost);
@@ -2290,7 +2299,7 @@ synth_mult (alg_out, t, cost_limit)
       q = t + 1;
       q = q & -q;
       m = exact_log2 (q);
-      if (m >= 0 && m < BITS_PER_WORD)
+      if (m >= 0 && m < MAX_BITS_PER_WORD)
 	{
 	  cost = shiftsub_cost[m];
 	  synth_mult (alg_in, (t + 1) >> m, cost_limit - cost);
@@ -2793,7 +2802,7 @@ expand_mult_highpart (mode, op0, cnst1, 
 
   /* expand_mult handles constant multiplication of word_mode
      or narrower.  It does a poor job for large modes.  */
-  if (size < BITS_PER_WORD
+  if (size < MAX_BITS_PER_WORD
       && mul_cost[(int) wider_mode] + shift_cost[size-1] < max_cost)
     {
       /* We have to do this, since expand_binop doesn't do conversion for
@@ -2824,7 +2833,7 @@ expand_mult_highpart (mode, op0, cnst1, 
 
   /* Secondly, same as above, but use sign flavor opposite of unsignedp.
      Need to adjust the result after the multiplication.  */
-  if (size - 1 < BITS_PER_WORD
+  if (size - 1 < MAX_BITS_PER_WORD
       && (mul_highpart_cost[(int) mode] + 2 * shift_cost[size-1] + 4 * add_cost
 	  < max_cost))
     {
@@ -2849,7 +2858,7 @@ expand_mult_highpart (mode, op0, cnst1, 
   /* Try widening the mode and perform a non-widening multiplication.  */
   moptab = smul_optab;
   if (smul_optab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing
-      && size - 1 < BITS_PER_WORD
+      && size - 1 < MAX_BITS_PER_WORD
       && mul_cost[(int) wider_mode] + shift_cost[size-1] < max_cost)
     {
       op1 = wide_op1;
@@ -2859,7 +2868,7 @@ expand_mult_highpart (mode, op0, cnst1, 
   /* Try widening multiplication of opposite signedness, and adjust.  */
   moptab = unsignedp ? smul_widen_optab : umul_widen_optab;
   if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing
-      && size - 1 < BITS_PER_WORD
+      && size - 1 < MAX_BITS_PER_WORD
       && (mul_widen_cost[(int) wider_mode]
 	  + 2 * shift_cost[size-1] + 4 * add_cost < max_cost))
     {
@@ -3199,7 +3208,7 @@ expand_divmod (rem_flag, code, mode, op0
 			  {
 			    rtx t1, t2, t3, t4;
 
-			    if (post_shift - 1 >= BITS_PER_WORD)
+			    if (post_shift - 1 >= MAX_BITS_PER_WORD)
 			      goto fail1;
 
 			    extra_cost = (shift_cost[post_shift - 1]
@@ -3226,8 +3235,8 @@ expand_divmod (rem_flag, code, mode, op0
 			  {
 			    rtx t1, t2;
 
-			    if (pre_shift >= BITS_PER_WORD
-				|| post_shift >= BITS_PER_WORD)
+			    if (pre_shift >= MAX_BITS_PER_WORD
+				|| post_shift >= MAX_BITS_PER_WORD)
 			      goto fail1;
 
 			    t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
@@ -3363,8 +3372,8 @@ expand_divmod (rem_flag, code, mode, op0
 		      {
 			rtx t1, t2, t3;
 
-			if (post_shift >= BITS_PER_WORD
-			    || size - 1 >= BITS_PER_WORD)
+			if (post_shift >= MAX_BITS_PER_WORD
+			    || size - 1 >= MAX_BITS_PER_WORD)
 			  goto fail1;
 
 			extra_cost = (shift_cost[post_shift]
@@ -3393,8 +3402,8 @@ expand_divmod (rem_flag, code, mode, op0
 		      {
 			rtx t1, t2, t3, t4;
 
-			if (post_shift >= BITS_PER_WORD
-			    || size - 1 >= BITS_PER_WORD)
+			if (post_shift >= MAX_BITS_PER_WORD
+			    || size - 1 >= MAX_BITS_PER_WORD)
 			  goto fail1;
 
 			ml |= (~(unsigned HOST_WIDE_INT) 0) << (size - 1);
@@ -3480,8 +3489,8 @@ expand_divmod (rem_flag, code, mode, op0
 		    if (mh)
 		      abort ();
 
-		    if (post_shift < BITS_PER_WORD
-			&& size - 1 < BITS_PER_WORD)
+		    if (post_shift < MAX_BITS_PER_WORD
+			&& size - 1 < MAX_BITS_PER_WORD)
 		      {
 			t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
 					   build_int_2 (size - 1, 0),
@@ -4135,8 +4144,12 @@ make_tree (type, x)
 
     case SIGN_EXTEND:
     case ZERO_EXTEND:
-      t = (*lang_hooks.types.type_for_mode) (GET_MODE (XEXP (x, 0)),
-					     GET_CODE (x) == ZERO_EXTEND);
+      if (CONSTANT_P (XEXP (x, 0)))
+        t = (*lang_hooks.types.type_for_mode) (GET_MODE (x),
+					       GET_CODE (x) == ZERO_EXTEND);
+      else
+        t = (*lang_hooks.types.type_for_mode) (GET_MODE (XEXP (x, 0)),
+					       GET_CODE (x) == ZERO_EXTEND);
       return fold (convert (type, make_tree (t, XEXP (x, 0))));
 
    default:
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/final.c gcc-3.3.6-m68hc1x/gcc/final.c
--- gcc-3.3.6/gcc/final.c	Mon Dec  1 09:18:36 2003
+++ gcc-3.3.6-m68hc1x/gcc/final.c	Sat Nov  5 19:17:25 2005
@@ -2909,7 +2909,22 @@ alter_subreg (xp)
   /* simplify_subreg does not remove subreg from volatile references.
      We are required to.  */
   if (GET_CODE (y) == MEM)
-    *xp = adjust_address (y, GET_MODE (x), SUBREG_BYTE (x));
+    {
+      unsigned outer_size = GET_MODE_SIZE (GET_MODE (x));
+      unsigned inner_size = GET_MODE_SIZE (GET_MODE (y));
+      int offset = SUBREG_BYTE (x);
+      
+      /* If this is a paradoxical subreg with a SUBREG_BYTE set
+         to 0 we must adjust the offset for big-endian machines
+         (otherwise we take the address of the high part).  */
+      if (BYTES_BIG_ENDIAN && !offset && outer_size > inner_size)
+        {
+          offset += MIN (inner_size, UNITS_PER_WORD);
+          offset -= MIN (outer_size, UNITS_PER_WORD);
+        }
+
+      *xp = adjust_address (y, GET_MODE (x), offset);
+    }
   else
     {
       rtx new = simplify_subreg (GET_MODE (x), y, GET_MODE (y),
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/flow.c gcc-3.3.6-m68hc1x/gcc/flow.c
--- gcc-3.3.6/gcc/flow.c	Sat Dec  4 01:36:35 2004
+++ gcc-3.3.6-m68hc1x/gcc/flow.c	Sat Nov  5 19:17:25 2005
@@ -571,7 +571,7 @@ verify_local_live_at_start (new_live_at_
 	      fputs ("Old:\n", rtl_dump_file);
 	      dump_bb (bb, rtl_dump_file);
 	    }
-	  abort ();
+	  // SCz: abort ();
 	}
     }
   else
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/gcse.c gcc-3.3.6-m68hc1x/gcc/gcse.c
--- gcc-3.3.6/gcc/gcse.c	Sat Dec 20 20:59:50 2003
+++ gcc-3.3.6-m68hc1x/gcc/gcse.c	Sat Nov  5 19:17:25 2005
@@ -3513,8 +3513,7 @@ handle_avail_expr (insn, expr)
       /* ??? If the change fails, we return 0, even though we created
 	 an insn.  I think this is ok.  */
       new_insn
-	= emit_insn_after (gen_rtx_SET (VOIDmode, to,
-					SET_DEST (expr_set)),
+	= emit_insn_after (gen_move_insn (to, SET_DEST (expr_set)),
 			   insn_computes_expr);
 
       /* Keep register set table up to date.  */
@@ -3525,7 +3524,7 @@ handle_avail_expr (insn, expr)
 	{
 	  fprintf (gcse_file, "GCSE: Creating insn %d to copy value of reg %d",
 		   INSN_UID (NEXT_INSN (insn_computes_expr)),
-		   REGNO (SET_SRC (PATTERN (NEXT_INSN (insn_computes_expr)))));
+		   REGNO (SET_DEST (expr_set)));
 	  fprintf (gcse_file, ", computed in insn %d,\n",
 		   INSN_UID (insn_computes_expr));
 	  fprintf (gcse_file, "      into newly allocated reg %d\n",
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/libgcc2.c gcc-3.3.6-m68hc1x/gcc/libgcc2.c
--- gcc-3.3.6/gcc/libgcc2.c	Wed Oct 23 12:47:24 2002
+++ gcc-3.3.6-m68hc1x/gcc/libgcc2.c	Sat Nov  5 19:17:25 2005
@@ -490,7 +490,12 @@ __udiv_w_sdiv (UWtype *rp __attribute__ 
 
 #if (defined (L_udivdi3) || defined (L_divdi3) || \
      defined (L_umoddi3) || defined (L_moddi3))
-#define L_udivmoddi4
+#if !defined(mc6811) && !defined(mc6812)
+# define L_udivmoddi4
+#else
+extern UDWtype
+__udivmoddi4 (UDWtype n, UDWtype d, UDWtype *rp);
+#endif
 #endif
 
 #ifdef L_clz
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/longlong.h gcc-3.3.6-m68hc1x/gcc/longlong.h
--- gcc-3.3.6/gcc/longlong.h	Thu Oct  3 22:39:08 2002
+++ gcc-3.3.6-m68hc1x/gcc/longlong.h	Sat Nov  5 19:17:25 2005
@@ -1162,6 +1162,67 @@ UDItype __umulsidi3 (USItype, USItype);
 
 #endif /* __GNUC__ */
 
+#if defined(mc6811) || defined(mc6812)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl)				\
+  do {									\
+    __asm__ ("subd 2+%2\n"						\
+             "\txgdx\n"							\
+             "\tsbcb 1+%2\n"						\
+             "\tsbca %2\n"						\
+             "\txgdx" : "=D"((USItype) (sl))				\
+		      : "0"((USItype) (al)), "m"((USItype) (bl)));	\
+    /* Assumes that the carry is not modified. */			\
+    /* which is true since the reload instructions */			\
+    /* generated between the two __asm__ only do load/store.  */	\
+    __asm__ ("sbcb 3+%2\n"						\
+             "\tsbca 2+%2\n"						\
+             "\txgdx\n"							\
+             "\tsbcb 1+%2\n"						\
+             "\tsbca %2\n"						\
+             "\txgdx" : "=D"((USItype) (sh))				\
+		      : "0"((USItype) (ah)), "m"((USItype) (bh)));	\
+  } while (0)
+#if defined(mc6812)
+#define umul_ppmm(w1, w0, u, v)						\
+  do {									\
+    UWtype __x0, __x1, __x2, __x3;					\
+									\
+    __x0 = ((UWtype) ((UHItype) __ll_lowpart (u))) * ((UWtype) ((UHItype) __ll_lowpart (v)));	\
+    __x1 = ((UWtype) ((UHItype) __ll_lowpart (u))) * ((UWtype) ((UHItype) __ll_highpart (v)));	\
+    __x2 = ((UWtype) ((UHItype) __ll_highpart (u))) * ((UWtype) ((UHItype) __ll_lowpart (v)));	\
+    __x3 = ((UWtype) ((UHItype) __ll_highpart (u))) * ((UWtype) ((UHItype) __ll_highpart (v)));	\
+									\
+    __x1 += __ll_highpart (__x0);/* this can't give carry */		\
+    __x1 += __x2;		/* but this indeed can */		\
+    __asm__ ("bcc 1f\n"                                                 \
+	     "\tinx\n"							\
+	     "1:" : "=D"(__x3) : "0"(__x3));				\
+									\
+    (w1) = __x3 + __ll_highpart (__x1);					\
+    (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0);		\
+  } while (0)
+#else
+#define umul_ppmm(w1, w0, u, v)						\
+  do {									\
+    UWtype __x0, __x1, __x2, __x3;					\
+    extern UWtype __attribute__((near)) __mulhi32 (UHItype, UHItype);	\
+									\
+    __x0 = __mulhi32 (__ll_lowpart (u), __ll_lowpart (v));		\
+    __x1 = __mulhi32 (__ll_lowpart (u), __ll_highpart (v));		\
+    __x2 = __mulhi32 (__ll_highpart (u), __ll_lowpart (v));		\
+    __x3 = __mulhi32 (__ll_highpart (u), __ll_highpart (v));		\
+									\
+    __x1 += __ll_highpart (__x0);/* this can't give carry */		\
+    __x1 += __x2;		/* but this indeed can */		\
+    __asm__ ("bcc 1f\n"                                                 \
+	     "\tinx\n"							\
+	     "1:" : "=D"(__x3) : "0"(__x3));				\
+									\
+    (w1) = __x3 + __ll_highpart (__x1);					\
+    (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0);		\
+  } while (0)
+#endif
+#endif     
 /* If this machine has no inline assembler, use C macros.  */
 
 #if !defined (add_ssaaaa)
@@ -1232,6 +1293,45 @@ UDItype __umulsidi3 (USItype, USItype);
 #endif
 
 /* Define this unconditionally, so it can be used for debugging.  */
+#if defined(mc6811) || defined(mc6812)
+extern USItype __udivmodsi4(USItype num, USItype den, USItype* mod);
+
+#define __udiv_qrnnd_c(q, r, n1, n0, d) \
+  do {									\
+    USItype __d1, __d0, __q1, __q0;					\
+    USItype __r0, __m;						\
+    __d1 = __ll_highpart (d);						\
+    __d0 = __ll_lowpart (d);						\
+									\
+    __q1 = __udivmodsi4 (n1,__d1,&__r0);				\
+    __m = (USItype) __q1 * __d0;					\
+    __r0 = __r0 * __ll_B | __ll_highpart (n0);				\
+    if (__r0 < __m)							\
+      {									\
+	__q1--, __r0 += (d);						\
+	if (__r0 >= (d)) /* i.e. we didn't get carry when adding to __r0 */\
+	  if (__r0 < __m)						\
+	    __q1--, __r0 += (d);					\
+      }									\
+    __r0 -= __m;							\
+									\
+    __q0 = __udivmodsi4 (__r0,__d1,&__r0);				\
+    __m = (USItype) __q0 * __d0;					\
+    __r0 = __r0 * __ll_B | __ll_lowpart (n0);				\
+    if (__r0 < __m)							\
+      {									\
+	__q0--, __r0 += (d);						\
+	if (__r0 >= (d))						\
+	  if (__r0 < __m)						\
+	    __q0--, __r0 += (d);					\
+      }									\
+    __r0 -= __m;							\
+									\
+    (q) = (USItype) __q1 * __ll_B | __q0;				\
+    (r) = __r0;								\
+  } while (0)
+#else
+/* Define this unconditionally, so it can be used for debugging.  */
 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
   do {									\
     UWtype __d1, __d0, __q1, __q0;					\
@@ -1268,6 +1368,7 @@ UDItype __umulsidi3 (USItype, USItype);
     (q) = (UWtype) __q1 * __ll_B | __q0;				\
     (r) = __r0;								\
   } while (0)
+#endif
 
 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
    __udiv_w_sdiv (defined in libgcc or elsewhere).  */
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/loop.c gcc-3.3.6-m68hc1x/gcc/loop.c
--- gcc-3.3.6/gcc/loop.c	Sun May 30 01:27:30 2004
+++ gcc-3.3.6-m68hc1x/gcc/loop.c	Sat Nov  5 19:17:25 2005
@@ -4703,7 +4703,8 @@ loop_givs_reduce (loop, bl)
 	     this is an address giv, then try to put the increment
 	     immediately after its use, so that flow can create an
 	     auto-increment addressing mode.  */
-	  if (v->giv_type == DEST_ADDR && bl->biv_count == 1
+	  if ((HAVE_POST_INCREMENT || HAVE_POST_DECREMENT)
+              && v->giv_type == DEST_ADDR && bl->biv_count == 1
 	      && bl->biv->always_executed && ! bl->biv->maybe_multiple
 	      /* We don't handle reversed biv's because bl->biv->insn
 		 does not have a valid INSN_LUID.  */
@@ -8979,7 +8980,13 @@ maybe_eliminate_biv_1 (loop, x, insn, bl
 		    || (GET_CODE (v->add_val) == REG
 			&& REG_POINTER (v->add_val)))
 		&& ! v->ignore && ! v->maybe_dead && v->always_computable
-		&& v->mode == mode)
+		&& v->mode == mode
+                /* SCz: There is a possible overflow here.
+                   If we compare to a constant value, the constant is
+                   re-computed (CST * mult_add + add_val) and there may
+                   be an overflow. CST was 16399, mult was 8, and integers
+                   are 16-bits.   (execute/loop-3c.c, -Os -mshort).  */
+                && 0)
 	      {
 		if (! biv_elimination_giv_has_0_offset (bl->biv, v, insn))
 		  continue;
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/regrename.c gcc-3.3.6-m68hc1x/gcc/regrename.c
--- gcc-3.3.6/gcc/regrename.c	Mon Nov  4 17:57:02 2002
+++ gcc-3.3.6-m68hc1x/gcc/regrename.c	Sat Nov  5 19:17:25 2005
@@ -102,6 +102,9 @@ note_sets (x, set, data)
   HARD_REG_SET *pset = (HARD_REG_SET *) data;
   unsigned int regno;
   int nregs;
+
+  if (GET_CODE (x) == SUBREG)
+    x = SUBREG_REG (x);
   if (GET_CODE (x) != REG)
     return;
   regno = REGNO (x);
@@ -292,6 +295,7 @@ regrename_optimize ()
 	  for (new_reg = 0; new_reg < FIRST_PSEUDO_REGISTER; new_reg++)
 	    {
 	      int nregs = HARD_REGNO_NREGS (new_reg, GET_MODE (*this->loc));
+              int mode = GET_MODE (*this->loc);
 
 	      for (i = nregs - 1; i >= 0; --i)
 	        if (TEST_HARD_REG_BIT (this_unavailable, new_reg + i)
@@ -307,7 +311,7 @@ regrename_optimize ()
 			&& !LEAF_REGISTERS[new_reg + i])
 #endif
 #ifdef HARD_REGNO_RENAME_OK
-		    || ! HARD_REGNO_RENAME_OK (reg + i, new_reg + i)
+		    || ! HARD_REGNO_RENAME_OK (reg + i, new_reg + i, mode)
 #endif
 		    )
 		  break;
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/reload.c gcc-3.3.6-m68hc1x/gcc/reload.c
--- gcc-3.3.6/gcc/reload.c	Fri Mar  5 18:09:34 2004
+++ gcc-3.3.6-m68hc1x/gcc/reload.c	Sun Jan 22 21:14:21 2006
@@ -4216,6 +4216,20 @@ find_reloads (insn, replace, ind_levels,
 
       if (goal_alternative_matches[rld[i].opnum] >= 0)
 	rld[i].opnum = goal_alternative_matches[rld[i].opnum];
+
+      /* If an operand's reload is RELOAD_OTHER, change any
+         RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_OUTPUT_ADDRESS reloads
+         of that operand to RELOAD_FOR_OTHER_ADDRESS.  This is necessary
+         to make sure the reloads are emitted in the good order.  We only need
+         to scan backward.  */
+      if (rld[i].when_needed == RELOAD_OTHER
+          && rld[i].optional == 0)
+        {
+          for (j = i - 1; j >= 0; j--)
+            if (rld[j].opnum == rld[i].opnum
+                && rld[j].when_needed == RELOAD_FOR_OPERAND_ADDRESS)
+              rld[j].when_needed = RELOAD_FOR_OTHER_ADDRESS;
+        }
     }
 
   /* Scan all the reloads, and check for RELOAD_FOR_OPERAND_ADDRESS reloads.
@@ -4556,10 +4570,8 @@ find_reloads_toplev (x, opnum, type, ind
 	 force a reload in that case.  So we should not do anything here.  */
 
       else if (regno >= FIRST_PSEUDO_REGISTER
-#ifdef LOAD_EXTEND_OP
 	       && (GET_MODE_SIZE (GET_MODE (x))
 		   <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
-#endif
 	       && (reg_equiv_address[regno] != 0
 		   || (reg_equiv_mem[regno] != 0
 		       && (! strict_memory_address_p (GET_MODE (x),
@@ -5913,7 +5925,7 @@ find_reloads_subreg_address (x, force_re
 		}
 
 	      find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
-				    &XEXP (tem, 0), opnum, ADDR_TYPE (type),
+				    &XEXP (tem, 0), opnum, type,
 				    ind_levels, insn);
 
 	      /* If this is not a toplevel operand, find_reloads doesn't see
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/reload1.c gcc-3.3.6-m68hc1x/gcc/reload1.c
--- gcc-3.3.6/gcc/reload1.c	Fri Nov 26 06:08:45 2004
+++ gcc-3.3.6-m68hc1x/gcc/reload1.c	Mon Jan 23 21:53:40 2006
@@ -1777,9 +1777,6 @@ find_reg (chain, order)
   if (best_reg == -1)
     return 0;
 
-  if (rtl_dump_file)
-    fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
-
   rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
   rl->regno = best_reg;
 
@@ -1930,6 +1927,7 @@ spill_failure (insn, class)
     {
       error ("unable to find a register to spill in class `%s'",
 	     reg_class_names[class]);
+
       fatal_insn ("this is the insn:", insn);
     }
 }
@@ -3979,7 +3977,7 @@ reload_as_needed (live_known)
 	     for this insn in order to be stored in
 	     (obeying register constraints).  That is correct; such reload
 	     registers ARE still valid.  */
-	  note_stores (oldpat, forget_old_reloads_1, NULL);
+         note_stores (oldpat, forget_old_reloads_1, NULL);
 
 	  /* There may have been CLOBBER insns placed after INSN.  So scan
 	     between INSN and NEXT and use them to forget old reloads.  */
@@ -4580,6 +4578,9 @@ reload_reg_reaches_end_p (regno, opnum, 
     case RELOAD_OTHER:
       /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
 	 its value must reach the end.  */
+      for (i = 0; i < reload_n_operands; i++)
+        if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
+          return 0;
       return 1;
 
       /* If this use is for part of the insn,
@@ -5298,6 +5299,13 @@ choose_reload_regs_init (chain, save_rel
   CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
   CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
 
+#if 0 /* TARGET_M68HC11 or NO_SPILL_REG_ROUND_ROBIN */
+  /* Don't use the round-robin fashion for allocation of spill registers.
+     If we use round-robin, the reload pass allocates Y and Z registers
+     which are expensive compared to X and D.  */
+  last_spill_reg = -1;
+#endif
+  
   CLEAR_HARD_REG_SET (reg_used_in_insn);
   {
     HARD_REG_SET tmp;
@@ -6037,6 +6045,29 @@ deallocate_reload_reg (r)
   reload_spill_index[r] = -1;
 }
 
+
+/* Returns true if merging reloads i and j should result in a
+   RELOAD_FOR_OTHER_ADDRESS reload, else false for RELOAD_OTHER.  */
+static int
+merge_becomes_other_address (int i, int j)
+{
+  int wn1 = rld[i].when_needed;
+  int wn2 = rld[j].when_needed;
+
+  if (wn2 == RELOAD_FOR_OTHER_ADDRESS)
+    wn2 = wn1;
+  else if (wn1 != RELOAD_FOR_OTHER_ADDRESS)
+    return 0;
+
+  return (wn2 == RELOAD_FOR_INPUT_ADDRESS
+	  || wn2 == RELOAD_FOR_INPADDR_ADDRESS
+	  || wn2 == RELOAD_FOR_OUTPUT_ADDRESS
+	  || wn2 == RELOAD_FOR_OUTADDR_ADDRESS
+	  || wn2 == RELOAD_FOR_OPERAND_ADDRESS
+	  || wn2 == RELOAD_FOR_OPADDR_ADDR
+	  || wn2 == RELOAD_FOR_OTHER_ADDRESS);
+}
+
 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
    reloads of the same item for fear that we might not have enough reload
    registers. However, normally they will get the same reload register
@@ -6050,6 +6081,7 @@ deallocate_reload_reg (r)
    This will not increase the number of spill registers needed and will
    prevent redundant code.  */
 
+extern const char *const reload_when_needed_name[];
 static void
 merge_assigned_reloads (insn)
      rtx insn;
@@ -6114,6 +6146,7 @@ merge_assigned_reloads (insn)
       if (j == n_reloads
 	  && max_input_address_opnum <= min_conflicting_input_opnum)
 	{
+          int changed = 0;
 	  for (j = 0; j < n_reloads; j++)
 	    if (i != j && rld[j].reg_rtx != 0
 		&& rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
@@ -6121,12 +6154,22 @@ merge_assigned_reloads (insn)
 		    || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
 		    || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
 	      {
-		rld[i].when_needed = RELOAD_OTHER;
+ 		if (merge_becomes_other_address (i, j))
+ 		  rld[i].when_needed = RELOAD_FOR_OTHER_ADDRESS;
+ 		else
+ 		  rld[i].when_needed = RELOAD_OTHER;
 		rld[j].in = 0;
 		reload_spill_index[j] = -1;
 		transfer_replacements (i, j);
+                changed = 1;
 	      }
 
+ 	  /* If this is now RELOAD_OTHER or RELOAD_FOR_OTHER_ADDRESS,
+ 	     look for any reloads that load parts of this operand and
+ 	     set them to RELOAD_FOR_OTHER_ADDRESS if they were for
+ 	     inputs, RELOAD_OTHER for outputs.  Note that this test is
+ 	     equivalent to looking for reloads for this operand
+  	     number.  */
 	  /* If this is now RELOAD_OTHER, look for any reloads that load
 	     parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
 	     if they were for inputs, RELOAD_OTHER for outputs.  Note that
@@ -6137,7 +6180,9 @@ merge_assigned_reloads (insn)
 	     same value or a part of it; we must not change its type if there
 	     is a conflicting input.  */
 
-	  if (rld[i].when_needed == RELOAD_OTHER)
+ 	  if (changed
+              && (rld[i].when_needed == RELOAD_OTHER
+ 	          || rld[i].when_needed == RELOAD_FOR_OTHER_ADDRESS))
 	    for (j = 0; j < n_reloads; j++)
 	      if (rld[j].in != 0
 		  && rld[j].when_needed != RELOAD_OTHER
@@ -6152,7 +6197,8 @@ merge_assigned_reloads (insn)
 
 		  rld[j].when_needed
 		    = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
-			|| rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
+			|| rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS
+                        || rld[j].when_needed == RELOAD_FOR_OPADDR_ADDR)
 		       ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
 
 		  /* Check to see if we accidentally converted two reloads
@@ -6164,8 +6210,13 @@ merge_assigned_reloads (insn)
 		      if (rld[k].in != 0 && rld[k].reg_rtx != 0
 			  && rld[k].when_needed == rld[j].when_needed
 			  && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
-			  && ! rtx_equal_p (rld[k].in, rld[j].in))
+			  && ! rtx_equal_p (rld[k].in, rld[j].in)) {
+                        printf("Changed reload %d, conflict %d with %d\n",
+                               i, k, j);
+                        
 			abort ();
+                      }
+                  
 		}
 	}
     }
@@ -7306,6 +7357,13 @@ emit_reload_insns (chain)
 					      rld[r].when_needed))
 		  CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
 	    }
+          else
+            {
+              /* When the reload does not reach the end, we must
+                 invalidate the old info.  */
+              for (k = 0; k < nr; k++)
+                CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
+            }
 	}
 
       /* The following if-statement was #if 0'd in 1.34 (or before...).
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/ChangeLog.M68HC11 gcc-3.3.6-m68hc1x/gcc/testsuite/ChangeLog.M68HC11
--- gcc-3.3.6/gcc/testsuite/ChangeLog.M68HC11	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/ChangeLog.M68HC11	Fri Jan 20 22:24:30 2006
@@ -0,0 +1,111 @@
+2006-01-20  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* gcc.c-torture/execute-scz/pr-15493.c (struct): New test for
+	savannah/15493
+
+2005-11-05  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* gcc.c-torture/execute-scz/pr-13917.c: New test for savannah/13917.
+	* gcc.c-torture/execute-scz/b-20051105.c: New test.
+
+2005-05-08  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* gcc.c-torture/compile-scz/pr-12572.c: Test case for savannah/12572.
+
+2005-04-03  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* gcc.c-torture/execute-scz/pr-12297.c: Test case for savannah/12297.
+	* gcc.c-torture/execute-scz/pr-12243.c: New test for savannah/12243.
+	* gcc.c-torture/compile-scz/b-2005-02-14.c: New test.
+
+2005-02-13  Stephane Carrez  <stcarrez@nerim.fr>
+
+	PR target/16925
+	* gcc.c-torture/compile-scz/pr-16925.c: New test.
+
+	PR target/14629
+	* gcc.c-torture/compile-scz/pr-14629.cc: New test.
+
+2005-02-12  Stephane Carrez  <stcarrez@nerim.fr>
+
+	PR savannah/11903
+	* gcc.c-torture/compile-scz/pr-11903.c: New test.
+
+2005-01-30  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* gcc.c-torture/execute-scz/pr-11741.c (strncpy): New test
+	for savannah/11741 
+
+2004-08-29  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* gcc.c-torture/execute-scz/b-20040816.c: New file for
+	bug savannah/10207.
+
+2003-10-01  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* gcc.dg/20020219-1.c: Compile with -mshort to make sure integers
+	are 16-bit (test disabled as it defines a huge array).
+	* gcc.dg/20020426-2.c: Likewise.
+	* gcc.dg/20020430-1.c: Likewise.
+	* gcc.dg/20021018-1.c: Likewise.
+	* gcc.dg/20021029-1.c: Likewise.
+	* gcc.dg/20021023-1.c: -fpic is not supported on m6811/m6812.
+
+2003-09-30  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* gcc.c-torture/compile/simd-5.x: Don't execute for 68HC11 because
+	it fails with 16-bit int.
+
+2003-08-02  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* gcc.c-torture/execute-scz/execute.exp: New testsuite for 68hc11/hc12.
+	andqi.c, b-20020520.c, bitfield.c, malloc.c, negqi.c,
+	autoinc.c, bigmul.c, bset.c, memset-2003-01-25.c, orqi.c,
+	b-20010414.c, bit.c, mul-1.c, setjmp-test.c: New test for compilation
+	and execution.
+
+	* gcc.c-torture/compile-scz/compile.exp: New testsuite for 68hc11/hc12.
+	add_opt.c, b-20010920.c, b-20030518.c, di.c, orext.c, push.c,
+	string.c, addshift.c, b-20011203.c, b-20030519.c, foo.c, pr-1416.c,
+	ret64.c, tst-asm.c, alloca.c, b-20020203.c, b-2003-07-04.c,
+	fprintf.c, pr-6698.c, rotate.c, vsprintf.c, ashr.c, b-20020206.c,
+	b-2003-07-30.c, gcc-bug.c, pr-6744.c, sex.c, b-20000411.c,
+	b-20020403.c, bclr.c, interrupt.c, pr-7223.c, sext.c,
+	b-20001206.c, b-20020610.c, lshr.c, pr-7361.c,
+	shift-1.c, b-20010424.c, b-20021015.c, cp.c, min.c, printf.c
+	shl.c: New tests for compilation only.
+
+2003-07-20  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* gcc.c-torture/execute/ieee/920810-1.x: New file, don't execute on
+	68HC11/HC12 because sprintf does not support floats.
+
+2003-07-20  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* gcc.c-torture/execute/shiftdi.x: New file, don't execute this
+	test on 68HC11/HC12 as it relies on 32-bit ints.
+	* gcc.c-torture/execute/20021024-1.x: New file, likewise.
+
+2003-05-18  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* gcc.c-torture/execute/20020404-1.x: New file, don't run this
+	test on 68HC11/68HC12.
+
+2003-05-18  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* gcc.dg/20001009-1.c: -fpic is not supported on m6811-* and m6812-*
+	* gcc.dg/inline-2.c: Likewise.
+	* gcc.dg/20030225-1.c: Likewise.
+	* gcc.dg/20010912-1.c: Likewise.
+	* gcc.dg/20020122-4.c: Likewise.
+	* gcc.dg/20020415-1.c: Likewise.
+	* gcc.dg/20021116-1.c: Likewise.
+	* gcc.dg/20030213-1.c: Likewise.
+	* gcc.dg/20030120-1.c: Likewise.
+	* gcc.misc-tests/bprob.exp: Don't run on m6811-* and m6812-* since
+	the __bb_init_func are not available.
+
+2003-05-18  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* testsuite/gcc.c-torture/compile/20010327-1.x: New file, don't
+	run this test on m6811/m6812 as it assumes pointers are 32-bits.
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/g++.dg/bprob/bprob.exp gcc-3.3.6-m68hc1x/gcc/testsuite/g++.dg/bprob/bprob.exp
--- gcc-3.3.6/gcc/testsuite/g++.dg/bprob/bprob.exp	Mon Oct 21 22:20:58 2002
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/g++.dg/bprob/bprob.exp	Sat Nov  5 19:17:25 2005
@@ -1,4 +1,4 @@
-#   Copyright (C) 2001, 2002 Free Software Foundation, Inc.
+#   Copyright (C) 2001, 2002, 2003 Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -20,7 +20,9 @@
 # Some targets don't have any implementation of __bb_init_func or are
 # missing other needed machinery.
 if { [istarget mmix-*-*]
-     || [istarget cris-*-*] } {
+     || [istarget cris-*-*]
+     || [istarget m6811-*-*]
+     || [istarget m6812-*-*] } {
     return
 }
 
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile/20010327-1.x gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile/20010327-1.x
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile/20010327-1.x	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile/20010327-1.x	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,8 @@
+# This test does not compile on m68hc11 because it
+# assumes pointers are 32-bits
+
+if { [istarget "m6811-*-*"] || [istarget "m6812-*-*"] } {
+      return 1
+}
+
+return 0
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile/920521-1.x gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile/920521-1.x
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile/920521-1.x	Thu Jun 29 05:10:00 2000
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile/920521-1.x	Sat Nov  5 19:17:25 2005
@@ -1,2 +1,7 @@
+# Test defines an asm which sometimes requires too many
+# registers for HC11/HC12.
+if { [istarget "m6811-*-*"] || [istarget "m6812-*-*"] } {
+      return 1
+}
 set options "-S"
 return 0
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile/simd-5.x gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile/simd-5.x
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile/simd-5.x	Sat May 24 13:55:35 2003
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile/simd-5.x	Sat Nov  5 19:17:25 2005
@@ -3,6 +3,11 @@ if { [istarget "h8300-*-*"] } {
     return 1;
 }
 
+# On 68HC11 is fails with 16-bit ints
+if { [istarget "m6811-*-*"] || [istarget "m6812-*-*"] } {
+    return 1;
+}
+
 if { [istarget "sparc64-*-*"] || [istarget "sparcv9-*-*"] } {
     # On SPARC64/SPARC-V9 it fails, except with -m32.
     set torture_eval_before_compile {
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/add_opt.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/add_opt.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/add_opt.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/add_opt.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,17 @@
+unsigned long addsi_and16(unsigned long a, unsigned long b)
+{
+  return a + (b & 0x0ffff);
+}
+
+unsigned long addsi_zext(unsigned long* a, unsigned long* b)
+{
+  *a = *a + (*b & 0x0ffff);
+  return *a;
+}
+
+unsigned long addsi_shift(unsigned long* a, unsigned long* b)
+{
+  *a = *a + (*b << 16);
+  return *a;
+}
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/addshift.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/addshift.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/addshift.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/addshift.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,6 @@
+unsigned long addsi_shift(unsigned long* a, unsigned long* b)
+{
+  *a = (*b << 16) + *a;
+  return *a;
+}
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/alloca.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/alloca.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/alloca.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/alloca.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,7 @@
+extern __attribute__((noreturn)) void bar(char*, int);
+
+void get(int size, char c)
+{
+  char *buf[size];
+  bar (buf, size);
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/ashr.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/ashr.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/ashr.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/ashr.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,5 @@
+long ashr(long a, short b)
+{
+  a = a >> b;
+  return a;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20000411.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20000411.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20000411.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20000411.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,51 @@
+#include <string.h>
+
+typedef unsigned char byte;
+
+// Data structure for queues.
+typedef struct {
+  byte start;
+  byte end;
+  byte count;
+  byte* data;
+  byte length;
+} queueType;
+
+// Add a value to the end of a queue.
+void Enqueue (queueType* queue, void *value, byte size)
+{
+  // Working variables.
+  byte counter;
+  //  byte increment = 1;
+
+  // Save each byte of the given value at start.
+  for (counter = 0; counter < size; counter++) {
+    // Save byte of value.
+    *(queue->data + queue->start) = *(byte*)(value++);
+
+    // Increment start pointer (with wrap around).
+    queue->start = (queue->start + 1) % queue->length;
+
+    // Push the end forward as necessary (with wrap around). 
+    //if (queue->start == queue->end) {
+    //queue->end = (queue->end + 1) % queue->length;
+    //  increment = 0;
+    //}
+  }
+
+  // Increment element count if there was no shifting of the end pointer.
+  //  if (increment) queue->count++;
+}
+
+
+int main()
+{
+  byte input = 0x10;
+
+  static queueType queue;
+  static byte buffer[5];
+  queue.start = queue.end = queue.count = 0;
+  queue.data = buffer;
+  queue.length = 5;
+  Enqueue(&queue,&input,sizeof(input));
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20001206.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20001206.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20001206.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20001206.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1 @@
+char *a[] = {"abcd", "defg"};
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20010424.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20010424.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20010424.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20010424.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,46 @@
+typedef char byte;
+extern int strlen(char*);
+extern void LcdWriteChar(byte,byte,byte,byte);
+extern void os_disable();
+enum align {
+  LCD_ALIGN_LEFT,
+  LCD_ALIGN_CENTER,
+  LCD_ALIGN_RIGHT
+};
+
+void LcdWriteString(
+    byte page_no, byte x, byte y, char *str, byte align
+) {
+
+char *ptr;
+
+ os_disable ();
+    switch( align ) {
+    case LCD_ALIGN_LEFT:
+        break;
+    case LCD_ALIGN_CENTER:
+        x -= strlen( str ) >> 1; break;
+    case LCD_ALIGN_RIGHT:
+        x -= strlen( str ); break;
+    }
+    for( ptr = str; *ptr != 0; ptr++ ) {
+        LcdWriteChar( page_no, x, y, *ptr );
+        x++;
+    }
+}
+
+void
+os_disable()
+{
+  ;
+}
+int main()
+{
+  LcdWriteString(1,2,3,"Hello",LCD_ALIGN_CENTER);
+  return 0;
+}
+void
+LcdWriteChar(byte p, byte x, byte y, byte c)
+{
+  ;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20010920.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20010920.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20010920.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20010920.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,14 @@
+unsigned int segwerte[9];
+void me_Measure_seg();
+void ser_putword( unsigned int data );
+
+void command_messen(void)
+{
+ // volatile int i;
+ int i;
+ me_Measure_seg();
+ for(i=0;i<9;i++)
+  {
+   ser_putword(segwerte[i]);
+  }
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20011203.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20011203.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20011203.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20011203.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,5 @@
+char IsWChanged(char c) {
+  char c1 = c * 10 + 60;
+  return c1;
+}
+ 
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20020203.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20020203.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20020203.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20020203.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,4 @@
+unsigned long add_shift(unsigned long a, unsigned long b)
+{
+  return ((a >> 16) + b);
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20020206.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20020206.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20020206.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20020206.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,13 @@
+volatile char _io_ports[10];
+char bar;
+
+int get ()
+{
+  while (_io_ports[3] & 0x80)
+    continue;
+
+  if (bar & 0x80)
+    return _io_ports[1];
+  
+  return _io_ports[2];
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20020403.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20020403.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20020403.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20020403.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,6 @@
+void foo(char* addr, char* data)
+{
+    *((volatile char*)0x0) |= 0x1;
+    *addr++ = *data++;
+    *((volatile char*)0x0) |= 0x1;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20020610.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20020610.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20020610.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20020610.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,8 @@
+int check(char *p)
+{
+  *p = 'a';
+  if (*p == 'a')
+    return *p;
+
+  return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20021015.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20021015.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20021015.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20021015.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,22 @@
+int main (void);
+void Call1 (void);
+unsigned char Var1         __attribute__ ((section (".page0")));
+ 
+void _start (void)
+{
+ main();
+}
+ 
+int main (void)
+{
+ if (!Var1)
+ {
+  Call1();
+ }
+ Var1 |= 1;
+return (0);
+}
+ 
+void Call1 (void)
+{
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-2003-07-04.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-2003-07-04.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-2003-07-04.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-2003-07-04.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,12 @@
+typedef unsigned long __u32;
+typedef unsigned short __u16;
+__u16 tcp_chksum;
+void a(void)
+{
+   
+     __u32 checksum;
+     checksum += checksum >> 16;
+     tcp_chksum = ~checksum;
+}
+
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-2003-07-30.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-2003-07-30.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-2003-07-30.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-2003-07-30.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,15 @@
+struct a 
+{
+  int a;
+  int b;
+  char bar[253];
+  long d;
+  int c[3];
+};
+
+struct a table[10];
+
+int get(int p)
+{
+  return table[p].c[2];
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20030518.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20030518.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20030518.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20030518.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,16 @@
+extern volatile unsigned char _io_ports[];
+
+int main(void)
+{
+    unsigned short x;
+    int i = 0;
+
+    x = (_io_ports[0x00] << 8) | _io_ports[0x00];
+
+    if (x >> i)
+    {
+        _io_ports[0x00] = 0;
+    }
+
+    return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20030519.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20030519.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-20030519.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-20030519.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,19 @@
+/*
+ *  compile with:
+ * m6811-elf-gcc -mshort -O -fomit-frame-pointer -S test.c
+ *          
+ * Then notice that the generated code references the frame pointer,
+ * even though we have told the compiler not to use it. The code is
+ * correct if optimization is disabled.
+ * */
+            
+void __attribute__((interrupt)) do_something(char *p1, char *p2);
+            
+void __attribute__((interrupt)) something(char *p1)
+{
+   char p2;
+   char* p2p = &p2;
+   do_something(p1, p2p);
+}
+
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-2005-02-14.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-2005-02-14.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/b-2005-02-14.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/b-2005-02-14.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,16 @@
+unsigned int x;
+int main(void);
+int main()
+{
+   
+      while(1)
+     {
+	
+	      for (x=1; x<=60000;x++); // Delay loop
+	      for (x=1; x<=60000;x++); // Delay loop
+     }
+   
+      return 0;
+}
+
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/bclr.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/bclr.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/bclr.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/bclr.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,13 @@
+#define bclr(m, o, b) \
+    __asm __volatile("bclr %i1,%0 %2" : : "x" (m), "n" (o), "n" (b))
+ 
+extern volatile unsigned char _io_ports[];
+extern unsigned short toto;
+
+void set(char* p)
+{
+  bclr(_io_ports, 0x30, 0x20);
+  _io_ports[0x30] |= 0x20;
+  p[2] |= 1;
+  toto |= 4;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/compile.exp gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/compile.exp
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/compile.exp	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/compile.exp	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,35 @@
+# Expect driver script for GCC Regression Tests
+# Copyright (C) 1993, 1995, 1997 Free Software Foundation
+#
+# This file is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 
+
+# These tests come from Torbjorn Granlund's (tege@cygnus.com)
+# C torture test suite, and other contributors.
+
+if $tracelevel then {
+    strace $tracelevel
+}
+
+# load support procs
+load_lib c-torture.exp
+
+foreach testcase [glob -nocomplain $srcdir/$subdir/*.c] {
+    # If we're only testing specific files and this isn't one of them, skip it.
+    if ![runtest_file_p $runtests $testcase] then {
+	continue
+    }
+
+    c-torture $testcase
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/cp.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/cp.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/cp.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/cp.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,6 @@
+#include <stddef.h>
+
+void copy(short *s, short *q, size_t l)
+{
+  while (--l > 0) *s++ = *q++;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/di.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/di.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/di.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/di.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,5 @@
+long long shl(long long a)
+{
+  return a << 1;
+}
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/foo.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/foo.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/foo.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/foo.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,4 @@
+int __attribute__((section("init")))  main()
+{
+  return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/fprintf.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/fprintf.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/fprintf.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/fprintf.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,28 @@
+/*
+ * Simple replacement of fprintf() for use by GCC testsuite.
+ */
+#include <stdarg.h>
+#include <stddef.h>
+
+typedef struct _file {
+  long a;
+} FILE;
+
+extern int vsprintf(char*, const char*, ...);
+extern int write(int, const char*, size_t);
+
+int
+fprintf(FILE* fp, const char* fmt, ...)
+{
+  char buf[256];
+  va_list args;
+  int i;
+
+  va_start(args, fmt);
+  i=vsprintf(buf,fmt,args);
+  va_end(args);
+
+  write(0, buf, i);
+  return i;
+}
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/gcc-bug.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/gcc-bug.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/gcc-bug.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/gcc-bug.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,87 @@
+/*
+command that triggered the bug:
+$ m68hc12-elf-gcc -O3 -c -I./src -I./sys-inc -fno-builtin  src/hc12_eeprom.c -o obj/hc12_eeprom.o
+src/hc12_eeprom.c: In function `write_eeprom':
+src/hc12_eeprom.c:44: Insn does not satisfy its constraints:
+(insn 32 30 128 (set (mem:QI (const_int 243 [0xf3]) 0)
+        (ior:QI (mem:QI (const_int 243 [0xf3]) 0)
+            (const_int 22 [0x16]))) 83 {*iorqi3_const} (insn_list 25 (nil))
+    (nil))
+src/hc12_eeprom.c:44: Internal compiler error in reload_cse_simplify_operands, at reload1.c:8387
+Please submit a full bug report,
+with preprocessed source if appropriate.
+See <URL:http://www.gnu.org/software/gcc/bugs.html> for instructions.
+make: *** [obj/hc12_eeprom.o] Error 1
+*/
+# 7 "src/hc12_eeprom.c"
+# 1 "src/hc912bc32.h" 1
+# 8 "src/hc12_eeprom.c" 2
+# 1 "src/hc12_util.h" 1
+# 12 "src/hc12_util.h"
+enum true_false { false=0, true};
+# 22 "src/hc12_util.h"
+typedef char bool;
+typedef char boolean;
+typedef unsigned char byte;
+typedef unsigned int uint;
+typedef unsigned long ulong;
+
+typedef const unsigned char* pcbyte;
+typedef const unsigned short* pcword;
+# 40 "src/hc12_util.h"
+void wait_1msec(void);
+void wait_10msec(void);
+void sleep(unsigned long);
+char bitNr(char);
+
+void initMain(void);
+void restartMain(void);
+
+void InitLock(char*);
+bool SetLock(char*);
+void ResetLock(char*);
+void WaitLock(char*);
+
+void BootLoaderDownload(void);
+void BootLoad(void);
+void Reboot(void);
+void Coldstart(void);
+char IsInterrupt(void);
+
+boolean isMenu(void);
+# 9 "src/hc12_eeprom.c" 2
+
+
+
+# 1 "src/hc12_eeprom.h" 1
+# 41 "src/hc12_eeprom.h"
+void write_eeprom(unsigned char*,unsigned char);
+# 13 "src/hc12_eeprom.c" 2
+
+
+
+void write_eeprom
+   (unsigned char* pPointer,
+    unsigned char bByte)
+{
+    if (*pPointer!=bByte)
+    {
+
+        (* (unsigned char *) (0x0000 + 0xF1))=0x00;
+        (* (unsigned char *) (0x0000 + 0xF3))|=0x02|0x04|0x10;
+        *pPointer=bByte;
+        (* (unsigned char *) (0x0000 + 0xF3))|=0x01;
+        wait_10msec();
+        (* (unsigned char *) (0x0000 + 0xF3))&=~(0x01);
+
+
+
+        (* (unsigned char *) (0x0000 + 0xF3))&=~(0x04|0x10);
+        *pPointer=bByte;
+        (* (unsigned char *) (0x0000 + 0xF3))|=0x01;
+        wait_10msec();
+        (* (unsigned char *) (0x0000 + 0xF3))&=~(0x01);
+        (* (unsigned char *) (0x0000 + 0xF3))&=~(0x02);
+        (* (unsigned char *) (0x0000 + 0xF1))=0xFF;
+    }
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/interrupt.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/interrupt.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/interrupt.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/interrupt.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,19 @@
+extern char clock_flags;
+extern char time_secs;
+extern char min_flag;
+
+#define REG_BASE 0
+#define REGISTER char
+#define PORTA           (*(volatile REGISTER *)(REG_BASE + 0x00))
+#define SHUTDOWN  0x40
+#define TIMING  0x01
+void __attribute__((interrupt))
+clock_interrupt_handler()
+{
+        PORTA &= ~SHUTDOWN;     /* power everything up*/
+        clock_flags |= TIMING;
+        if(time_secs != 0)
+                return;
+        min_flag = 1;           /* 1 minute flag for main.c*/
+}
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/lshr.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/lshr.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/lshr.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/lshr.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,8 @@
+unsigned long global;
+
+unsigned long ashr(unsigned long a, short b)
+{
+  a = a >> b;
+  global = a >> 1;
+  return a;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/min.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/min.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/min.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/min.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,39 @@
+unsigned short uminhi(unsigned short a, unsigned short b)
+{
+  a = (a < b) ? a : b;
+  return a;
+}
+
+unsigned short umaxhi(unsigned short a, unsigned short b)
+{
+  a = (a > b) ? a : b;
+  return a;
+}
+
+unsigned char e;
+
+void
+umaxqi(unsigned char a)
+{
+  e = (a > e) ? e : a;
+}
+
+unsigned char
+umaxqi2(unsigned char a)
+{
+  a = (a > e) ? e : a;
+  return a;
+}
+
+void
+uminqi(unsigned char a)
+{
+  e = (a < e) ? e : a;
+}
+
+unsigned char
+uminqi2(unsigned char a)
+{
+  a = (a < e) ? e : a;
+  return a;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/orext.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/orext.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/orext.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/orext.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,16 @@
+unsigned long b;
+unsigned char c;
+unsigned char d;
+
+unsigned short get()
+{
+  return (c << 8) | d;
+}
+
+unsigned long orext(unsigned long a)
+{
+  a = (b >> 16) | a;
+  a = a | c;
+  a = a | (unsigned long) ((d | (c << 8)));
+  return a;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-11813.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-11813.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-11813.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-11813.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,20 @@
+struct Regs
+{
+volatile unsigned char reg;
+};
+
+struct Device
+{
+struct Regs *regs;
+};
+
+struct Device dev0 =
+{
+(struct Regs *) 0x0100,
+};
+
+void init(struct Device *device)
+{
+device->regs->reg |= 0x01;
+device->regs->reg &= ~0x01;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-12572.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-12572.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-12572.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-12572.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,14 @@
+int main()
+{
+   
+   unsigned short x;
+   
+   for (x=1; x<=0x8000; x++) 
+     {
+	
+	asm volatile ("nop");
+     }
+   
+   
+   return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-1416.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-1416.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-1416.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-1416.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,8 @@
+
+#define MIN(x1,x2) (x1 > x2)?x1:x2
+typedef unsigned short WORD;
+
+WORD wT;
+WORD TstMin(void) {
+  return MIN(wT, 99);
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-14629.cc gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-14629.cc
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-14629.cc	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-14629.cc	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,47 @@
+extern void Hex2Ascii(unsigned char,unsigned char*);
+extern void cputch(char);
+class CFrame {
+ protected:
+  unsigned char *m_rxBuf;
+  unsigned int m_frameLen;
+  unsigned char OnRxChar(unsigned char __c);
+ private:
+  unsigned int m_rxCnt;
+  unsigned char m_state;
+};
+
+unsigned char
+CFrame::OnRxChar(unsigned char c)
+{
+  switch (m_state)
+    {
+    case 0:
+      m_rxCnt = 0;
+      m_state = 1;
+      
+    case 1:
+      if (c == 0x5a)
+        {
+          ++m_rxCnt;
+          if (m_rxCnt == 2)
+            m_state = 2;
+        }
+      else
+        {
+          char buf[2];
+          Hex2Ascii(c, (unsigned char*)buf);
+          cputch(buf[0]);
+          cputch(buf[1]);
+          m_rxCnt = 0;
+        }
+      break;
+      
+    case 2:
+      m_rxBuf[m_rxCnt++] = c;
+      if (m_rxCnt == (unsigned int) 7)
+        m_frameLen = *(unsigned short*)(&m_rxBuf[4]);
+      break;
+    }
+  
+  return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-16925.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-16925.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-16925.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-16925.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,9 @@
+/* PR target/16925: ICE on 64-bit host architectures */
+typedef unsigned int UDItype __attribute__ ((mode (DI)));
+
+void ICE_on_64bit_archs (void)
+{
+  UDItype a;
+  a |= 0x8000000000000LL;
+}
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-17551.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-17551.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-17551.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-17551.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,14 @@
+int calc (void)
+  {
+    int  mask_size;
+    int i,j,x;
+
+  for(i=-mask_size; i<=mask_size; i++)
+    for(j=-mask_size; j<=mask_size; j++)
+    {
+      x = (i*i)+(j*j);
+    }
+
+  return x; 
+}
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-6698.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-6698.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-6698.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-6698.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,57 @@
+/*  scanner.c */
+/*  J. Tritthardt, MPIMF/BMO */
+/*  Version 1.0 - 28.02.2002 */
+
+/*  Testprogramm fuer die LEDs der Scanner-Box */
+
+#define COPCTL *(volatile unsigned char *)(0x16)
+
+#define IO_BASE 0
+#define PORTT *((volatile unsigned char *)(IO_BASE + 0xAE))
+#define DDRT *((volatile unsigned char *)(IO_BASE + 0xAF))
+
+#define led_red 0x02
+#define led_red_port PORTT
+#define led_red_ddr DDRT
+#define led_green 0x08
+#define led_green_port PORTT
+#define led_green_ddr DDRT
+
+void delay();
+
+int main() 
+{ 
+  led_red_port = led_red_port | led_red;
+  led_red_ddr = led_red_ddr | led_red;
+  led_green_port = led_green_port | led_green;
+  led_green_ddr = led_green_ddr | led_green;
+
+  while (1) {
+    led_red_port = led_red_port | led_red;
+    led_green_port = led_green_port & ~led_green;
+
+    delay();
+
+    led_green_port = led_green_port | led_green;
+    led_red_port = led_red_port & ~led_red;
+
+    delay();
+  }
+
+  return 0;
+} 
+ 
+void __premain() 
+{
+    __asm__ __volatile__ ("clr 0x16");
+} 
+
+void delay()
+{
+#ifdef mc6812
+  __asm__ __volatile__ ("PSHD\n\tLDD	0xFFFF\n\tDBNE	D,-3\n\tPULD\n\tRTS");
+#endif
+#ifdef mc6811
+  __asm__ __volatile__ ("PSHA\n\tLDD	0xFFFF\n\tPULA\n\tRTS");
+#endif
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-6744.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-6744.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-6744.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-6744.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,1671 @@
+# 1 "eeprom.c"
+#define ASM 0 
+
+
+
+
+
+
+
+# 1 "eeprom.h" 1
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# 1 "/usr/lib/gcc-lib/m6811-elf/2.95.3/include/stdbool.h" 1 3
+ 
+
+
+
+ 
+
+typedef enum
+  {
+    false = 0,
+    true = 1
+  } bool;
+
+ 
+
+
+
+ 
+
+
+
+# 16 "eeprom.h" 2
+
+# 1 "../../include/sys/hwreg.h" 1
+ 
+
+
+
+
+
+
+
+
+# 1 "../../include/asm-m68hc12/hwreg.h" 1
+ 
+
+
+
+
+
+
+
+
+
+
+
+# 1 "../../include/asm-m68hc12/param.h" 1
+ 
+
+
+
+
+
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+ 
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+ 
+
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+
+
+
+
+
+# 13 "../../include/asm-m68hc12/hwreg.h" 2
+
+# 1 "../../include/asm-m68hc12/hwregaddr.h" 1
+ 
+
+
+
+
+
+
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+ 
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+  
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+                                    
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+
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+              
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+
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+              
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+              
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+              
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+ 
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+
+
+
+
+
+
+
+
+
+
+# 14 "../../include/asm-m68hc12/hwreg.h" 2
+
+
+typedef unsigned char byte;
+typedef unsigned short word;
+
+ 
+extern volatile byte _io_ports[];
+extern volatile byte *io_ports;
+
+
+
+
+
+
+ 
+
+
+
+ 
+
+
+
+
+
+ 
+
+
+ 
+
+
+static inline void
+relocate_reg(word base)
+{
+  _io_ports[0x11 ] = (base/0x100) & 0xF8;
+  io_ports = (byte*) base;
+}
+
+ 
+
+
+static inline void
+set_bus_expanded(void)
+{
+  *((volatile word*) &_io_ports[( 0x0A  )])  = (word)((byte)(1<<7) | (1<<2) )*0x100 + ((1<<5) | (1<<4) ) ;
+  _io_ports[( 0x13  )]  = 0x7F;        
+}
+
+
+ 
+
+
+static inline void
+set_bus_expanded_wide(void)
+{
+  *((volatile word*) &_io_ports[( 0x0A  )])  = (word)((byte)(1<<7) | (1<<2) )*0x100 + ((1<<6) | (1<<5) | (1<<4) ) ;
+  _io_ports[( 0x13  )]  = 0x7F;
+}
+
+ 
+static inline void
+set_bus_single_chip(void)
+{
+  _io_ports[( 0x0B  )]  = (byte)(1<<7) | (1<<4) ;
+}
+
+ 
+
+
+static inline void
+rti_init(byte scale)
+{
+  _io_ports[( 0x14  )]  = (1<<5)  | (scale & (0x7) );
+}
+
+ 
+static inline byte
+rti_getFlg(void)
+{
+  return _io_ports[( 0x15  )] ;
+}
+
+ 
+static inline void
+rti_clearFlg(void)
+{
+  _io_ports[( 0x15  )]  = 0x80 ;
+}
+
+ 
+static inline void
+cop_disable(void)
+{
+#if ASM
+  asm("bclr %0,%1" : : "R"( _io_ports[( 0x16  )]  ), "i"(  (0x7)  )) ;        
+#endif
+}
+
+ 
+static inline void
+cop_force_reset(void)
+{
+  _io_ports[( 0x17  )]  = 0x55;
+  _io_ports[( 0x17  )]  = 0xAA;
+}
+
+ 
+
+static inline void
+cop_reset(void)
+{
+
+  cop_force_reset();
+
+}
+
+ 
+static inline void
+cop_init(void)
+{
+  cop_force_reset();
+  _io_ports[( 0x16  )]  = (1<<3)  | 2 ;
+}
+
+
+
+
+
+
+# 10 "../../include/sys/hwreg.h" 2
+
+
+
+
+
+
+
+# 17 "eeprom.h" 2
+
+
+# 1 "/usr/lib/gcc-lib/m6811-elf/2.95.3/include/stddef.h" 1 3
+
+
+
+
+
+
+ 
+
+
+# 19 "/usr/lib/gcc-lib/m6811-elf/2.95.3/include/stddef.h" 3
+
+
+
+ 
+
+
+ 
+
+
+
+
+
+ 
+
+
+# 61 "/usr/lib/gcc-lib/m6811-elf/2.95.3/include/stddef.h" 3
+
+
+ 
+
+
+
+
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 
+
+
+
+
+
+ 
+
+ 
+
+# 131 "/usr/lib/gcc-lib/m6811-elf/2.95.3/include/stddef.h" 3
+
+
+ 
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+typedef short unsigned int size_t;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 
+
+
+
+
+ 
+
+# 271 "/usr/lib/gcc-lib/m6811-elf/2.95.3/include/stddef.h" 3
+
+
+# 283 "/usr/lib/gcc-lib/m6811-elf/2.95.3/include/stddef.h" 3
+
+
+ 
+
+ 
+
+# 317 "/usr/lib/gcc-lib/m6811-elf/2.95.3/include/stddef.h" 3
+
+
+
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# 19 "eeprom.h" 2
+
+
+
+
+ 
+bool eeprom_isWriting (void);
+
+ 
+
+int eeprom_prepareRead (word offset);
+
+ 
+
+
+int eeprom_readByte (word offset);
+
+ 
+
+
+word eeprom_readWord (word offset);
+
+ 
+void eeprom_chkWrite (void);
+
+ 
+
+int eeprom_writeByte (word offset, byte data);
+
+ 
+
+
+int eeprom_writeWord (word offset, word data);
+
+
+
+
+
+
+# 9 "eeprom.c" 2
+
+# 1 "../../include/timer.h" 1
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+# 1 "../../include/sys/timer.h" 1
+ 
+
+
+
+
+
+
+
+
+
+# 1 "../../include/asm-m68hc12/timer.h" 1
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+   
+
+  static inline void
+  timer_init(void)
+  {
+    _io_ports[( 0x8D  )]  = (byte)(1<<5)  | 3 ;
+     
+    _io_ports[( 0x86  )]   = (byte)(1<<7)  | (byte)(1<<5)  | (byte)(1<<4) ;
+  }
+
+   
+
+  static inline short
+  get_hwtime(void)
+  {
+    return *((volatile word*) &_io_ports[( 0x84  )]) ;
+  }
+
+   
+
+  static inline byte
+  get_tof_flg(void)
+  {
+    return (_io_ports[( 0x8F  )]  & (byte)(1<<7) );
+  }
+
+   
+  static inline void
+  tc_set_outputcompare(byte n)
+  {
+    _io_ports[( 0x80  )]  |= 1<<n;
+  }
+
+   
+  static inline void
+  tc_set_inputcapture(byte n)
+  {
+    _io_ports[( 0x80  )]  &= (byte)~(1<<n);
+  }
+
+   
+  static inline void
+  tc_interrupt_enable(byte n)
+  {
+    _io_ports[( 0x8C  )]  |= (byte)(1<<n);
+  }
+
+   
+  static inline void
+  tc_interrupt_disable(byte n)
+  {
+    _io_ports[( 0x8C  )]  &= (byte)~(1<<n);
+  }
+
+   
+
+  static inline byte
+  tc_get_flg(byte n)
+  {
+    return (_io_ports[( 0x8E  )]  & (byte)(1<<n));
+  }
+
+   
+
+  static inline word
+  tc_get_value(byte n)
+  {
+    return ((volatile word*) &_io_ports[( 0x90  )]) [n];
+  }
+
+   
+
+  static inline void
+  tc_set_value(byte n, word val)
+  {
+    ((volatile word*) &_io_ports[( 0x90  )]) [n] = val;
+  }
+
+   
+
+
+  static inline void
+  tc_add_microseconds(byte n, unsigned long t)
+  {
+    tc_set_value(n, tc_get_value(n) + (word)((8000000   / (1<< 3 ))   * t/1000000));
+  }
+
+   
+
+
+  static inline void
+  tc_set_tocmode(byte n, byte mode)
+  {
+    word d = *((volatile word*) &_io_ports[( 0x88  )]) ;
+    n *= 2;                        
+    d &= ~(0x3 << n);              
+    d |= mode << n;                
+
+    *((volatile word*) &_io_ports[( 0x88  )])  = d;
+  }
+
+   
+
+
+  static inline void
+  tc_toggle_tocmode(byte n)
+  {
+    *((volatile word*) &_io_ports[( 0x88  )])  ^= (word)(1<<(n*2));
+  }
+
+   
+
+
+  static inline void
+  tc_set_ticmode(byte n, byte mode)
+  {
+    word d = *((volatile word*) &_io_ports[( 0x8A  )]) ;
+    n *= 2;                         
+    d &= ~(0x3 << n);
+    d |= mode << n;
+
+    *((volatile word*) &_io_ports[( 0x8A  )])  = d;
+  }
+
+
+
+
+
+
+# 11 "../../include/sys/timer.h" 2
+
+
+
+
+
+
+# 14 "../../include/timer.h" 2
+
+# 1 "../../include/sys/locks.h" 1
+ 
+
+
+
+
+
+
+
+
+
+# 1 "../../include/asm-m68hc12/locks.h" 1
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 
+
+ 
+
+static inline short
+lock(void)
+{
+  short ccsav;
+  asm volatile ("tpa\nsei": "=d"(ccsav):: "cc");
+  return ccsav;
+}
+
+ 
+
+static inline void
+unlock(void)
+{
+  asm volatile ("cli"::: "cc");
+}
+
+ 
+
+static inline void
+restorelock(short ccsav)
+{
+  asm volatile ("tap":: "d"(ccsav): "cc");
+}
+
+
+
+
+
+
+# 11 "../../include/sys/locks.h" 2
+
+
+
+
+
+
+# 15 "../../include/timer.h" 2
+
+
+   
+
+
+
+
+
+
+   
+
+
+
+
+
+
+  extern volatile unsigned TofCnt;          
+  extern volatile unsigned MillisecCnt;
+  extern volatile byte TimerFlgs;
+
+   
+
+  extern void timer_init_tof (void);
+
+   
+
+  extern signed char reserveTimerNum (byte n);
+
+   
+
+  extern signed char reserveTimerNumOnly (byte n);
+  extern void freeTimerNum (byte n);
+  extern void timer_init_msec (byte tnum);
+  extern void doTimeMsec (void);
+  extern unsigned long get_time (void);
+
+  extern void intTof (void) __attribute__((__interrupt__));
+  extern void intTimeMsec (void) __attribute__((__interrupt__));
+
+   
+
+  static inline void
+  doTof (void)
+  {
+    get_hwtime();   
+    TofCnt++;
+#if ASM
+    asm("bset %0,%1"::"a"( TimerFlgs ), "i"(  (byte)(1<<7)  )) ;
+#endif
+  }
+
+   
+  static inline byte
+  isTickMsecFlg (void)
+  {
+    return TimerFlgs & (1<<6) ;
+  }
+
+   
+  static inline void
+  clearTickMsecFlg (void)
+  {
+#if ASM
+    asm("bclr %0,%1"::"R"( TimerFlgs ), "i"(  (1<<6)  )) ;
+#endif
+  }
+
+
+
+
+
+
+# 10 "eeprom.c" 2
+
+
+
+
+extern volatile byte _eeprom_base[0x300 ];
+static word   dataOffset;           
+static byte   dataBuf[2];           
+static byte   dataSize;             
+static byte   writeTries = 2 ;     
+static signed char eepTimerNum = -1;
+
+
+
+
+
+ 
+
+bool
+eeprom_isWriteMode (void)
+{
+  return _io_ports[( 0xF3  )]  & (1<<1) ;
+}
+
+ 
+
+static inline void
+eeprom_mapOn (void)
+{
+#if ASM
+  asm("bset %0,%1"::"R"( _io_ports[( 0x12  )]  ), "i"(  (1<<0)  )) ;
+#endif
+}
+
+ 
+static inline void
+eeprom_mapOff (void)
+{
+#if ASM
+  asm("bclr %0,%1"::"R"( _io_ports[( 0x12  )]  ), "i"(  (1<<0)  )) ;
+#endif
+}
+
+ 
+
+int
+eeprom_prepareRead (word offset)
+{
+  if(offset >= 0x300 )    return -2;    
+  if(eeprom_isWriteMode())   return -1;    
+  eeprom_mapOn();                        
+  return 0;
+}
+
+ 
+
+
+int
+eeprom_readByte (word offset)
+{
+  int rtn;
+
+  rtn = eeprom_prepareRead(offset);
+  if(rtn < 0) return rtn;
+
+  return _eeprom_base[( offset )] ;         
+}
+
+ 
+
+
+word
+eeprom_readWord (word offset)
+{
+  if(eeprom_prepareRead(offset) < 0) return 0xFFFF;
+  return *((volatile word*) &_eeprom_base[( offset )]) ;         
+}
+
+ 
+void
+eeprom_chkWrite (void)
+{
+  if(eepTimerNum < 0) return;        
+
+   
+  if((_io_ports[( 0xF3  )]  & (1<<0) ) )
+  {
+     
+    if(tc_get_flg(eepTimerNum))
+    {
+       
+#if ASM
+      asm("bclr %0,%1" : : "R"(_io_ports[( 0xF3  )]  ), "i"(  (1<<0)  )) ;
+      asm("bclr %0,%1" : : "R"( _io_ports[( 0xF3  )]  ), "i"(  (1<<1)  )) ;    
+#endif
+    }
+  }
+
+   
+  if(! (_io_ports[( 0xF3  )]  & (1<<0) ) )
+  {
+     
+    if(dataSize)
+    {
+      byte dataOddBoundary = dataSize & 1;      
+      byte dataIdx;
+      word currOffset, r, w;
+
+       
+      dataIdx = dataSize - 1;
+#if ASM
+      asm("bclr %0,%1"::"R"( dataIdx ), "i"(  1 )) ;                    
+#endif
+      currOffset = dataOffset + dataIdx;
+
+      if(dataOddBoundary) {
+         
+        r = eeprom_readByte(currOffset);
+        w = dataBuf[dataIdx];
+      }
+      else {
+         
+        r = eeprom_readWord(currOffset);
+        w = *((word*)&dataBuf[dataIdx]);
+      }
+
+       
+      if((w ^ r) & w)
+      {
+         
+#if ASM
+        asm("bset %0,%1"::"R"( _io_ports[( 0xF3  )]  ), "i"(  (1<<4) | (1<<2) | (1<<1)  )) ;
+#endif
+        if(dataOddBoundary)
+        {
+          _eeprom_base[( currOffset )]  = w;      
+        }
+        else
+        {
+          *((volatile word*) &_eeprom_base[( currOffset )])  = w;      
+        }
+
+         
+        tc_set_value(eepTimerNum, get_hwtime()+(word)((8000000   / (1<< 3 ))  *.010));
+#if ASM
+        asm("bset %0,%1"::"R"( _io_ports[( 0xF3  )]  ), "i"(  (1<<0)  )) ;       
+#endif
+      }
+      else if(r != w && writeTries)    
+      {
+         
+        _io_ports[( 0xF3  )]  = (_io_ports[( 0xF3  )]  & ~(1<<2) ) | (1<<1) ;
+
+        if(dataOddBoundary) {
+          _eeprom_base[( currOffset )]  = w;      
+        }
+        else {
+          *((volatile word*) &_eeprom_base[( currOffset )])  = w;      
+        }
+
+        writeTries--;                        
+
+         
+        tc_set_value(eepTimerNum, get_hwtime()+(word)((8000000   / (1<< 3 ))  *.010));
+#if ASM
+        asm("bset %0,%1"::"R"( _io_ports[( 0xF3  )]  ), "i"(  (1<<0)  )) ;       
+#endif
+      }
+      else    
+      {
+        dataSize = dataIdx;                 
+        writeTries = 2 ;        
+
+        if(!dataSize)
+        {
+           
+          freeTimerNum(eepTimerNum);
+          eepTimerNum = -1;
+        }
+      }
+    }
+  }
+}
+
+ 
+
+
+
+
+static int
+eeprom_writeData (word offset, void *data, size_t sz)
+{
+  if(dataSize) return -1;                       
+  if(offset + sz > 0x300 ) return -2;       
+  eepTimerNum = reserveTimerNum(0);              
+  if(eepTimerNum < 0) return -3;                    
+  if(sz > sizeof(dataBuf)) return -4;                  
+
+   
+  tc_set_outputcompare(eepTimerNum);
+
+   
+  dataOffset = offset;
+  memcpy(dataBuf, data, sz);
+  dataSize   = sz;
+
+  return 0;
+}
+
+ 
+
+int
+eeprom_writeByte (word offset, byte data)
+{
+  return eeprom_writeData(offset, &data, 1);
+}
+
+ 
+
+
+int
+eeprom_writeWord (word offset, word data)
+{
+  return eeprom_writeData(offset, &data, 2);
+}
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-7223.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-7223.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-7223.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-7223.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,22 @@
+
+extern int foo(int);
+
+int main(int argn, char ** argv)
+{
+        char i;
+        int pos;
+        short d, e, f;
+
+        for(i=100;i>0;--i){
+                argn += i;
+        }
+
+        e = (short)i-argn;
+        d = argn / 1000;
+
+        pos = foo(d * e);
+
+        (*(((unsigned char *)0x1000)+(0x00))) |= 0x10;
+
+        return argn;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-7361.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-7361.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/pr-7361.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/pr-7361.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,211 @@
+# 5 "essai.c"
+# 1 "nanoK.h" 1
+# 26 "nanoK.h"
+# 1 "type_def.h" 1
+# 26 "type_def.h"
+typedef unsigned char u8;
+typedef unsigned short u16;
+typedef unsigned int u32;
+typedef signed char s8;
+typedef signed short s16;
+typedef signed int s32;
+# 27 "nanoK.h" 2
+# 45 "nanoK.h"
+u8 nanoK_init(void);
+# 56 "nanoK.h"
+u8 nanoK_task_init(u8 t, void (*fct)(void), u8* stk, u16 stk_len);
+# 65 "nanoK.h"
+u8 nanoK_aggregate_task(u8 t1, u8 t2);
+# 74 "nanoK.h"
+inline void nanoK_task_terminate(void);
+# 84 "nanoK.h"
+inline u8 nanoK_task_reset(u8 t);
+# 98 "nanoK.h"
+void nanoK_hook_init(void (*fct)(void), u8* stk, u16 stk_len);
+
+
+
+
+
+void nanoK_start(void);
+
+
+
+
+
+void nanoK_kernel(void);
+
+
+
+
+typedef struct {
+        struct {
+                u8 CCR;
+                u16 D;
+                u16 X;
+                u16 Y;
+                u16 PC;
+                u16 SP;
+        } hard_regs;
+        struct {
+                u16 r[8];
+                u16 tmp;
+                u16 z;
+                u16 xy;
+                u16 frame;
+        } soft_regs;
+} t_context;
+# 6 "essai.c" 2
+# 1 "vectors.h" 1
+# 26 "vectors.h"
+# 1 "type_def.h" 1
+# 27 "vectors.h" 2
+
+typedef enum {
+        Sci,
+        Spi,
+        Pulse_acc_input,
+        Pulse_acc_overf,
+        Timer_overf,
+        Output_compare_5,
+        Output_compare_4,
+        Output_compare_3,
+        Output_compare_2,
+        Output_compare_1,
+        Input_capture_3,
+        Input_capture_2,
+        Input_capture_1,
+        Real_time,
+        Irq,
+        Xirq,
+        Swi,
+        Illegal,
+        Cop_fail,
+        Cop_clock_fail
+
+} t_vector_num;
+
+extern u8 VECTORS_init(void);
+extern void VECTORS_set(t_vector_num n, void (*f)(void));
+# 7 "essai.c" 2
+# 23 "essai.c"
+extern u8 run_task_num;
+# 37 "essai.c"
+static u16 compteur;
+
+static u8 stk0[50];
+static void task0(void)
+{
+
+        while(1) {
+                (*((u8*)0x1003)) &= ~0x03;
+                (*((u8*)0x1003)) |= 0x00;
+                nanoK_task_terminate();
+        }
+}
+
+static u8 stk1[50];
+static void task1(void)
+{
+
+        while(1) {
+                (*((u8*)0x1003)) &= ~0x02;
+                (*((u8*)0x1003)) |= 0x01;
+                nanoK_task_terminate();
+        }
+}
+
+static u8 stk2[50];
+static void task2(void)
+{
+
+        while(1) {
+                (*((u8*)0x1003)) &= ~0x01;
+                (*((u8*)0x1003)) |= 0x02;
+                nanoK_task_terminate();
+        }
+}
+
+static u8 stk3[50];
+static void task3(void)
+{
+
+        while(1) {
+                (*((u8*)0x1003)) &= ~0x00;
+                (*((u8*)0x1003)) |= 0x03;
+                nanoK_task_terminate();
+        }
+}
+
+static u8 hook_stk[50];
+
+static void hook(void)
+{
+
+        compteur++;
+
+
+
+
+
+
+
+        (*((u8*)0x1025)) |= 0x40;
+
+}
+
+typedef void(*JMP)(void);
+typedef struct t_vectors_table {
+  u8 opcode;
+  JMP f;
+} t_vectors_table;
+
+int main(void)
+{
+
+        (*((u8*)0x1007)) = 0xf3;
+
+        nanoK_init();
+        VECTORS_init();
+        compteur = 0;
+
+
+        nanoK_task_init(0, task0, stk0, sizeof(stk0));
+
+
+        nanoK_task_init(1, task1, stk1, sizeof(stk1));
+
+
+        nanoK_task_init(2, task2, stk2, sizeof(stk2));
+
+
+        nanoK_task_init(3, task3, stk3, sizeof(stk3));
+
+
+        nanoK_hook_init(hook, hook_stk, sizeof(hook_stk));
+
+
+
+
+
+
+
+        VECTORS_set(Real_time, nanoK_kernel);
+        (*((u8*)0x1026)) |= 0x03;
+        (*((u8*)0x1024)) |= 0x43;
+
+
+
+        nanoK_start();
+
+
+        return 0;
+}
+
+
+
+
+void __premain() {
+  return;
+}
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/printf.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/printf.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/printf.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/printf.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,24 @@
+/*
+ * Simple replacement of printf() for use by GCC testsuite.
+ */
+#include <stdarg.h>
+#include <stddef.h>
+
+extern int vsprintf(char*, const char*, ...);
+extern int write(int, const char*, size_t);
+
+int
+printf(const char *fmt, ...)
+{
+  char buf[256];
+  va_list args;
+  int i;
+
+  va_start(args, fmt);
+  i=vsprintf(buf,fmt,args);
+  va_end(args);
+
+  write(0, buf, i);
+  return i;
+}
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/push.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/push.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/push.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/push.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,4 @@
+int bar()
+{
+  return toto(1, 2, 3, 4);
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/ret64.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/ret64.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/ret64.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/ret64.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,9 @@
+long long ret64L()
+{
+  return (long long) (1);
+}
+
+long long ret642L(int a, int b)
+{
+  return (long long) (a + b);
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/rotate.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/rotate.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/rotate.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/rotate.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,60 @@
+unsigned short rotate15(unsigned short a)
+{
+  return (a << 15) | (a >> 1);
+}
+unsigned short rotate14(unsigned short a)
+{
+  return (a << 14) | (a >> 2);
+}
+unsigned short rotate13(unsigned short a)
+{
+  return (a << 13) | (a >> 3);
+}
+unsigned short rotate12(unsigned short a)
+{
+  return (a << 12) | (a >> 4);
+}
+unsigned short rotate11(unsigned short a)
+{
+  return (a << 11) | (a >> 5);
+}
+unsigned short rotate10(unsigned short a)
+{
+  return (a << 10) | (a >> 6);
+}
+unsigned short rotate9(unsigned short a)
+{
+  return (a << 9) | (a >> 7);
+}
+unsigned short rotate8(unsigned short a)
+{
+  return (a << 8) | (a >> 8);
+}
+unsigned short rotate7(unsigned short a)
+{
+  return (a << 7) | (a >> 9);
+}
+unsigned short rotate6(unsigned short a)
+{
+  return (a << 6) | (a >> 10);
+}
+unsigned short rotate5(unsigned short a)
+{
+  return (a << 5) | (a >> 11);
+}
+unsigned short rotate4(unsigned short a)
+{
+  return (a << 4) | (a >> 12);
+}
+unsigned short rotate3(unsigned short a)
+{
+  return (a << 3) | (a >> 13);
+}
+unsigned short rotate2(unsigned short a)
+{
+  return (a << 2) | (a >> 14);
+}
+unsigned short rotate1(unsigned short a)
+{
+  return (a << 1) | (a >> 15);
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/sex.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/sex.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/sex.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/sex.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,5 @@
+short
+sexh (signed char *p)
+{
+  return *p;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/sext.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/sext.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/sext.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/sext.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,9 @@
+short get16(signed char a)
+{
+  return a;
+}
+
+long get(short a)
+{
+  return a;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/shift-1.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/shift-1.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/shift-1.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/shift-1.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,9 @@
+unsigned char Shift( unsigned char bitPosition )
+{
+        unsigned char mask;
+
+        mask = 1 <<  bitPosition;
+
+        return ( mask );
+}
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/shl.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/shl.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/shl.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/shl.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,6 @@
+unsigned long shl(unsigned long a, int b)
+{
+  a = a >> b;
+  bar(b);
+  return a;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/string.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/string.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/string.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/string.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,313 @@
+/*
+ *  linux/lib/string.c
+ *
+ *  Copyright (C) 1991, 1992  Linus Torvalds
+ */
+
+/*
+ * stupid library routines.. The optimized versions should generally be found
+ * as inline code in <asm-xx/string.h>
+ *
+ * These are buggy as well..
+ */
+ 
+#define NULL (void*)0
+typedef unsigned short size_t;
+
+char * ___strtok = NULL;
+
+#ifndef __HAVE_ARCH_STRCPY
+char * strcpy(char * dest,const char *src)
+{
+	char *tmp = dest;
+
+	while ((*dest++ = *src++) != '\0')
+		/* nothing */;
+	return tmp;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRNCPY
+char * strncpy(char * dest,const char *src,size_t count)
+{
+	char *tmp = dest;
+
+	while (count-- && (*dest++ = *src++) != '\0')
+		/* nothing */;
+
+	return tmp;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRCAT
+char * strcat(char * dest, const char * src)
+{
+	char *tmp = dest;
+
+	while (*dest)
+		dest++;
+	while ((*dest++ = *src++) != '\0')
+		;
+
+	return tmp;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRNCAT
+char * strncat(char *dest, const char *src, size_t count)
+{
+	char *tmp = dest;
+
+	if (count) {
+		while (*dest)
+			dest++;
+		while ((*dest++ = *src++)) {
+			if (--count == 0) {
+				*dest = '\0';
+				break;
+			}
+		}
+	}
+
+	return tmp;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRCMP
+int strcmp(const char * cs,const char * ct)
+{
+	register signed char __res;
+
+	while (1) {
+		if ((__res = *cs - *ct++) != 0 || !*cs++)
+			break;
+	}
+
+	return __res;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRNCMP
+int strncmp(const char * cs,const char * ct,size_t count)
+{
+	register signed char __res = 0;
+
+	while (count) {
+		if ((__res = *cs - *ct++) != 0 || !*cs++)
+			break;
+		count--;
+	}
+
+	return __res;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRCHR
+char * strchr(const char * s, int c)
+{
+	for(; *s != (char) c; ++s)
+		if (*s == '\0')
+			return NULL;
+	return (char *) s;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRRCHR
+char * strrchr(const char * s, int c)
+{
+       const char *p = s + strlen(s);
+       do {
+           if (*p == (char)c)
+               return (char *)p;
+       } while (--p >= s);
+       return NULL;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRLEN
+size_t strlen(const char * s)
+{
+	const char *sc;
+
+	for (sc = s; *sc != '\0'; ++sc)
+		/* nothing */;
+	return sc - s;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRNLEN
+size_t strnlen(const char * s, size_t count)
+{
+	const char *sc;
+
+	for (sc = s; count-- && *sc != '\0'; ++sc)
+		/* nothing */;
+	return sc - s;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRSPN
+size_t strspn(const char *s, const char *accept)
+{
+	const char *p;
+	const char *a;
+	size_t count = 0;
+
+	for (p = s; *p != '\0'; ++p) {
+		for (a = accept; *a != '\0'; ++a) {
+			if (*p == *a)
+				break;
+		}
+		if (*a == '\0')
+			return count;
+		++count;
+	}
+
+	return count;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRPBRK
+char * strpbrk(const char * cs,const char * ct)
+{
+	const char *sc1,*sc2;
+
+	for( sc1 = cs; *sc1 != '\0'; ++sc1) {
+		for( sc2 = ct; *sc2 != '\0'; ++sc2) {
+			if (*sc1 == *sc2)
+				return (char *) sc1;
+		}
+	}
+	return NULL;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRTOK
+char * strtok(char * s,const char * ct)
+{
+	char *sbegin, *send;
+
+	sbegin  = s ? s : ___strtok;
+	if (!sbegin) {
+		return NULL;
+	}
+	sbegin += strspn(sbegin,ct);
+	if (*sbegin == '\0') {
+		___strtok = NULL;
+		return( NULL );
+	}
+	send = strpbrk( sbegin, ct);
+	if (send && *send != '\0')
+		*send++ = '\0';
+	___strtok = send;
+	return (sbegin);
+}
+#endif
+
+#ifndef __HAVE_ARCH_MEMSET
+void * memset(void * s,char c,size_t count)
+{
+	char *xs = (char *) s;
+
+	while (count--)
+		*xs++ = c;
+
+	return s;
+}
+#endif
+
+#ifndef __HAVE_ARCH_BCOPY
+char * bcopy(const char * src, char * dest, int count)
+{
+	char *tmp = dest;
+
+	while (count--)
+		*tmp++ = *src++;
+
+	return dest;
+}
+#endif
+
+#ifndef __HAVE_ARCH_MEMCPY
+void * memcpy(void * dest,const void *src,size_t count)
+{
+	char *tmp = (char *) dest, *s = (char *) src;
+
+	while (count--)
+		*tmp++ = *s++;
+
+	return dest;
+}
+#endif
+
+#ifndef __HAVE_ARCH_MEMMOVE
+void * memmove(void * dest,const void *src,size_t count)
+{
+	char *tmp, *s;
+
+	if (dest <= src) {
+		tmp = (char *) dest;
+		s = (char *) src;
+		while (count--)
+			*tmp++ = *s++;
+		}
+	else {
+		tmp = (char *) dest + count;
+		s = (char *) src + count;
+		while (count--)
+			*--tmp = *--s;
+		}
+
+	return dest;
+}
+#endif
+
+#ifndef __HAVE_ARCH_MEMCMP
+int memcmp(const void * cs,const void * ct,size_t count)
+{
+	const unsigned char *su1, *su2;
+	signed char res = 0;
+
+	for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
+		if ((res = *su1 - *su2) != 0)
+			break;
+	return res;
+}
+#endif
+
+/*
+ * find the first occurrence of byte 'c', or 1 past the area if none
+ */
+#ifndef __HAVE_ARCH_MEMSCAN
+void * memscan(void * addr, int c, size_t size)
+{
+	unsigned char * p = (unsigned char *) addr;
+
+	while (size) {
+		if (*p == c)
+			return (void *) p;
+		p++;
+		size--;
+	}
+  	return (void *) p;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRSTR
+char * strstr(const char * s1,const char * s2)
+{
+	int l1, l2;
+
+	l2 = strlen(s2);
+	if (!l2)
+		return (char *) s1;
+	l1 = strlen(s1);
+	while (l1 >= l2) {
+		l1--;
+		if (!memcmp(s1,s2,l2))
+			return (char *) s1;
+		s1++;
+	}
+	return NULL;
+}
+#endif
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/tst-asm.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/tst-asm.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/tst-asm.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/tst-asm.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,19 @@
+void __premain()
+{
+  __asm__ volatile("clra\n\t"
+	                     "tap" : : : "d");
+}
+
+void inline foo()
+{
+  char* msg = "TEST STRING";
+  unsigned char code = 16;
+  
+  __asm__ __volatile__("jsr  0x7012"
+                       : : "x"(msg), "d"(code));
+}
+
+int main()
+{
+  ;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/vsprintf.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/vsprintf.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/compile-scz/vsprintf.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/compile-scz/vsprintf.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,320 @@
+/*
+ *  linux/lib/vsprintf.c
+ *
+ *  Copyright (C) 1991, 1992  Linus Torvalds
+ */
+
+/* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */
+/*
+ * Wirzenius wrote this portably, Torvalds fucked it up :-)
+ */
+
+#include <stdarg.h>
+/*#include <sys/types.h>*/
+/*#include <linux/string.h>*/
+/*#include <ctype.h> */
+
+#define isxdigit(c) (((c) >= '0' && (c) <= '9') || \
+                     ((c) >= 'a' && (c) <= 'f') || \
+                     ((c) >= 'A' && (c) <= 'F'))
+#define isdigit(c)  ((c) >= '0' && (c) <= '9')
+#define islower(c)  ((c) >= 'a')
+#define toupper(c)  ((c) - 'a' + 'A')
+
+unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base)
+{
+	unsigned long result = 0,value;
+
+	if (!base) {
+		base = 10;
+		if (*cp == '0') {
+			base = 8;
+			cp++;
+			if ((*cp == 'x') && isxdigit(cp[1])) {
+				cp++;
+				base = 16;
+			}
+		}
+	}
+	while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp)
+	    ? toupper(*cp) : *cp)-'A'+10) < base) {
+		result = result*base + value;
+		cp++;
+	}
+	if (endp)
+		*endp = (char *)cp;
+	return result;
+}
+
+/* we use this so that we can do without the ctype library */
+#define is_digit(c)	((c) >= '0' && (c) <= '9')
+
+static int skip_atoi(const char **s)
+{
+	int i=0;
+
+	while (is_digit(**s))
+		i = i*10 + *((*s)++) - '0';
+	return i;
+}
+
+#define ZEROPAD	1		/* pad with zero */
+#define SIGN	2		/* unsigned/signed long */
+#define PLUS	4		/* show plus */
+#define SPACE	8		/* space if plus */
+#define LEFT	16		/* left justified */
+#define SPECIAL	32		/* 0x */
+#define LARGE	64		/* use 'ABCDEF' instead of 'abcdef' */
+
+#define do_div(n,base) ({ \
+int __res; \
+__res = ((unsigned long) n) % (unsigned) base; \
+n = ((unsigned long) n) / (unsigned) base; \
+__res; })
+
+static char * number(char * str, long num, int base, int size, int precision
+	,int type)
+{
+	char c,sign,tmp[66];
+	const char *digits="0123456789abcdefghijklmnopqrstuvwxyz";
+	int i;
+
+	if (type & LARGE)
+		digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ";
+	if (type & LEFT)
+		type &= ~ZEROPAD;
+	if (base < 2 || base > 36)
+		return 0;
+	c = (type & ZEROPAD) ? '0' : ' ';
+	sign = 0;
+	if (type & SIGN) {
+		if (num < 0) {
+			sign = '-';
+			num = -num;
+			size--;
+		} else if (type & PLUS) {
+			sign = '+';
+			size--;
+		} else if (type & SPACE) {
+			sign = ' ';
+			size--;
+		}
+	}
+	if (type & SPECIAL) {
+		if (base == 16)
+			size -= 2;
+		else if (base == 8)
+			size--;
+	}
+	i = 0;
+	if (num == 0)
+		tmp[i++]='0';
+	else while (num != 0)
+		tmp[i++] = digits[do_div(num,base)];
+	if (i > precision)
+		precision = i;
+	size -= precision;
+	if (!(type&(ZEROPAD+LEFT)))
+		while(size-->0)
+			*str++ = ' ';
+	if (sign)
+		*str++ = sign;
+	if (type & SPECIAL)
+		if (base==8)
+			*str++ = '0';
+		else if (base==16) {
+			*str++ = '0';
+			*str++ = digits[33];
+		}
+	if (!(type & LEFT))
+		while (size-- > 0)
+			*str++ = c;
+	while (i < precision--)
+		*str++ = '0';
+	while (i-- > 0)
+		*str++ = tmp[i];
+	while (size-- > 0)
+		*str++ = ' ';
+	return str;
+}
+
+int vsprintf(char *buf, const char *fmt, va_list args)
+{
+	int len;
+	unsigned long num;
+	int i, base;
+	char * str;
+	const char *s;
+
+	int flags;		/* flags to number() */
+
+	int field_width;	/* width of output field */
+	int precision;		/* min. # of digits for integers; max
+				   number of chars for from string */
+	int qualifier;		/* 'h', 'l', or 'L' for integer fields */
+
+	for (str=buf ; *fmt ; ++fmt) {
+		if (*fmt != '%') {
+			*str++ = *fmt;
+			continue;
+		}
+			
+		/* process flags */
+		flags = 0;
+		repeat:
+			++fmt;		/* this also skips first '%' */
+			switch (*fmt) {
+				case '-': flags |= LEFT; goto repeat;
+				case '+': flags |= PLUS; goto repeat;
+				case ' ': flags |= SPACE; goto repeat;
+				case '#': flags |= SPECIAL; goto repeat;
+				case '0': flags |= ZEROPAD; goto repeat;
+				}
+		
+		/* get field width */
+		field_width = -1;
+		if (is_digit(*fmt))
+			field_width = skip_atoi(&fmt);
+		else if (*fmt == '*') {
+			++fmt;
+			/* it's the next argument */
+			field_width = va_arg(args, int);
+			if (field_width < 0) {
+				field_width = -field_width;
+				flags |= LEFT;
+			}
+		}
+
+		/* get the precision */
+		precision = -1;
+		if (*fmt == '.') {
+			++fmt;	
+			if (is_digit(*fmt))
+				precision = skip_atoi(&fmt);
+			else if (*fmt == '*') {
+				++fmt;
+				/* it's the next argument */
+				precision = va_arg(args, int);
+			}
+			if (precision < 0)
+				precision = 0;
+		}
+
+		/* get the conversion qualifier */
+		qualifier = -1;
+		if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L') {
+			qualifier = *fmt;
+			++fmt;
+		}
+
+		/* default base */
+		base = 10;
+
+		switch (*fmt) {
+		case 'c':
+			if (!(flags & LEFT))
+				while (--field_width > 0)
+					*str++ = ' ';
+			*str++ = (unsigned char) va_arg(args, int);
+			while (--field_width > 0)
+				*str++ = ' ';
+			continue;
+
+		case 's':
+			s = va_arg(args, char *);
+			if (!s)
+				s = "<NULL>";
+
+			len = strlen(s);
+                        if (len > precision && precision >= 0)
+                          len = precision;
+
+			if (!(flags & LEFT))
+				while (len < field_width--)
+					*str++ = ' ';
+			for (i = 0; i < len; ++i)
+				*str++ = *s++;
+			while (len < field_width--)
+				*str++ = ' ';
+			continue;
+
+		case 'p':
+			if (field_width == -1) {
+				field_width = 2*sizeof(void *);
+				flags |= ZEROPAD;
+			}
+			str = number(str,
+				(unsigned long) va_arg(args, void *), 16,
+				field_width, precision, flags);
+			continue;
+
+
+		case 'n':
+			if (qualifier == 'l') {
+				long * ip = va_arg(args, long *);
+				*ip = (str - buf);
+			} else {
+				int * ip = va_arg(args, int *);
+				*ip = (str - buf);
+			}
+			continue;
+
+		/* integer number formats - set up the flags and "break" */
+		case 'o':
+			base = 8;
+			break;
+
+		case 'X':
+			flags |= LARGE;
+		case 'x':
+			base = 16;
+			break;
+
+		case 'd':
+		case 'i':
+			flags |= SIGN;
+		case 'u':
+			break;
+
+                        /* For GCC test gcc.c-torture/execute/ieee/920810-1.c */
+                case 'g':
+                  *str++ = '0';
+                  continue;
+                  
+		default:
+			if (*fmt != '%')
+				*str++ = '%';
+			if (*fmt)
+				*str++ = *fmt;
+			else
+				--fmt;
+			continue;
+		}
+		if (qualifier == 'l')
+			num = va_arg(args, unsigned long);
+		else if (qualifier == 'h')
+			if (flags & SIGN)
+				num = va_arg(args, int);
+			else
+				num = va_arg(args, unsigned int);
+		else if (flags & SIGN)
+			num = va_arg(args, int);
+		else
+			num = va_arg(args, unsigned int);
+		str = number(str, num, base, field_width, precision, flags);
+	}
+	*str = '\0';
+	return str-buf;
+}
+
+int sprintf(char * buf, const char *fmt, ...)
+{
+	va_list args;
+	int i;
+
+	va_start(args, fmt);
+	i=vsprintf(buf,fmt,args);
+	va_end(args);
+	return i;
+}
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute/20020404-1.x gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute/20020404-1.x
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute/20020404-1.x	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute/20020404-1.x	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,6 @@
+# This test fails on HC11/HC12 when it is compiled with 16-bit integers
+# because it passes value 0x1eadbeef in an int.
+if { [istarget "m6811-*-*"] || [istarget "m6812-*-*"] } {
+    return 1
+}
+return 0
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute/20020720-1.x gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute/20020720-1.x
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute/20020720-1.x	Mon Jan  3 02:43:45 2005
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute/20020720-1.x	Sat Nov  5 19:17:25 2005
@@ -29,7 +29,7 @@ set torture_eval_before_compile {
     set compiler_conditional_xfail_data {
         "This test fails to optimize completely on certain platforms." \
         { "xtensa-*-*" "sh-*-*" "arm*-*-*" "strongarm*-*-*" "xscale*-*-*" \
-	  "h8300*-*-*" "x86_64-*-*" "cris-*-*" } \
+	  "h8300*-*-*" "x86_64-*-*" "cris-*-*" "m6811-*-*" "m6812-*-*" } \
         { "*" } \
         { "-O0" }
     }
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute/20021024-1.x gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute/20021024-1.x
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute/20021024-1.x	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute/20021024-1.x	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,10 @@
+# 16-bit "int"
+if { [istarget "xstormy16-*"] } {
+	return 1
+}
+if { [istarget "m6811-*-*"] || [istarget "m6812-*-*"]} {
+	return 1
+}
+
+return 0
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute/960312-1.x gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute/960312-1.x
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute/960312-1.x	Sun Mar  2 23:35:16 2003
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute/960312-1.x	Sat Nov  5 19:17:25 2005
@@ -2,6 +2,6 @@
 # is uses an asm that requires two 32-bit registers (int).  It passes
 # when using -mshort because there are enough registers;  force -mshort.
 if { [istarget "m6811-*-*"] || [istarget "m6812-*-*"] } {
-	set options "-mshort"
+	set additional_flags "-mshort"
 }
 return 0
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute/ieee/920810-1.x gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute/ieee/920810-1.x
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute/ieee/920810-1.x	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute/ieee/920810-1.x	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,7 @@
+# sprintf %g is not supported on HC11/HC12 (too big for a final link)
+if { [istarget "m6811-*-*"] || [istarget "m6812-*-*"]} {
+	return 1
+}
+
+return 0
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute/shiftdi.x gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute/shiftdi.x
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute/shiftdi.x	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute/shiftdi.x	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,10 @@
+# 16-bit "int"
+if { [istarget "xstormy16-*"] } {
+	return 1
+}
+if { [istarget "m6811-*-*"] || [istarget "m6812-*-*"]} {
+	return 1
+}
+
+return 0
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/andqi.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/andqi.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/andqi.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/andqi.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,52 @@
+signed char value;
+
+signed char values[] = {
+  0, 1, 2, 3, 5, 7, 9, 16, 127, 128
+};
+
+signed char expect[] = {
+  0, 0, 0, 0, 4, 4, 8, 0, 12, 0
+};
+
+void
+andqi_global ()
+{
+  value &= 12;
+}
+
+void
+andqi_ptr (signed char* p)
+{
+  *p &= 12;
+}
+
+signed char
+andqi_return (signed char v)
+{
+  return v & 12;
+}
+
+int
+main()
+{
+  unsigned i;
+  signed char c;
+  
+  for (i = 0; i < sizeof(values) / sizeof(values[0]); i++)
+    {
+      value = values[i];
+      andqi_global ();
+      if (value != expect[i])
+        abort ();
+
+      c = values[i];
+      andqi_ptr (&c);
+      if (c != expect[i])
+        abort ();
+
+      c = andqi_return (values[i]);
+      if (c != expect[i])
+        abort ();
+    }
+  exit (0);
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/autoinc.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/autoinc.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/autoinc.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/autoinc.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,70 @@
+void
+post_inc_short (unsigned short *dst, unsigned short *src)
+{
+  *dst++ = *src++;
+  *dst++ = 0xabcd;
+  *dst++ = src[2];
+  *dst = *src++;
+}
+
+void
+pre_inc_short (unsigned short *dst, unsigned short *src)
+{
+  *++dst = *++src;
+  *++dst = 0xabcd;
+  *++dst = src[3];
+  *++dst = *++src;
+}
+
+
+void
+post_inc_long (unsigned long *dst, unsigned long *src)
+{
+  *dst++ = *src++;
+  *dst++ = 0xabcdef23;
+  *dst++ = src[2];
+  *dst = *src++;
+}
+
+void
+pre_inc_long (unsigned long *dst, unsigned long *src)
+{
+  *++dst = *++src;
+  *++dst = 0xabcdef23;
+  *++dst = src[3];
+  *++dst = *++src;
+}
+
+int
+main ()
+{
+  unsigned short dst[10];
+  unsigned short src[10];
+  unsigned long dstl[10];
+  unsigned long srcl[10];
+
+  src[0] = 0x1234;
+  src[1] = 0x2345;
+  src[3] = 0x3456;
+  src[4] = 0x4567;
+  post_inc_short (dst, src);
+  if (dst[0] != 0x1234 || dst[1] != 0xabcd
+      || dst[2] != 0x3456 || dst[3] != 0x2345)
+    abort ();
+
+  srcl[0] = 0x12345678;
+  srcl[1] = 0x23456789;
+  srcl[3] = 0x3456789a;
+  srcl[4] = 0x456789ab;
+  post_inc_long (dstl, srcl);
+  if (dstl[0] != 0x12345678 || dstl[1] != 0xabcdef23
+      || dstl[2] != 0x3456789a || dstl[3] != 0x23456789)
+    abort ();
+
+  pre_inc_long (dstl, &srcl[-1]);
+  if (dstl[1] != 0x12345678 || dstl[2] != 0xabcdef23
+      || dstl[3] != 0x3456789a || dstl[4] != 0x23456789)
+    abort ();
+
+  return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/b-20010414.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/b-20010414.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/b-20010414.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/b-20010414.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,55 @@
+enum v {
+  L1, L2, L3
+};
+void bar();
+
+int
+get(unsigned char a, unsigned char b, long *c, enum v d)
+{
+  int i, j;
+
+  bar ();
+  switch (d)
+    {
+    case L1:
+      i = 1;
+      break;
+
+    case L2:
+      i = b;
+      break;
+
+    case L3:
+      i = *c;
+      break;
+    }
+  j = 0;
+  while (i > 0)
+    {
+      j += i;
+      i--;
+    }
+  return j;
+}
+
+void
+bar()
+{
+  ;
+}
+
+int
+main ()
+{
+  long a = 0x12345678;
+  int result;
+  
+  result = get (1, 2, &a, L2);
+  if (a != 0x12345678)
+    abort ();
+
+  if (result != 3)
+    abort ();
+  
+  return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/b-20020520.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/b-20020520.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/b-20020520.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/b-20020520.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,13 @@
+ static  struct {
+     unsigned int b0 : 1;
+   int v : 4;
+   int b : 8;
+  }tester;
+
+int main()
+{
+  tester.b = 4;
+  tester.v = 2;
+  return tester.b0;
+}
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/b-20040816.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/b-20040816.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/b-20040816.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/b-20040816.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,22 @@
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned long uint32_t;
+
+uint32_t test;
+
+void shl(uint8_t Nr)
+{
+    test |= (1L<<Nr);
+}
+ 
+int main(void)
+{
+  test = 1;
+  shl(2);
+  if (test != 5L)
+     return 1;
+  shl(17);
+  if (test != (5L | (1L << 17)))
+     return 1;
+  return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/b-20051105.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/b-20051105.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/b-20051105.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/b-20051105.c	Sat Nov  5 21:14:46 2005
@@ -0,0 +1,79 @@
+struct fields
+{
+  unsigned long long u1 : 15;
+  unsigned long long u2 : 33;
+  unsigned long long u3 : 16;
+  signed long long   s1 : 15;
+  signed long long   s2 : 33;
+  signed long long   s3 : 16;
+} flags;
+
+struct sfields
+{
+  unsigned long u1 : 15;
+  unsigned long u2 : 17;
+  unsigned long u3 : 16;
+  signed long    s1 : 15;
+  signed long    s2 : 17;
+  signed long    s3 : 16;
+} sflags;
+
+void break1()
+{
+}
+
+#define FIELD(S,VAL,CODE) \
+  flags.S = VAL;          \
+  break1();               \
+  if (flags.S != VAL) {   \
+    return CODE;          \
+  }
+
+#define CHECK_U2(CODE) \
+  FIELD(u2,1,CODE+1);        \
+  FIELD(u2,2,CODE+1);        \
+  FIELD(u2,0x100,CODE+1);     \
+  FIELD(u2,0xabcd,CODE+1);    \
+  FIELD(u2,0x12ab34cd,CODE+1)
+
+#define CHECK_S2(CODE) \
+  FIELD(s2,1,CODE+1);        \
+  FIELD(s2,2,CODE+1);        \
+  FIELD(s2,0x100,CODE+1);     \
+  FIELD(s2,0xabcd,CODE+1);    \
+  FIELD(s2,0x12ab34cd,CODE+1)
+
+int main() 
+{
+  flags.s2 = 1;
+  break1();
+  if (flags.s2 != 1)
+    return 1;
+
+  flags.u2 = 0x1aaaaffffLL;
+  break1();
+  if (flags.u2 != 0x1aaaaffffLL)
+    return 2;
+  
+  flags.u2 = ~0x1aaaaffffLL;
+  break1();
+  if (flags.u2 != 0x055550000LL)
+    return 3;
+
+  sflags.s2 = 1;
+  break1();
+  if (sflags.s2 != 1)
+    return 4;
+
+  sflags.u2 = 0x1aaffL;
+  break1();
+  if (sflags.u2 != 0x1aaffL)
+    return 5;
+  
+  sflags.u2 = ~0x1aaffL;
+  if (sflags.u2 != 0x5500L)
+    return 6;
+
+  CHECK_U2(50);
+  return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/bigmul.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/bigmul.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/bigmul.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/bigmul.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,29 @@
+long a = 10000;
+long b = 200000;
+unsigned long c = 100000;
+unsigned long d = 20000;
+long long e = 100000000LL;
+long long f = 200000000LL;
+
+int main()
+{
+  long r;
+  unsigned long p;
+  long long q;
+  
+  r = a * b;
+  if (r != 10000 * 200000)
+    return 1;
+
+  p = c * d;
+  if (p != 100000 * 20000)
+    return 1;
+
+  q = e * f;
+  if (q != 100000000LL * 200000000LL)
+    return 1;
+  
+  return 0;
+}
+
+  
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/bit.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/bit.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/bit.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/bit.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,95 @@
+unsigned
+bit_char (unsigned char n)
+{
+  unsigned cnt = 0;
+
+  if (n & 1) cnt++;
+  if (n & 2) cnt++;
+  if (n & 4) cnt++;
+  if (n & 8) cnt++;
+  if (n & 16) cnt++;
+  if (n & 32) cnt++;
+  if (n & 64) cnt++;
+  if (n & 128) cnt++;
+  return cnt;
+}
+
+unsigned
+bit_short (unsigned short n)
+{
+  unsigned cnt = 0;
+
+  if (n & 1) cnt++;
+  if (n & 128) cnt++;
+  if (n & 256) cnt++;
+  if (n & 0x8000) cnt++;
+
+  return cnt + bit_char (n) + bit_char (n >> 8);
+}
+
+unsigned
+bit_ulong (unsigned long n)
+{
+  unsigned cnt = 0;
+
+  if (n & 1) cnt++;
+  if (n & 0x8000) cnt++;  
+  if (n & 0x10000) cnt++;
+  if (n & 0x80000000) cnt++;
+  return cnt + bit_short (n) + bit_short (n >> 16);
+}
+
+unsigned
+bit_ulonglong (unsigned long long n)
+{
+  unsigned cnt = 0;
+
+  if (n & 1LL) cnt++;
+  if (n & 0x80000000LL) cnt++;  
+  if (n & 0x100000000LL) cnt++;
+  if (n & 0x8000000000000000LL) cnt++;
+  return cnt + bit_ulong (n) + bit_ulong (n >> 32);
+}
+
+int
+main ()
+{
+  long long n;
+  int i, j;
+  unsigned cnt_char, cnt_short, cnt_long, cnt_longlong;
+  
+  for (i = 0; i < 64; i++)
+    {
+      n = (1LL << i);
+      cnt_char = 0;
+      cnt_short = 0;
+      cnt_long  = 0;
+      cnt_longlong = bit_ulonglong (n);
+      for (j = 0; j < 8; j++)
+	{
+	  cnt_char += bit_char (n >> (j * 8));
+	  if ((j & 1) == 0)
+	    cnt_short += bit_short (n >> (j * 8));
+
+	  if ((j & 3) == 0)
+	    cnt_long += bit_ulong (n >> (j * 8));
+	}
+#if 0
+      printf ("%d: %d %d %d %d\n", i, cnt_char, cnt_short,
+	      cnt_long, cnt_longlong);
+#endif
+      if ((i % 8) == 0 || (i % 8) == 7)
+	cnt_short --, cnt_long --, cnt_longlong --;
+
+      if ((i % 16) == 0 || (i % 16) == 15)
+	cnt_long --, cnt_longlong --;
+
+      if ((i % 32) == 0 || (i % 32) == 31)
+	cnt_longlong --;
+
+      if (cnt_short != cnt_char || cnt_short != cnt_long
+	  || cnt_long != cnt_longlong || cnt_char != 1)
+	exit (1);
+    }
+  return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/bitfield.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/bitfield.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/bitfield.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/bitfield.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,328 @@
+struct bfield 
+{
+  int b1 : 1;
+  int b2 : 2;
+  int b3 : 3;
+  int b4 : 4;
+  int b5 : 5;
+  int b6 : 6;
+  int b7 : 7;
+  int b8 : 8;
+  int b9 : 9;
+  int b10: 10;
+  int b11: 11;
+  int b12: 12;
+  int b13: 13;
+  int b14: 14;
+  int b15: 15;
+};
+
+struct bfield
+fillup (int value)
+{
+  struct bfield bf;
+
+  bf.b1 = value;
+  bf.b2 = value;
+  bf.b3 = value;
+  bf.b4 = value;
+  bf.b5 = value;
+  bf.b6 = value;
+  bf.b7 = value;
+  bf.b8 = value;
+  bf.b9 = value;
+  bf.b10 = value;
+  bf.b11 = value;
+  bf.b12 = value;
+  bf.b13 = value;
+  bf.b14 = value;
+  bf.b15 = value;
+  return bf;
+}
+
+int
+compare (struct bfield b1, struct bfield b2)
+{
+  if (b1.b1 != b2.b1)
+    return 1;
+  if (b1.b2 != b2.b2)
+    return 2;
+  if (b1.b3 != b2.b3)
+    return 3;
+  if (b1.b4 != b2.b4)
+    return 4;
+  if (b1.b5 != b2.b5)
+    return 5;
+  if (b1.b6 != b2.b6)
+    return 6;
+  if (b1.b7 != b2.b7)
+    return 7;
+  if (b1.b8 != b2.b8)
+    return 8;
+  if (b1.b9 != b2.b9)
+    return 9;
+  if (b1.b10 != b2.b10)
+    return 10;
+  if (b1.b11 != b2.b11)
+    return 11;
+  if (b1.b12 != b2.b12)
+    return 12;
+  if (b1.b13 != b2.b13)
+    return 13;
+  if (b1.b14 != b2.b14)
+    return 14;
+  if (b1.b15 != b2.b15)
+    return 15;
+
+  return 0;
+}
+
+int
+expect_value (int n, int bits)
+{
+  if (n & (1 << (bits - 1)))
+    return (n & ((1 << bits) - 1)) | ~((1 << bits) - 1);
+  else
+    return (n & ((1 << bits) - 1));
+}
+
+
+int
+main ()
+{
+  long long n;
+  long i, j;
+  unsigned cnt_char, cnt_short, cnt_long, cnt_longlong;
+  struct bfield b1, b2;
+  
+  for (i = 0; i < 32768; )
+    {
+      int res;
+
+      b1 = fillup (i);
+      b2 = fillup (i);
+#define exit(P) {printf ("At %d\n", __LINE__); return 1; }
+
+      if (b1.b1 != expect_value (i, 1))
+	exit (1);
+      if (b1.b2 != expect_value (i, 2))
+	exit (1);
+      if (b1.b3 != expect_value (i, 3))
+	exit (1);
+      if (b1.b4 != expect_value (i, 4))
+	exit (1);
+      if (b1.b5 != expect_value (i, 5))
+	exit (1);
+      if (b1.b6 != expect_value (i, 6))
+	exit (1);
+      if (b1.b7 != expect_value (i, 7))
+	exit (1);
+      if (b1.b8 != expect_value (i, 8))
+	exit (1);
+      if (b1.b9 != expect_value (i, 9))
+	exit (1);
+      if (b1.b10 != expect_value (i, 10))
+	exit (1);
+      if (b1.b11 != expect_value (i, 11))
+	exit (1);
+      if (b1.b12 != expect_value (i, 12))
+	exit (1);
+      if (b1.b13 != expect_value (i, 13))
+	exit (1);
+      if (b1.b14 != expect_value (i, 14))
+	exit (1);
+
+      if (b1.b15 != expect_value (i, 15))
+	exit (1);
+
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+
+      /* B1 */
+      b2.b1 = ~b2.b1;
+      res = compare (b1, b2);
+      if (res != 1)
+	exit (1);
+
+      b2.b1 = b1.b1;
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+      
+      /* B2 */
+      b2.b2 = ~b2.b2;
+      res = compare (b1, b2);
+      if (res != 2)
+	exit (1);
+
+      b2.b2 = b1.b2;
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+      
+      /* B3 */
+      b2.b3 = ~b2.b3;
+      res = compare (b1, b2);
+      if (res != 3)
+	exit (1);
+
+      b2.b3 = b1.b3;
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+      
+      /* B4 */
+      b2.b4 = ~b2.b4;
+      res = compare (b1, b2);
+      if (res != 4)
+	exit (1);
+
+      b2.b4 = b1.b4;
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+      
+      /* B5 */
+      b2.b5 = ~b2.b5;
+      res = compare (b1, b2);
+      if (res != 5)
+	exit (1);
+
+      b2.b5 = b1.b5;
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+
+      /* B6 */
+      b2.b6 = ~b2.b6;
+      res = compare (b1, b2);
+      if (res != 6)
+	exit (1);
+
+      b2.b6 = b1.b6;
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+
+      /* B7 */
+      b2.b7 = ~b2.b7;
+      res = compare (b1, b2);
+      if (res != 7)
+	exit (1);
+
+      b2.b7 = b1.b7;
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+
+      /* B8 */
+      b2.b8 = ~b2.b8;
+      res = compare (b1, b2);
+      if (res != 8)
+	exit (1);
+
+      b2.b8 = b1.b8;
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+
+      /* B9 */
+      b2.b9 = ~b2.b9;
+      res = compare (b1, b2);
+      if (res != 9)
+	exit (1);
+
+      b2.b9 = b1.b9;
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+
+      /* B10 */
+      b2.b10 = ~b2.b10;
+      res = compare (b1, b2);
+      if (res != 10)
+	exit (1);
+
+      b2.b10 = b1.b10;
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+
+      /* B10 */
+      b2.b10 = ~b2.b10;
+      res = compare (b1, b2);
+      if (res != 10)
+	exit (1);
+
+      b2.b10 = b1.b10;
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+
+      /* B11 */
+      b2.b11 = ~b2.b11;
+      res = compare (b1, b2);
+      if (res != 11)
+	exit (1);
+
+      b2.b11 = b1.b11;
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+
+      /* B12 */
+      b2.b12 = ~b2.b12;
+      res = compare (b1, b2);
+      if (res != 12)
+	exit (1);
+
+      b2.b12 = b1.b12;
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+
+      /* B13 */
+      b2.b13 = ~b2.b13;
+      res = compare (b1, b2);
+      if (res != 13)
+	exit (1);
+
+      b2.b13 = b1.b13;
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+
+      /* B14 */
+      b2.b14 = ~b2.b14;
+      res = compare (b1, b2);
+      if (res != 14)
+	exit (1);
+
+      b2.b14 = b1.b14;
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+
+      /* B15 */
+      b2.b15 = ~b2.b15;
+      res = compare (b1, b2);
+      if (res != 15)
+	exit (1);
+
+      b2.b15 = b1.b15;
+      res = compare (b1, b2);
+      if (res != 0)
+	exit (1);
+
+      if (i < 300)
+        {
+          i++;
+        }
+      else
+        {
+          i += 119;
+        }
+    }
+  return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/bset.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/bset.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/bset.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/bset.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,13 @@
+/* Handle GEL page0 indications.  The global/static variables
+   specified with that attribute will be put within page0.  */
+#define PAGE0_ATTRIBUTE __attribute__((section(".page0")))
+
+char var PAGE0_ATTRIBUTE;
+
+int main()
+{
+  var |= 1;
+  if (var & 2)
+    var &= 8;
+  return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/execute.exp gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/execute.exp
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/execute.exp	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/execute.exp	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,43 @@
+# Copyright (C) 1991, 1992, 1993, 1995, 1997 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 
+
+# This file was written by Rob Savoye. (rob@cygnus.com)
+# Modified and maintained by Jeffrey Wheat (cassidy@cygnus.com)
+
+#
+# These tests come from Torbjorn Granlund (tege@cygnus.com)
+# C torture test suite.
+#
+
+if $tracelevel then {
+    strace $tracelevel
+}
+
+# load support procs
+load_lib c-torture.exp
+
+#
+# main test loop
+#
+
+foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.c]] {
+    # If we're only testing specific files and this isn't one of them, skip it.
+    if ![runtest_file_p $runtests $src] then {
+	continue
+    }
+
+    c-torture-execute $src
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/malloc.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/malloc.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/malloc.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/malloc.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,32 @@
+#include <stdlib.h>
+#include <string.h>
+
+int main()
+{
+  char *p[100];
+  int i, j;
+  
+  for (i = 0; i < 100; i++)
+    {
+      p[i] = malloc (40);
+      /* printf ("p[%d] = 0x%02x\n", i, p[i]); */
+    }
+
+  for (i = 0; i < 10; i++)
+    for (j = 0; j < 32; j++)
+      p[i][j] = i + j + ' ';
+
+  for (i = 0; i < 10; i++)
+    p[i][32] = 0;
+
+  for (i = 0; i < 10; i++)
+    for (j = 0; j < 10; j++)
+      if (i == j)
+        {
+          if (strcmp (p[i], p[j]) != 0)
+            return 1;
+        }
+      else if (strcmp (p[i], p[j]) == 0)
+        return 1;
+  return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/memset-2003-01-25.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/memset-2003-01-25.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/memset-2003-01-25.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/memset-2003-01-25.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,9 @@
+#include <string.h>
+
+char foo[10];
+
+int main()
+{
+  memset (foo, 1, sizeof (foo));
+  return foo[0] - 1;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/mul-1.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/mul-1.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/mul-1.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/mul-1.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,114 @@
+unsigned char
+frac_char (unsigned char n)
+{
+  if (n > 1)
+    return n * frac_char (n - 1);
+  else
+    return 1;
+}
+
+unsigned short
+frac_ushort (unsigned short n)
+{
+  if (n > 1)
+    return n * frac_ushort (n - 1);
+  else
+    return 1;
+}
+
+short
+frac_short (short n)
+{
+  if (n > 1)
+    return n * frac_short (n - 1);
+  else
+    return 1;
+}
+
+unsigned long
+frac_ulong (unsigned long n)
+{
+  if (n > 1)
+    return n * frac_ulong (n - 1);
+  else
+    return 1;
+}
+
+long
+frac_long (long n)
+{
+  if (n > 1)
+    return n * frac_long (n - 1);
+  else
+    return 1;
+}
+
+unsigned long long
+frac_ulonglong (unsigned long long n)
+{
+  if (n > 1)
+    return n * frac_ulonglong (n - 1);
+  else
+    return 1;
+}
+
+long long
+frac_longlong (long long n)
+{
+  if (n > 1)
+    return n * frac_longlong (n - 1);
+  else
+    return 1;
+}
+
+long long ftable[] = {
+  1, 2, 6, 24, 120, 720, 5040, 40320, 362880,
+  3628800, 39916800, 479001600, 6227020800,
+  87178291200, 1307674368000, 20922789888000,
+  355687428096000, 6402373705728000, 121645100408832000,
+  2432902008176640000
+};
+
+void
+error (char *func, int n, long long result)
+{
+  printf ("Failed: %s (%d) => %lld\n", func, n, result);
+  exit (1);
+}
+
+int
+main ()
+{
+  int i;
+
+  for (i = 0; i < sizeof(ftable) / sizeof(ftable[0]); i++)
+    {
+      if (ftable[i] < 256)
+	{
+	  if (frac_char (i+1) != ftable[i])
+	    error ("frac_char", i, (long long) frac_char (i+1));
+	}
+      if (ftable[i] < 65536)
+	{
+	  if (ftable[i] <= 32767 && frac_short (i+1) != ftable[i])
+	    error ("frac_short", i, (long long) frac_short (i+1));
+
+	  if (frac_ushort (i+1) != ftable[i])
+	    error ("frac_ushort", i, (long long) frac_ushort (i+1));
+	}
+      if (ftable[i] < 65536*65536)
+	{
+	  if (ftable[i] <= 0x7ffffffffL && frac_long (i+1) != ftable[i])
+	    error ("frac_long", i, (long long) frac_long (i+1));
+
+	  if (frac_ulong (i+1) != ftable[i])
+	    error ("frac_ulong", i, (long long) frac_ulong (i+1));
+	}
+      if (frac_longlong (i+1) != ftable[i])
+	error ("frac_longlong", i, frac_longlong (i+1));
+
+      if (frac_ulonglong (i+1) != ftable[i])
+	error ("frac_ulonglong", i, frac_ulonglong (i+1));      
+    }
+  return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/negqi.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/negqi.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/negqi.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/negqi.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,64 @@
+signed char value;
+
+signed char values[] = {
+  0, 1, 2, 3, 5, 7, 9, 16, 127, 128
+};
+
+signed char expect[] = {
+  0, -1, -2, -3, -5, -7, -9, -16, -127, 128
+};
+
+void
+negqi_global ()
+{
+  value = - value;
+}
+
+void
+negqi_ptr (signed char* p)
+{
+  *p = - *p;
+}
+
+signed char
+negqi_return (signed char v)
+{
+  return -v;
+}
+
+int
+main()
+{
+  unsigned i;
+  signed char c;
+  
+  for (i = 0; i < sizeof(values) / sizeof(values[0]); i++)
+    {
+      value = values[i];
+      negqi_global ();
+      if (value != expect[i])
+        abort ();
+
+      negqi_global ();
+      if (value != values[i])
+        abort ();
+
+      c = value;
+      negqi_ptr (&c);
+      if (c != expect[i])
+        abort ();
+
+      negqi_ptr (&c);
+      if (c != values[i])
+        abort ();
+
+      c = negqi_return (c);
+      if (c != expect[i])
+        abort ();
+
+      c = negqi_return (c);
+      if (c != values[i])
+        abort ();
+    }
+  exit (0);
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/orqi.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/orqi.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/orqi.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/orqi.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,52 @@
+signed char value;
+
+signed char values[] = {
+  0,  1,  2,  3,  5,  7, 9, 16, 127, 128
+};
+
+signed char expect[] = {
+ 12, 13, 14, 15, 13, 15, 13, 28, 127, 140
+};
+
+void
+orqi_global ()
+{
+  value |= 12;
+}
+
+void
+orqi_ptr (signed char* p)
+{
+  *p |= 12;
+}
+
+signed char
+orqi_return (signed char v)
+{
+  return v | 12;
+}
+
+int
+main()
+{
+  unsigned i;
+  signed char c;
+  
+  for (i = 0; i < sizeof(values) / sizeof(values[0]); i++)
+    {
+      value = values[i];
+      orqi_global ();
+      if (value != expect[i])
+        abort ();
+
+      c = values[i];
+      orqi_ptr (&c);
+      if (c != expect[i])
+        abort ();
+
+      c = orqi_return (values[i]);
+      if (c != expect[i])
+        abort ();
+    }
+  exit (0);
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/pr-11741.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/pr-11741.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/pr-11741.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/pr-11741.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,59 @@
+typedef short bsdstuff_size_t;
+char *strncpy(char *dst, const char *src, bsdstuff_size_t n)
+{
+  // printf("src=%s\r\n", src);
+  // printf("size=%d", n);
+  if (n != 0) {
+    char *d = dst;
+    const char *s = src;
+    
+    do {
+      if ((*d++ = *s++) == 0) {
+        /* NUL pad the remaining n-1 bytes */
+        while (--n != 0)
+          *d++ = 0;
+        break;
+      }
+    } while (--n != 0);
+  }
+  //printf("dst=%s\r\n", dst);
+  
+  return (dst);
+  
+}
+
+static const char* strings[] = {
+  "hello world",
+  "a",
+  "bb",
+  "0123456789012234568",
+  "asfasfsgdhtrhwrthrhwvdvegqeasdfasf",
+  0
+};
+
+int
+main ()
+{
+  char buf[64];
+  char *p;
+  int i;
+
+  for (i = 0; strings[i] != 0; i++)
+    {
+      memset (buf, 1, sizeof (buf));
+      if (buf[3] != 1 || buf[12] != 1 || buf[sizeof (buf) - 1] != 1)
+        abort ();
+
+      p = strncpy (buf, strings[i], sizeof (buf));
+      if (buf[sizeof (buf) - 1] != 0)
+        abort ();
+      if (p != buf)
+        abort ();
+
+      if (buf[0] != strings[i][0])
+        abort ();
+      if (strcmp (buf, strings[i]) != 0)
+        abort ();
+    }
+  return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/pr-12243.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/pr-12243.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/pr-12243.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/pr-12243.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,27 @@
+static unsigned char spi_test1[256];
+
+void fnTest(void)
+{
+  unsigned short i;
+   
+  for (i = 0; i < sizeof(spi_test1); i++) 
+    {
+      spi_test1[i] = (unsigned char)i;
+    }
+}
+
+void main(void)
+{
+  fnTest ();
+  
+  if (spi_test1[0] != 0)
+    exit (1);
+
+  if (spi_test1[1] != 1)
+    exit (2);
+
+  if (spi_test1[10] != 10)
+    exit (3);
+
+  exit (0);
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/pr-12297.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/pr-12297.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/pr-12297.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/pr-12297.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,50 @@
+unsigned long lsqrt (unsigned long x)
+{
+	if (x <= 1)
+		return x;
+
+	/* If 'x' is small enough, use 16-bit integers.  */
+	if ((x & 0xFFFF0000L) == 0)
+	{
+		unsigned short v0, x0, q0, x1;
+
+		v0 = (unsigned short) (x);
+		x0 = v0 / 2;
+		while (1)
+		{
+			q0 = v0 / x0;
+			x1 = (x0 + q0) / 2;
+			if (q0 >= x0)
+				break;
+			x0 = x1;
+		}
+		return (unsigned long) x1;
+	}
+	else
+	{
+		unsigned long v0, q0, x1;
+
+		v0 = x;
+		x = x / 2;
+		while (1)
+		{
+			q0 = v0 / x;
+			x1 = (x + q0) / 2;
+			if (q0 >= x)
+				break;
+			x = x1;
+		}
+		return x1;
+	}
+}
+
+int main ()
+{
+  unsigned long result = lsqrt (40);
+  if (result != 6)
+    exit (1);
+
+  return 0;
+}
+
+
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/pr-13917.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/pr-13917.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/pr-13917.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/pr-13917.c	Sat Nov  5 22:12:59 2005
@@ -0,0 +1,50 @@
+#include <string.h>
+
+void ltoa(char *buf, unsigned long i, int base);
+
+void ltoa(char *buf, unsigned long i, int base)
+{
+  char *s;
+#define LEN 25
+  int rem;
+  char rev[LEN+1];
+
+  if (i == 0)
+    s = "0";
+  else
+    {
+      rev[LEN] = 0;
+      s = &rev[LEN];
+      while (i)
+        {
+          rem = i % base;
+          if (rem < 10)
+            *--s = rem + '0'; // >>>>>>>> Here appears the error.
+          else
+            if (base == 16)
+              *--s = "abcdef"[rem - 10];
+          i /= base;
+        }
+    }
+  strcpy(buf, s);
+}
+
+int main()
+{
+  char buf[32];
+
+  ltoa(buf, 0x123456, 10);
+  if (strcmp(buf, "1193046") != 0)
+    return 1;
+  
+  ltoa(buf, 0x2345678, 13);
+  if (strcmp(buf, "7870") != 0)
+    return 1;
+  
+  ltoa(buf, 0xabcdef0, 16);
+  if (strcmp(buf, "abcdef0") != 0)
+    return 1;
+  
+  /* Also check that the strcmp detects strings not equal!  */
+  return strcmp(buf, "bcde") != 0 ? 0 : 1;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/pr-15493.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/pr-15493.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/pr-15493.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/pr-15493.c	Wed Jan 25 21:18:05 2006
@@ -0,0 +1,57 @@
+#ifdef mc68hc1x
+/* The softregs start at address 0.  The test needs to write
+   at 0x0 to verify that the 'mebi->dirX = 0' are fixed.
+   We use this padding scratch area to make sure the soft
+   registers do not start at 0. */
+char __attribute__((section(".page0"))) scratch[0x20] = { 0 };
+#endif
+
+typedef struct
+{
+   volatile unsigned char portA;
+   volatile unsigned char  portB;
+   volatile unsigned char  dirA;
+   volatile unsigned char  dirB;
+} MEBI_Regs;
+
+void ReadExternalBus( unsigned int addr )
+{
+   MEBI_Regs *mebi = (MEBI_Regs*)0;
+
+   // Write the address to the port A and B registers
+   mebi->portB = addr;
+   mebi->portA = addr>>8;
+
+   // Change ports A and B to inputs
+   mebi->dirA = 0;
+   mebi->dirB = 0;
+}
+
+void check(MEBI_Regs* p, unsigned char a, unsigned char b)
+{
+  if (p->portA != a)
+    abort();
+  if (p->portB != b)
+    abort();
+  if (p->dirA != 0)
+    abort();
+  if (p->dirB != 0)
+    abort();
+}
+
+int main( void )
+{
+#ifdef mc68hc1x
+  char* p = (char*) 0;
+  unsigned short i;
+  
+  for (i = 0x20; i > 0; i--)
+    *p++ = 0xaa;
+
+#endif
+  ReadExternalBus( 0x1000 );
+#ifdef mc68hc1x
+  check(0, 0x10, 0);
+#endif
+  return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/setjmp-test.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/setjmp-test.c
--- gcc-3.3.6/gcc/testsuite/gcc.c-torture/execute-scz/setjmp-test.c	Thu Jan  1 01:00:00 1970
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.c-torture/execute-scz/setjmp-test.c	Sat Nov  5 19:17:25 2005
@@ -0,0 +1,50 @@
+#include <stdio.h>
+#include <setjmp.h>
+
+jmp_buf jbuf;
+int jret;
+
+int
+fact (int n)
+{
+  if (n <= 1)
+    {
+      if (jret)
+        longjmp (jbuf, jret);
+      
+      return 1;
+    }
+  else
+    {
+      return fact (n - 1) * n;
+    }
+}
+
+int
+compute (int n)
+{
+  int result;
+
+  result = setjmp (jbuf);
+  if (result != 0)
+    return result;
+
+  result = fact (n);
+  return result * n;
+}
+
+int
+main ()
+{
+  int result;
+
+  result = compute (4);
+  if (result != 96)
+    abort ();
+  
+  jret = 23;
+  result = compute (4);
+  if (result != 23)
+    abort ();
+  return 0;
+}
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/20001009-1.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20001009-1.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/20001009-1.c	Fri Mar 15 06:36:37 2002
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20001009-1.c	Sat Nov  5 19:17:25 2005
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -fpic" } */
-/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* cris-*-aout* mmix-*-* } 0 } */
+/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* cris-*-aout* mmix-*-* m6811-*-* m6812-*-* } 0 } */
 
 extern void foo (void *a, double x, double y);
 void
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/20010912-1.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20010912-1.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/20010912-1.c	Fri Mar 15 06:36:37 2002
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20010912-1.c	Sat Nov  5 19:17:25 2005
@@ -1,6 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -fpic" } */
-/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* cris-*-aout* mmix-*-* } 0 } */
+/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* cris-*-aout* mmix-*-* m6811-*-* m6812-*-* } 0 } */
 
 extern void abort (void);
 extern void exit (int);
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/20020122-4.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20020122-4.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/20020122-4.c	Fri Mar 15 06:36:37 2002
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20020122-4.c	Sat Nov  5 19:17:25 2005
@@ -2,7 +2,7 @@
    (mem (lo_sum pic (symbol_ref))) within an asm at the right time.  */
 /* { dg-do compile } */
 /* { dg-options "-O2 -fpic" } */
-/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* cris-*-aout* mmix-*-* } 0 } */
+/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* cris-*-aout* mmix-*-* m6811-*-* m6812-*-* } 0 } */
 
 void foo()
 {
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/20020219-1.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20020219-1.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/20020219-1.c	Tue Oct 15 00:07:18 2002
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20020219-1.c	Sat Nov  5 19:17:25 2005
@@ -8,6 +8,7 @@
 /* { dg-do run } */
 /* { dg-options "-O2" } */
 /* { dg-options "-O2 -mdisable-indexing" { target hppa*-*-hpux* } } */
+/* { dg-options "-mshort" { target m6811-*-* m6812-*-* } } */
 
 /* Disable the test entirely for 16-bit targets.  */
 #if __INT_MAX__ > 32767
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/20020415-1.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20020415-1.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/20020415-1.c	Mon Apr 22 03:19:05 2002
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20020415-1.c	Sat Nov  5 19:17:25 2005
@@ -3,7 +3,7 @@
    ASM_SIMPLIFY_DWARF_ADDR hook.  */
 /* { dg-do compile } */
 /* { dg-options "-O2 -fpic -g" } */
-/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* mmix-*-* } 0 } */
+/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* mmix-*-* m6811-*-* m6812-*-* } 0 } */
 
 static inline char *
 bar (unsigned long x, char *y)
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/20020426-2.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20020426-2.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/20020426-2.c	Sun Apr 28 21:48:10 2002
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20020426-2.c	Sat Nov  5 19:17:25 2005
@@ -3,6 +3,7 @@
 /* { dg-do run } */
 /* { dg-options "-O2" } */
 /* { dg-options "-O2 -frename-registers -fomit-frame-pointer -fPIC -mcpu=i686" { target i?86-*-* } } */
+/* { dg-warning "not supported" "PIC unsupported" { target m6811-*-* m6812-*-* } 0 } */
 
 typedef struct
 {
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/20020430-1.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20020430-1.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/20020430-1.c	Fri Feb  7 05:00:04 2003
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20020430-1.c	Sat Nov  5 19:17:25 2005
@@ -6,6 +6,7 @@
 
 /* { dg-do compile } */
 /* { dg-options "-O2 -frename-registers -fpic" } */
+/* { dg-warning "not supported" "PIC unsupported" { target m6811-*-* m6812-*-* } 0 } */
 
 typedef unsigned long XID;
 typedef XID Window;
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/20021014-1.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20021014-1.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/20021014-1.c	Mon Oct 28 19:10:56 2002
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20021014-1.c	Sat Nov  5 19:17:25 2005
@@ -9,6 +9,7 @@
 /* Support for -p on irix relies on libprof1.a which doesn't appear to
    exist on any irix6 system currently posting testsuite results.  */
 /* { dg-error "libprof1.a" "Profiler support missing" { target mips*-*-irix* } 0 } */
+/* { dg-error "mcount" "Profiler support missing" { target m6811-*-* m6812-*-* } 0 } */
 
 extern void abort (void);
 extern void exit (int);
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/20021018-1.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20021018-1.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/20021018-1.c	Mon Oct 21 22:27:14 2002
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20021018-1.c	Sat Nov  5 19:17:25 2005
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -fpic" } */
+/* { dg-warning "not supported" "PIC unsupported" { target m6811-*-* m6812-*-* } 0 } */
 
 extern void abort (void);
 extern void exit (int);
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/20021023-1.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20021023-1.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/20021023-1.c	Wed Oct 23 23:20:08 2002
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20021023-1.c	Sat Nov  5 19:17:25 2005
@@ -2,6 +2,7 @@
    considered as local_symbolic_operand.  */
 /* { dg-do compile } */
 /* { dg-options "-O2 -fpic" } */
+/* { dg-warning "not supported" "PIC unsupported" { target m6811-*-* m6812-*-* } 0 } */
 
 typedef __builtin_va_list va_list;
 
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/20021029-1.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20021029-1.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/20021029-1.c	Thu Nov 14 08:56:54 2002
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20021029-1.c	Sat Nov  5 19:17:25 2005
@@ -2,6 +2,7 @@
    variables into writable sections.  */
 /* { dg-do compile } */
 /* { dg-options "-O2 -fpic" } */
+/* { dg-warning "not supported" "PIC unsupported" { target m6811-*-* m6812-*-* } 0 } */
 /* { dg-final { scan-assembler-not ".data.rel.ro.local" } } */
 
 int foo (int a)
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/20021116-1.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20021116-1.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/20021116-1.c	Sat Nov 16 21:04:40 2002
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20021116-1.c	Sat Nov  5 19:17:25 2005
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -fpic" } */
-/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* cris-*-aout* mmix-*-* } 0 } */
+/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* cris-*-aout* mmix-*-* m6811-*-* m6812-*-* } 0 } */
 
 void **
 foo (void **x, int y, void *z)
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/20030120-1.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20030120-1.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/20030120-1.c	Tue Jan 21 08:40:04 2003
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20030120-1.c	Sat Nov  5 19:17:25 2005
@@ -1,7 +1,7 @@
 /* PR 7154 */
 /* { dg-do compile } */
 /* { dg-options "-O -fpic" } */
-/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* mmix-*-* } 0 } */
+/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* mmix-*-* m6811-*-* m6812-*-* } 0 } */
 
 const int x[1]={ 1 };
 void foo(int i, int *p)
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/20030213-1.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20030213-1.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/20030213-1.c	Fri Feb 14 10:21:30 2003
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20030213-1.c	Sat Nov  5 19:17:25 2005
@@ -1,7 +1,7 @@
 /* Testcase for http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01017.html */
 /* { dg-do link } */
 /* { dg-options "-O -fpic" } */
-/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* cris-*-aout* mmix-*-* } 0 } */
+/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* cris-*-aout* mmix-*-* m6811-*-* m6812-*-* } 0 } */
 
 int *g;
 
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/20030225-1.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20030225-1.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/20030225-1.c	Wed Feb 26 00:20:14 2003
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/20030225-1.c	Sat Nov  5 19:17:25 2005
@@ -5,7 +5,7 @@
    and Benjamin Herrenschmidt <benh@kernel.crashing.org>.  */
 /* { dg-do run } */
 /* { dg-options "-O2 -fPIC" } */
-/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* mmix-*-* } 0 } */
+/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* mmix-*-* m6811-*-* m6812-*-* } 0 } */
 
 
 extern void exit (int);
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/inline-2.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/inline-2.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/inline-2.c	Wed Oct  2 10:26:39 2002
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/inline-2.c	Sat Nov  5 19:17:25 2005
@@ -2,7 +2,7 @@
    it has been deferred.  */
 /* { dg-do compile } */
 /* { dg-options "-O3 -finline-limit=0 -fpic" } */
-/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* cris-*-aout* mmix-*-* } 0 } */
+/* { dg-warning "not supported" "PIC unsupported" { target cris-*-elf* cris-*-aout* mmix-*-* m6811-*-* m6812-*-* } 0 } */
 
 static int foo(void)
 {
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/nest.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/nest.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/nest.c	Sat Aug  9 08:51:11 2003
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/nest.c	Sat Nov  5 19:17:25 2005
@@ -5,6 +5,7 @@
 /* Support for -pg on irix relies on gcrt1.o which doesn't exist yet.
    See: http://gcc.gnu.org/ml/gcc/2002-10/msg00169.html */
 /* { dg-error "gcrt1.o" "Profiler support missing" { target mips*-*-irix* } 0 } */
+/* { dg-error "mcount" "Profiler support missing" { target m6811-*-* m6812-*-* } 0 } */
 /* { dg-error "-pg not supported" "Profiler support missing" { target *-*-sco3.2v5* } 0 } */
 
 long foo (long x)
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.dg/noncompile/20020213-1.c gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/noncompile/20020213-1.c
--- gcc-3.3.6/gcc/testsuite/gcc.dg/noncompile/20020213-1.c	Thu Feb 14 11:22:53 2002
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.dg/noncompile/20020213-1.c	Sat Nov  5 19:17:25 2005
@@ -3,8 +3,8 @@
 typedef struct { int i; } FILE;
 typedef __SIZE_TYPE__ size_t;
 int fputs (const char *, FILE *);
-void bzero (void *, size_t);
-int bcmp (const void *, const void *, size_t);
+void bzero (void *, size_t); /* { dg-warning "conflicting types for built-in" { target m6811-*-* } } */
+int bcmp (const void *, const void *, size_t); /* { dg-warning "conflicting types for built-in" { target m6811-*-* } } */
 
 char buf[32];
 FILE *f;
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/testsuite/gcc.misc-tests/bprob.exp gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.misc-tests/bprob.exp
--- gcc-3.3.6/gcc/testsuite/gcc.misc-tests/bprob.exp	Mon Oct 21 22:21:00 2002
+++ gcc-3.3.6-m68hc1x/gcc/testsuite/gcc.misc-tests/bprob.exp	Sat Nov  5 19:17:25 2005
@@ -1,4 +1,4 @@
-#   Copyright (C) 2001, 2002 Free Software Foundation, Inc.
+#   Copyright (C) 2001, 2002, 2003 Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -20,7 +20,9 @@
 # Some targets don't have any implementation of __bb_init_func or are
 # missing other needed machinery.
 if { [istarget mmix-*-*]
-     || [istarget cris-*-*] } {
+     || [istarget cris-*-*]
+     || [istarget m6811-*-*]
+     || [istarget m6812-*-*] } {
     return
 }
 
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/toplev.c gcc-3.3.6-m68hc1x/gcc/toplev.c
--- gcc-3.3.6/gcc/toplev.c	Fri Mar  5 18:55:51 2004
+++ gcc-3.3.6-m68hc1x/gcc/toplev.c	Sat Nov  5 19:17:25 2005
@@ -3101,7 +3101,10 @@ rest_of_compilation (decl)
 	setjmp_args_warning ();
     }
 
-  if (optimize)
+  /* SCz: PR target/5854, this is initializing registers by inserting
+     instructions before the prologue instructions that save incomming
+     registers.  */
+  if (optimize && 0)
     {
       if (!flag_new_regalloc && initialize_uninitialized_subregs ())
 	{
diff --exclude-from=exclude.lst -Nrup gcc-3.3.6/gcc/version.c gcc-3.3.6-m68hc1x/gcc/version.c
--- gcc-3.3.6/gcc/version.c	Tue May  3 12:56:18 2005
+++ gcc-3.3.6-m68hc1x/gcc/version.c	Sun Jan 22 21:17:06 2006
@@ -6,7 +6,7 @@
    please modify this string to indicate that, e.g. by putting your
    organization's name in parentheses at the end of the string.  */
 
-const char version_string[] = "3.3.6";
+const char version_string[] = "3.3.6-m68hc1x-20060122";
 
 /* This is the location of the online document giving instructions for
    reporting bugs.  If you distribute a modified version of GCC,