1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
|
# frv testcase for bcralr $ccond
# mach: all
.include "testutils.inc"
start
.global bcralr
bcralr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr ok1,lr
set_icc 0x0 0
bcralr 0
fail
ok1:
set_spr_addr ok2,lr
set_icc 0x1 1
bcralr 0
fail
ok2:
set_spr_addr ok3,lr
set_icc 0x2 2
bcralr 0
fail
ok3:
set_spr_addr ok4,lr
set_icc 0x3 3
bcralr 0
fail
ok4:
set_spr_addr ok5,lr
set_icc 0x4 0
bcralr 0
fail
ok5:
set_spr_addr ok6,lr
set_icc 0x5 1
bcralr 0
fail
ok6:
set_spr_addr ok7,lr
set_icc 0x6 2
bcralr 0
fail
ok7:
set_spr_addr ok8,lr
set_icc 0x7 3
bcralr 0
fail
ok8:
set_spr_addr ok9,lr
set_icc 0x8 0
bcralr 0
fail
ok9:
set_spr_addr oka,lr
set_icc 0x9 1
bcralr 0
fail
oka:
set_spr_addr okb,lr
set_icc 0xa 2
bcralr 0
fail
okb:
set_spr_addr okc,lr
set_icc 0xb 3
bcralr 0
fail
okc:
set_spr_addr okd,lr
set_icc 0xc 0
bcralr 0
fail
okd:
set_spr_addr oke,lr
set_icc 0xd 1
bcralr 0
fail
oke:
set_spr_addr okf,lr
set_icc 0xe 2
bcralr 0
fail
okf:
set_spr_addr okg,lr
set_icc 0xf 3
bcralr 0
fail
okg:
; ccond is true
set_spr_immed 1,lcr
set_spr_addr okh,lr
set_icc 0x0 0
bcralr 1
fail
okh:
set_spr_immed 1,lcr
set_spr_addr oki,lr
set_icc 0x1 1
bcralr 1
fail
oki:
set_spr_immed 1,lcr
set_spr_addr okj,lr
set_icc 0x2 2
bcralr 1
fail
okj:
set_spr_immed 1,lcr
set_spr_addr okk,lr
set_icc 0x3 3
bcralr 1
fail
okk:
set_spr_immed 1,lcr
set_spr_addr okl,lr
set_icc 0x4 0
bcralr 1
fail
okl:
set_spr_immed 1,lcr
set_spr_addr okm,lr
set_icc 0x5 1
bcralr 1
fail
okm:
set_spr_immed 1,lcr
set_spr_addr okn,lr
set_icc 0x6 2
bcralr 1
fail
okn:
set_spr_immed 1,lcr
set_spr_addr oko,lr
set_icc 0x7 3
bcralr 1
fail
oko:
set_spr_immed 1,lcr
set_spr_addr okp,lr
set_icc 0x8 0
bcralr 1
fail
okp:
set_spr_immed 1,lcr
set_spr_addr okq,lr
set_icc 0x9 1
bcralr 1
fail
okq:
set_spr_immed 1,lcr
set_spr_addr okr,lr
set_icc 0xa 2
bcralr 1
fail
okr:
set_spr_immed 1,lcr
set_spr_addr oks,lr
set_icc 0xb 3
bcralr 1
fail
oks:
set_spr_immed 1,lcr
set_spr_addr okt,lr
set_icc 0xc 0
bcralr 1
fail
okt:
set_spr_immed 1,lcr
set_spr_addr oku,lr
set_icc 0xd 1
bcralr 1
fail
oku:
set_spr_immed 1,lcr
set_spr_addr okv,lr
set_icc 0xe 2
bcralr 1
fail
okv:
set_spr_immed 1,lcr
set_spr_addr okw,lr
set_icc 0xf 3
bcralr 1
fail
okw:
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcralr 1
set_icc 0x1 1
bcralr 1
set_icc 0x2 2
bcralr 1
set_icc 0x3 3
bcralr 1
set_icc 0x4 0
bcralr 1
set_icc 0x5 1
bcralr 1
set_icc 0x6 2
bcralr 1
set_icc 0x7 3
bcralr 1
set_icc 0x8 0
bcralr 1
set_icc 0x9 1
bcralr 1
set_icc 0xa 2
bcralr 1
set_icc 0xb 3
bcralr 1
set_icc 0xc 0
bcralr 1
set_icc 0xd 1
bcralr 1
set_icc 0xe 2
bcralr 1
set_icc 0xf 3
bcralr 1
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcralr 0
set_spr_immed 1,lcr
set_icc 0x1 1
bcralr 0
set_spr_immed 1,lcr
set_icc 0x2 2
bcralr 0
set_spr_immed 1,lcr
set_icc 0x3 3
bcralr 0
set_spr_immed 1,lcr
set_icc 0x4 0
bcralr 0
set_spr_immed 1,lcr
set_icc 0x5 1
bcralr 0
set_spr_immed 1,lcr
set_icc 0x6 2
bcralr 0
set_spr_immed 1,lcr
set_icc 0x7 3
bcralr 0
set_spr_immed 1,lcr
set_icc 0x8 0
bcralr 0
set_spr_immed 1,lcr
set_icc 0x9 1
bcralr 0
set_spr_immed 1,lcr
set_icc 0xa 2
bcralr 0
set_spr_immed 1,lcr
set_icc 0xb 3
bcralr 0
set_spr_immed 1,lcr
set_icc 0xc 0
bcralr 0
set_spr_immed 1,lcr
set_icc 0xd 1
bcralr 0
set_spr_immed 1,lcr
set_icc 0xe 2
bcralr 0
set_spr_immed 1,lcr
set_icc 0xf 3
bcralr 0
pass
bad:
fail
|
