1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
|
# frv testcase for mcmpsh $FRi,$FRj,$FCCk
# mach: all
.include "testutils.inc"
start
.global mcmpsh
mcmpsh:
set_fr_iimmed 0x7fff,0x7fff,fr10
set_fr_iimmed 0x7fff,0x7fff,fr11
set_fcc 0x7,0 ; Set mask opposite of expected
set_fcc 0x7,1 ; Set mask opposite of expected
mcmpsh fr10,fr11,fcc0
test_fcc 0x8,0
test_fcc 0x8,1
set_fr_iimmed 0x7fff,0x7fff,fr10
set_fr_iimmed 0x7fff,0x8000,fr11
set_fcc 0x7,0 ; Set mask opposite of expected
set_fcc 0xd,1 ; Set mask opposite of expected
mcmpsh fr10,fr11,fcc0
test_fcc 0x8,0
test_fcc 0x2,1
set_fr_iimmed 0x7fff,0x7fff,fr10
set_fr_iimmed 0x8000,0x7fff,fr11
set_fcc 0xd,0 ; Set mask opposite of expected
set_fcc 0x7,1 ; Set mask opposite of expected
mcmpsh fr10,fr11,fcc0
test_fcc 0x2,0
test_fcc 0x8,1
set_fr_iimmed 0x7fff,0x7fff,fr10
set_fr_iimmed 0x8000,0x8000,fr11
set_fcc 0xd,0 ; Set mask opposite of expected
set_fcc 0xd,1 ; Set mask opposite of expected
mcmpsh fr10,fr11,fcc0
test_fcc 0x2,0
test_fcc 0x2,1
set_fr_iimmed 0x7fff,0x8000,fr10
set_fr_iimmed 0x7fff,0x7fff,fr11
set_fcc 0x7,0 ; Set mask opposite of expected
set_fcc 0xb,1 ; Set mask opposite of expected
mcmpsh fr10,fr11,fcc0
test_fcc 0x8,0
test_fcc 0x4,1
set_fr_iimmed 0x7fff,0x8000,fr10
set_fr_iimmed 0x7fff,0x8000,fr11
set_fcc 0x7,0 ; Set mask opposite of expected
set_fcc 0x7,1 ; Set mask opposite of expected
mcmpsh fr10,fr11,fcc0
test_fcc 0x8,0
test_fcc 0x8,1
set_fr_iimmed 0x7fff,0x8000,fr10
set_fr_iimmed 0x8000,0x7fff,fr11
set_fcc 0xd,0 ; Set mask opposite of expected
set_fcc 0xb,1 ; Set mask opposite of expected
mcmpsh fr10,fr11,fcc0
test_fcc 0x2,0
test_fcc 0x4,1
set_fr_iimmed 0x7fff,0x8000,fr10
set_fr_iimmed 0x8000,0x8000,fr11
set_fcc 0xd,0 ; Set mask opposite of expected
set_fcc 0x7,1 ; Set mask opposite of expected
mcmpsh fr10,fr11,fcc0
test_fcc 0x2,0
test_fcc 0x8,1
set_fr_iimmed 0x8000,0x7fff,fr10
set_fr_iimmed 0x7fff,0x7fff,fr11
set_fcc 0xb,0 ; Set mask opposite of expected
set_fcc 0x7,1 ; Set mask opposite of expected
mcmpsh fr10,fr11,fcc0
test_fcc 0x4,0
test_fcc 0x8,1
set_fr_iimmed 0x8000,0x7fff,fr10
set_fr_iimmed 0x7fff,0x8000,fr11
set_fcc 0xb,0 ; Set mask opposite of expected
set_fcc 0xd,1 ; Set mask opposite of expected
mcmpsh fr10,fr11,fcc0
test_fcc 0x4,0
test_fcc 0x2,1
set_fr_iimmed 0x8000,0x7fff,fr10
set_fr_iimmed 0x8000,0x7fff,fr11
set_fcc 0x7,0 ; Set mask opposite of expected
set_fcc 0x7,1 ; Set mask opposite of expected
mcmpsh fr10,fr11,fcc0
test_fcc 0x8,0
test_fcc 0x8,1
set_fr_iimmed 0x8000,0x7fff,fr10
set_fr_iimmed 0x8000,0x8000,fr11
set_fcc 0x7,0 ; Set mask opposite of expected
set_fcc 0xd,1 ; Set mask opposite of expected
mcmpsh fr10,fr11,fcc0
test_fcc 0x8,0
test_fcc 0x2,1
set_fr_iimmed 0x8000,0x8000,fr10
set_fr_iimmed 0x7fff,0x7fff,fr11
set_fcc 0xb,0 ; Set mask opposite of expected
set_fcc 0xb,1 ; Set mask opposite of expected
mcmpsh fr10,fr11,fcc0
test_fcc 0x4,0
test_fcc 0x4,1
set_fr_iimmed 0x8000,0x8000,fr10
set_fr_iimmed 0x7fff,0x8000,fr11
set_fcc 0xb,0 ; Set mask opposite of expected
set_fcc 0x7,1 ; Set mask opposite of expected
mcmpsh fr10,fr11,fcc0
test_fcc 0x4,0
test_fcc 0x8,1
set_fr_iimmed 0x8000,0x8000,fr10
set_fr_iimmed 0x8000,0x7fff,fr11
set_fcc 0x7,0 ; Set mask opposite of expected
set_fcc 0xb,1 ; Set mask opposite of expected
mcmpsh fr10,fr11,fcc0
test_fcc 0x8,0
test_fcc 0x4,1
set_fr_iimmed 0x8000,0x8000,fr10
set_fr_iimmed 0x8000,0x8000,fr11
set_fcc 0x7,0 ; Set mask opposite of expected
set_fcc 0x7,1 ; Set mask opposite of expected
mcmpsh fr10,fr11,fcc0
test_fcc 0x8,0
test_fcc 0x8,1
pass
|
