1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
|
# Intel(r) Wireless MMX(tm) technology testcase for WADD
# mach: xscale
# as: -mcpu=xscale+iwmmxt
.include "testutils.inc"
start
.global wadd
wadd:
# Enable access to CoProcessors 0 & 1 before
# we attempt these instructions.
mvi_h_gr r1, 3
mcr p15, 0, r1, cr15, cr1, 0
# Test UnSaturated Byte Addition
mvi_h_gr r0, 0x12345678
mvi_h_gr r1, 0x9abcde00
mvi_h_gr r2, 0x11111111
mvi_h_gr r3, 0x11111111
mvi_h_gr r4, 0
mvi_h_gr r5, 0
tmcrr wr0, r0, r1
tmcrr wr1, r2, r3
tmcrr wr2, r4, r5
waddb wr2, wr0, wr1
tmrrc r0, r1, wr0
tmrrc r2, r3, wr1
tmrrc r4, r5, wr2
test_h_gr r0, 0x12345678
test_h_gr r1, 0x9abcde00
test_h_gr r2, 0x11111111
test_h_gr r3, 0x11111111
test_h_gr r4, 0x23456789
test_h_gr r5, 0xabcdef11
# Test Unsigned Saturated Byte Addition
mvi_h_gr r0, 0x12345678
mvi_h_gr r1, 0x9abcde00
mvi_h_gr r2, 0x11111111
mvi_h_gr r3, 0x11111111
mvi_h_gr r4, 0
mvi_h_gr r5, 0
tmcrr wr0, r0, r1
tmcrr wr1, r2, r3
tmcrr wr2, r4, r5
waddbus wr2, wr0, wr1
tmrrc r0, r1, wr0
tmrrc r2, r3, wr1
tmrrc r4, r5, wr2
test_h_gr r0, 0x12345678
test_h_gr r1, 0x9abcde00
test_h_gr r2, 0x11111111
test_h_gr r3, 0x11111111
test_h_gr r4, 0x23456789
test_h_gr r5, 0xabcdef11
# Test Signed Saturated Byte Addition
mvi_h_gr r0, 0x12345678
mvi_h_gr r1, 0x9abcde00
mvi_h_gr r2, 0x11111111
mvi_h_gr r3, 0x11111111
mvi_h_gr r4, 0
mvi_h_gr r5, 0
tmcrr wr0, r0, r1
tmcrr wr1, r2, r3
tmcrr wr2, r4, r5
waddbss wr2, wr0, wr1
tmrrc r0, r1, wr0
tmrrc r2, r3, wr1
tmrrc r4, r5, wr2
test_h_gr r0, 0x12345678
test_h_gr r1, 0x9abcde00
test_h_gr r2, 0x11111111
test_h_gr r3, 0x11111111
test_h_gr r4, 0x2345677f
test_h_gr r5, 0xabcdef11
# Test UnSaturated Halfword Addition
mvi_h_gr r0, 0x12345678
mvi_h_gr r1, 0x9abcde00
mvi_h_gr r2, 0x11111111
mvi_h_gr r3, 0x11111111
mvi_h_gr r4, 0
mvi_h_gr r5, 0
tmcrr wr0, r0, r1
tmcrr wr1, r2, r3
tmcrr wr2, r4, r5
waddh wr2, wr0, wr1
tmrrc r0, r1, wr0
tmrrc r2, r3, wr1
tmrrc r4, r5, wr2
test_h_gr r0, 0x12345678
test_h_gr r1, 0x9abcde00
test_h_gr r2, 0x11111111
test_h_gr r3, 0x11111111
test_h_gr r4, 0x23456789
test_h_gr r5, 0xabcdef11
# Test Unsigned Saturated Halfword Addition
mvi_h_gr r0, 0x12345678
mvi_h_gr r1, 0x9abcde00
mvi_h_gr r2, 0x11111111
mvi_h_gr r3, 0x11111111
mvi_h_gr r4, 0
mvi_h_gr r5, 0
tmcrr wr0, r0, r1
tmcrr wr1, r2, r3
tmcrr wr2, r4, r5
waddhus wr2, wr0, wr1
tmrrc r0, r1, wr0
tmrrc r2, r3, wr1
tmrrc r4, r5, wr2
test_h_gr r0, 0x12345678
test_h_gr r1, 0x9abcde00
test_h_gr r2, 0x11111111
test_h_gr r3, 0x11111111
test_h_gr r4, 0x23456789
test_h_gr r5, 0xabcdef11
# Test Signed Saturated Halfword Addition
mvi_h_gr r0, 0x12345678
mvi_h_gr r1, 0x9abcde00
mvi_h_gr r2, 0x11111111
mvi_h_gr r3, 0x11111111
mvi_h_gr r4, 0
mvi_h_gr r5, 0
tmcrr wr0, r0, r1
tmcrr wr1, r2, r3
tmcrr wr2, r4, r5
waddhss wr2, wr0, wr1
tmrrc r0, r1, wr0
tmrrc r2, r3, wr1
tmrrc r4, r5, wr2
test_h_gr r0, 0x12345678
test_h_gr r1, 0x9abcde00
test_h_gr r2, 0x11111111
test_h_gr r3, 0x11111111
test_h_gr r4, 0x23456789
test_h_gr r5, 0xabcdef11
# Test UnSaturated Word Addition
mvi_h_gr r0, 0x12345678
mvi_h_gr r1, 0x9abcde00
mvi_h_gr r2, 0x11111111
mvi_h_gr r3, 0x11111111
mvi_h_gr r4, 0
mvi_h_gr r5, 0
tmcrr wr0, r0, r1
tmcrr wr1, r2, r3
tmcrr wr2, r4, r5
waddw wr2, wr0, wr1
tmrrc r0, r1, wr0
tmrrc r2, r3, wr1
tmrrc r4, r5, wr2
test_h_gr r0, 0x12345678
test_h_gr r1, 0x9abcde00
test_h_gr r2, 0x11111111
test_h_gr r3, 0x11111111
test_h_gr r4, 0x23456789
test_h_gr r5, 0xabcdef11
# Test Unsigned Saturated Word Addition
mvi_h_gr r0, 0x12345678
mvi_h_gr r1, 0x9abcde00
mvi_h_gr r2, 0x11111111
mvi_h_gr r3, 0x11111111
mvi_h_gr r4, 0
mvi_h_gr r5, 0
tmcrr wr0, r0, r1
tmcrr wr1, r2, r3
tmcrr wr2, r4, r5
waddwus wr2, wr0, wr1
tmrrc r0, r1, wr0
tmrrc r2, r3, wr1
tmrrc r4, r5, wr2
test_h_gr r0, 0x12345678
test_h_gr r1, 0x9abcde00
test_h_gr r2, 0x11111111
test_h_gr r3, 0x11111111
test_h_gr r4, 0x23456789
test_h_gr r5, 0xabcdef11
# Test Signed Saturated Word Addition
mvi_h_gr r0, 0x12345678
mvi_h_gr r1, 0x9abcde00
mvi_h_gr r2, 0x11111111
mvi_h_gr r3, 0x11111111
mvi_h_gr r4, 0
mvi_h_gr r5, 0
tmcrr wr0, r0, r1
tmcrr wr1, r2, r3
tmcrr wr2, r4, r5
waddwss wr2, wr0, wr1
tmrrc r0, r1, wr0
tmrrc r2, r3, wr1
tmrrc r4, r5, wr2
test_h_gr r0, 0x12345678
test_h_gr r1, 0x9abcde00
test_h_gr r2, 0x11111111
test_h_gr r3, 0x11111111
test_h_gr r4, 0x23456789
test_h_gr r5, 0xabcdef11
pass
|
