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# frv testcase for fcblglr $FCCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global fcblglr
fcblglr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_fcc 0x0 0
fcblglr fcc0,0,0
set_spr_addr bad,lr
set_fcc 0x1 1
fcblglr fcc1,0,1
set_spr_addr ok3,lr
set_fcc 0x2 2
fcblglr fcc2,0,2
fail
ok3:
set_spr_addr ok4,lr
set_fcc 0x3 3
fcblglr fcc3,0,3
fail
ok4:
set_spr_addr ok5,lr
set_fcc 0x4 0
fcblglr fcc0,0,0
fail
ok5:
set_spr_addr ok6,lr
set_fcc 0x5 1
fcblglr fcc1,0,1
fail
ok6:
set_spr_addr ok7,lr
set_fcc 0x6 2
fcblglr fcc2,0,2
fail
ok7:
set_spr_addr ok8,lr
set_fcc 0x7 3
fcblglr fcc3,0,3
fail
ok8:
set_spr_addr bad,lr
set_fcc 0x8 0
fcblglr fcc0,0,0
set_spr_addr bad,lr
set_fcc 0x9 1
fcblglr fcc1,0,1
set_spr_addr okb,lr
set_fcc 0xa 2
fcblglr fcc2,0,2
fail
okb:
set_spr_addr okc,lr
set_fcc 0xb 3
fcblglr fcc3,0,3
fail
okc:
set_spr_addr okd,lr
set_fcc 0xc 0
fcblglr fcc0,0,0
fail
okd:
set_spr_addr oke,lr
set_fcc 0xd 1
fcblglr fcc1,0,1
fail
oke:
set_spr_addr okf,lr
set_fcc 0xe 2
fcblglr fcc2,0,2
fail
okf:
set_spr_addr okg,lr
set_fcc 0xf 3
fcblglr fcc3,0,3
fail
okg:
; ccond is true
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_fcc 0x0 0
fcblglr fcc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_fcc 0x1 1
fcblglr fcc1,1,1
set_spr_immed 1,lcr
set_spr_addr okj,lr
set_fcc 0x2 2
fcblglr fcc2,1,2
fail
okj:
set_spr_immed 1,lcr
set_spr_addr okk,lr
set_fcc 0x3 3
fcblglr fcc3,1,3
fail
okk:
set_spr_immed 1,lcr
set_spr_addr okl,lr
set_fcc 0x4 0
fcblglr fcc0,1,0
fail
okl:
set_spr_immed 1,lcr
set_spr_addr okm,lr
set_fcc 0x5 1
fcblglr fcc1,1,1
fail
okm:
set_spr_immed 1,lcr
set_spr_addr okn,lr
set_fcc 0x6 2
fcblglr fcc2,1,2
fail
okn:
set_spr_immed 1,lcr
set_spr_addr oko,lr
set_fcc 0x7 3
fcblglr fcc3,1,3
fail
oko:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_fcc 0x8 0
fcblglr fcc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_fcc 0x9 1
fcblglr fcc1,1,1
set_spr_immed 1,lcr
set_spr_addr okr,lr
set_fcc 0xa 2
fcblglr fcc2,1,2
fail
okr:
set_spr_immed 1,lcr
set_spr_addr oks,lr
set_fcc 0xb 3
fcblglr fcc3,1,3
fail
oks:
set_spr_immed 1,lcr
set_spr_addr okt,lr
set_fcc 0xc 0
fcblglr fcc0,1,0
fail
okt:
set_spr_immed 1,lcr
set_spr_addr oku,lr
set_fcc 0xd 1
fcblglr fcc1,1,1
fail
oku:
set_spr_immed 1,lcr
set_spr_addr okv,lr
set_fcc 0xe 2
fcblglr fcc2,1,2
fail
okv:
set_spr_immed 1,lcr
set_spr_addr okw,lr
set_fcc 0xf 3
fcblglr fcc3,1,3
fail
okw:
; ccond is false
set_spr_immed 128,lcr
set_fcc 0x0 0
fcblglr fcc0,1,0
set_fcc 0x1 1
fcblglr fcc1,1,1
set_fcc 0x2 2
fcblglr fcc2,1,2
set_fcc 0x3 3
fcblglr fcc3,1,3
set_fcc 0x4 0
fcblglr fcc0,1,0
set_fcc 0x5 1
fcblglr fcc1,1,1
set_fcc 0x6 2
fcblglr fcc2,1,2
set_fcc 0x7 3
fcblglr fcc3,1,3
set_fcc 0x8 0
fcblglr fcc0,1,0
set_fcc 0x9 1
fcblglr fcc1,1,1
set_fcc 0xa 2
fcblglr fcc2,1,2
set_fcc 0xb 3
fcblglr fcc3,1,3
set_fcc 0xc 0
fcblglr fcc0,1,0
set_fcc 0xd 1
fcblglr fcc1,1,1
set_fcc 0xe 2
fcblglr fcc2,1,2
set_fcc 0xf 3
fcblglr fcc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_fcc 0x0 0
fcblglr fcc0,0,0
set_spr_immed 1,lcr
set_fcc 0x1 1
fcblglr fcc1,0,1
set_spr_immed 1,lcr
set_fcc 0x2 2
fcblglr fcc2,0,2
set_spr_immed 1,lcr
set_fcc 0x3 3
fcblglr fcc3,0,3
set_spr_immed 1,lcr
set_fcc 0x4 0
fcblglr fcc0,0,0
set_spr_immed 1,lcr
set_fcc 0x5 1
fcblglr fcc1,0,1
set_spr_immed 1,lcr
set_fcc 0x6 2
fcblglr fcc2,0,2
set_spr_immed 1,lcr
set_fcc 0x7 3
fcblglr fcc3,0,3
set_spr_immed 1,lcr
set_fcc 0x8 0
fcblglr fcc0,0,0
set_spr_immed 1,lcr
set_fcc 0x9 1
fcblglr fcc1,0,1
set_spr_immed 1,lcr
set_fcc 0xa 2
fcblglr fcc2,0,2
set_spr_immed 1,lcr
set_fcc 0xb 3
fcblglr fcc3,0,3
set_spr_immed 1,lcr
set_fcc 0xc 0
fcblglr fcc0,0,0
set_spr_immed 1,lcr
set_fcc 0xd 1
fcblglr fcc1,0,1
set_spr_immed 1,lcr
set_fcc 0xe 2
fcblglr fcc2,0,2
set_spr_immed 1,lcr
set_fcc 0xf 3
fcblglr fcc3,0,3
pass
bad:
fail
|
