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# frv testcase for mp_exception
# mach: fr500 fr550 frv
# xerror:
# This program no longer assembles because the assembler
# now detects the unaligned registers. For this reason
# this test is now marked as "xerror" and prints the
# expected message "fail"
.include "testutils.inc"
start
.global mp_exception
mpx:
.if 1
fail
.else
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mcmpsh fr10,fr11,fcc1 ; mp_exception: cr-not-aligned
test_spr_bits 0x7000,12,3,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf is set
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mcmpsh.p fr10,fr11,fcc0 ; no exception
mcmpsh fr10,fr11,fcc2 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
mmulhs.p fr10,fr11,acc3 ; no exception
mmulhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned
test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mmulhu fr10,fr11,acc0 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mmulxhs.p fr10,fr11,acc3 ; no exception
mmulxhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned
test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mmulxhu fr10,fr11,acc0 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mmachs.p fr10,fr11,acc3 ; no exception
mmachs fr10,fr11,acc1 ; mp_exception: acc-not-aligned
test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mmachu fr10,fr11,acc0 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mqaddhss.p fr10,fr12,fr17 ; mp_exception: register-not-aligned
mqaddhss fr10,fr12,fr14 ; no exception
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mqaddhss.p fr10,fr12,fr14 ; no exception
mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mqaddhss.p fr19,fr12,fr14 ; mp_exception: register-not-aligned
mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqaddhss fr10,fr12,fr14 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mqmulhs.p fr10,fr11,acc3 ; no exception
mqmulhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned
test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqmulhu fr10,fr11,acc0 ; mp_exception: register_not_aligned
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqmulhu fr10,fr12,acc0 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mqmulxhs.p fr10,fr11,acc3 ; no exception
mqmulxhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned
test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqmulxhu fr10,fr11,acc0 ; mp_exception: register-not-aligned
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqmulxhu fr10,fr12,acc0 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mqmachs.p fr10,fr12,acc3 ; no exception
mqmachs fr10,fr12,acc2 ; mp_exception: acc-not-aligned
test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned
mqmachu fr10,fr12,acc0 ; no exception
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqmachu.p fr10,fr12,acc0 ; no exception
mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned
mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqmachu fr10,fr12,acc0 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mqcpxrs.p fr10,fr12,acc0 ; no exception
mqcpxrs fr10,fr12,acc1 ; mp_exception: acc-not-aligned
test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned
mqcpxru fr10,fr12,acc0 ; no exception
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqcpxru.p fr10,fr12,acc0 ; no exception
mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned
mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqcpxru fr10,fr12,acc0 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
pass
.endif
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