1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
|
# frv testcase for mmachs $GRi,$GRj,$ACCk
# mach: frv fr500 fr400
.include "testutils.inc"
start
.global mmachs
mmachs:
; Positive operands
set_fr_iimmed 2,3,fr7 ; multiply small numbers
set_fr_iimmed 3,2,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
set_fr_iimmed 0,1,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
set_fr_iimmed 2,1,fr7 ; multiply by 1
set_fr_iimmed 1,2,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
test_accg_immed 0,accg0
test_acc_immed 8,acc0
test_accg_immed 0,accg1
test_acc_immed 8,acc1
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
test_accg_immed 0,accg0
test_acc_limmed 0,0x8006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0,0x8006,acc1
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
test_accg_immed 0,accg0
test_acc_limmed 0x0001,0x0006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0001,0x0006,acc1
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
test_accg_immed 0,accg0
test_acc_limmed 0x4000,0x0007,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x4000,0x0007,acc1
; Mixed operands
set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
test_accg_immed 0,accg0
test_acc_limmed 0x4000,0x0001,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x4000,0x0001,acc1
set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0xffff,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0xffff,acc1
set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0xffff,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0xffff,acc1
set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0xbffd,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0xbffd,acc1
set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0x3ffd,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0x3ffd,acc1
set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xbffd,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xbffd,acc1
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xc003,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xc003,acc1
set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xc005,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xc005,acc1
set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
test_accg_immed 0,accg0
test_acc_immed 0x3ffec006,acc0
test_accg_immed 0,accg1
test_acc_immed 0x3ffec006,acc1
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
test_accg_immed 0,accg0
test_acc_immed 0x7ffec006,acc0
test_accg_immed 0,accg1
test_acc_immed 0x7ffec006,acc1
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr7
set_fr_iimmed 1,1,fr8
mmachs fr7,fr8,acc0
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0xffff,acc1
set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0xffff,acc1
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_fr_iimmed 0xffff,0,fr7
set_fr_iimmed 1,0xffff,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x80,accg0
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
set_fr_iimmed 0x0000,0x8000,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x80,accg0
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
pass
|
