File: m32r.cpu

package info (click to toggle)
gdb-doc 8.2.1-1
  • links: PTS, VCS
  • area: non-free
  • in suites: buster
  • size: 224,856 kB
  • sloc: ansic: 1,935,878; asm: 341,756; exp: 146,402; makefile: 56,625; sh: 23,696; cpp: 20,830; yacc: 12,914; perl: 5,331; ada: 4,977; python: 4,617; xml: 4,176; pascal: 3,134; lisp: 1,527; cs: 879; lex: 620; f90: 479; sed: 228; awk: 140; objc: 134; fortran: 43
file content (2437 lines) | stat: -rw-r--r-- 65,857 bytes parent folder | download | duplicates (31)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
; Renesas M32R CPU description.  -*- Scheme -*-
;
; Copyright 1998, 1999, 2000, 2001, 2003, 2007, 2009
; Free Software Foundation, Inc.
;
; Contributed by Red Hat Inc; developed under contract from Mitsubishi
; Electric Corporation.
;
; This file is part of the GNU Binutils.
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
; MA 02110-1301, USA.

(include "simplify.inc")

; FIXME: Delete sign extension of accumulator results.
; Sign extension is done when accumulator is read.

; define-arch must appear first

(define-arch
  (name m32r) ; name of cpu family
  (comment "Renesas M32R")
  (default-alignment aligned)
  (insn-lsb0? #f)
  (machs m32r m32rx m32r2)
  (isas m32r)
)

; Attributes.

; An attribute to describe which pipeline an insn runs in.
; O_OS is a special attribute for sll, sra, sla, slli, srai, slai.
; These instructions have O attribute for m32rx and OS attribute for m32r2.

(define-attr
  (for insn)
  (type enum)
  (name PIPE)
  (comment "parallel execution pipeline selection")
  (values NONE O S OS O_OS)
)

; A derived attribute that says which insns can be executed in parallel
; with others.  This is a required attribute for architectures with
; parallel execution.

(define-attr
  (for insn)
  (type enum)
  (name PARALLEL)
  (attrs META) ; do not define in any generated file for now
  (values NO YES)
  (default (if (eq-attr (current-insn) PIPE NONE) (symbol NO) (symbol YES)))
)

; Instruction set parameters.

(define-isa
  (name m32r)

  ; This is 32 because 16 bit insns always appear as pairs.
  ; ??? See if this can go away.  It's only used by the disassembler (right?)
  ; to decide how long an unknown insn is.  One value isn't sufficient (e.g. if
  ; on a 16 bit (and not 32 bit) boundary, will only want to advance pc by 16.)
  (default-insn-bitsize 32)

  ; Number of bytes of insn we can initially fetch.
  ; The M32R is tricky in that insns are either two 16-bit insns
  ; (executed sequentially or in parallel) or one 32-bit insn.
  ; So on one hand the base insn size is 16 bits, but on another it's 32.
  ; 32 is chosen because:
  ; - if the chip were ever bi-endian it is believed that the byte order would
  ;   be based on 32 bit quantities
  ; - 32 bit insns are always aligned on 32 bit boundaries
  ; - the pc will never stop on a 16 bit (and not 32 bit) boundary
  ;   [well actually it can, but there are no branches to such places]
  (base-insn-bitsize 32)

  ; Used in computing bit numbers.
  (default-insn-word-bitsize 32)

  ; The m32r fetches 2 insns at a time.
  (liw-insns 2)

  ; While the m32r can execute insns in parallel, the base mach can't
  ; (other than nop).  The base mach is greatly handicapped by this, but
  ; we still need to cleanly handle it.
  (parallel-insns 2)

  ; Initial bitnumbers to decode insns by.
  (decode-assist (0 1 2 3 8 9 10 11))

  ; Classification of instructions that fit in the various frames.
  ; wip, not currently used
  (insn-types (long ; name
	       31 ; length
	       (eq-attr (current-insn) LENGTH 31) ; matching insns
	       (0 1 2 7 8 9 10) ; decode-assist
	       )
	      (short
	       15
	       (eq-attr (current-insn) LENGTH 15) ; matching insns
	       (0 1 2 7 8 9 10)
	       )
	      )

  ; Instruction framing.
  ; Each m32r insn is either one 32 bit insn, two 16 bit insns executed
  ; serially (left->right), or two 16 bit insns executed parallelly.
  ; wip, not currently used
  (frame long32 ; name
	 ((long)) ; list of insns in frame, plus constraint
	 "$0"   ; assembler
	 (+ (1 1) (31 $0)) ; value
	 (sequence () (execute $0)) ; action
	 )
  (frame serial2x16
	 ((short)
	  (short))
	 "$0 -> $1"
	 (+ (1 0) (15 $0) (1 0) (15 $1))
	 (sequence ()
		   (execute $0)
		   (execute $1))
	 )
  (frame parallel2x16
	 ((short (eq-attr (current-insn) PIPE "O,BOTH"))
	  (short (eq-attr (current-insn) PIPE "S,BOTH")))
	 "$0 || $1"
	 (+ (1 0) (15 $0) (1 1) (15 $1))
	 (parallel ()
		   (execute $0)
		   (execute $1))
	 )
)

; Cpu family definitions.

; ??? define-cpu-family [and in general "cpu-family"] might be clearer than
; define-cpu.
; ??? Have define-arch provide defaults for architecture that define-cpu can
; then override [reduces duplication in define-cpu].
; ??? Another way to go is to delete cpu-families entirely and have one mach
; able to inherit things from another mach (would also need the ability to
; not only override specific inherited things but also disable some,
; e.g. if an insn wasn't supported).

(define-cpu
  ; cpu names must be distinct from the architecture name and machine names.
  ; The "b" suffix stands for "base" and is the convention.
  ; The "f" suffix stands for "family" and is the convention.
  (name m32rbf)
  (comment "Renesas M32R base family")
  (endian either)
  (word-bitsize 32)
  ; Override isa spec (??? keeps things simpler, though it was more true
  ; in the early days and not so much now).
  (parallel-insns 1)
)

(define-cpu
  (name m32rxf)
  (comment "Renesas M32Rx family")
  (endian either)
  (word-bitsize 32)
  ; Generated files have an "x" suffix.
  (file-transform "x")
)

(define-cpu
  (name m32r2f)
  (comment "Renesas M32R2 family")
  (endian either)
  (word-bitsize 32)
  ; Generated files have an "2" suffix.
  (file-transform "2")
)

(define-mach
  (name m32r)
  (comment "Generic M32R cpu")
  (cpu m32rbf)
)

(define-mach
  (name m32rx)
  (comment "M32RX cpu")
  (cpu m32rxf)
)

(define-mach
  (name m32r2)
  (comment "M32R2 cpu")
  (cpu m32r2f)
)

; Model descriptions.

; The meaning of this value is wip but at the moment it's intended to describe
; the implementation (i.e. what -mtune=foo does in sparc gcc).
;
; Notes while wip:
; - format of pipeline entry:
;   (pipeline name (stage1-name ...) (stage2-name ...) ...)
;   The contents of a stage description is wip.
; - each mach must have at least one model
; - the default model must be the first one
;- maybe have `retire' support update total cycle count to handle current
;  parallel insn cycle counting problems

(define-model
  (name m32r/d) (comment "m32r/d") (attrs)
  (mach m32r)

  ;(prefetch)
  ;(retire)

  (pipeline p-non-mem "" () ((fetch) (decode) (execute) (writeback)))
  (pipeline p-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))

  ; `state' is a list of variables for recording model state
  (state
   ; bit mask of h-gr registers, =1 means value being loaded from memory
   (h-gr UINT)
   )

  (unit u-exec "Execution Unit" ()
	1 1 ; issue done
	() ; state
	((sr INT -1) (dr INT -1)) ; inputs
	((dr INT -1)) ; outputs
	() ; profile action (default)
	)
  (unit u-cmp "Compare Unit" ()
	1 1 ; issue done
	() ; state
	((src1 INT -1) (src2 INT -1)) ; inputs
	() ; outputs
	() ; profile action (default)
	)
  (unit u-mac "Multiply/Accumulate Unit" ()
	1 1 ; issue done
	() ; state
	((src1 INT -1) (src2 INT -1)) ; inputs
	() ; outputs
	() ; profile action (default)
	)
  (unit u-cti "Branch Unit" ()
	1 1 ; issue done
	() ; state
	((sr INT -1)) ; inputs
	((pc)) ; outputs
	() ; profile action (default)
	)
  (unit u-load "Memory Load Unit" ()
	1 1 ; issue done
	() ; state
	((sr INT)
	 ;(ld-mem AI)
	 ) ; inputs
	((dr INT)) ; outputs
	() ; profile action (default)
	)
  (unit u-store "Memory Store Unit" ()
	1 1 ; issue done
	() ; state
	((src1 INT) (src2 INT)) ; inputs
	() ; ((st-mem AI)) ; outputs
	() ; profile action (default)
	)
)

(define-model
  (name test) (comment "test") (attrs)
  (mach m32r)
  (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
  (unit u-exec "Execution Unit" ()
	1 1 ; issue done
	() () () ())
)

; Each mach must have at least one model.

(define-model
  (name m32rx) (comment "m32rx") (attrs)
  (mach m32rx)

  ; ??? It's 6 stages but I forget the details right now.
  (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
  (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
  (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))

  (unit u-exec "Execution Unit" ()
	1 1 ; issue done
	() ; state
	((sr INT -1) (dr INT -1)) ; inputs
	((dr INT -1)) ; outputs
	() ; profile action (default)
	)
  (unit u-cmp "Compare Unit" ()
	1 1 ; issue done
	() ; state
	((src1 INT -1) (src2 INT -1)) ; inputs
	() ; outputs
	() ; profile action (default)
	)
  (unit u-mac "Multiply/Accumulate Unit" ()
	1 1 ; issue done
	() ; state
	((src1 INT -1) (src2 INT -1)) ; inputs
	() ; outputs
	() ; profile action (default)
	)
  (unit u-cti "Branch Unit" ()
	1 1 ; issue done
	() ; state
	((sr INT -1)) ; inputs
	((pc)) ; outputs
	() ; profile action (default)
	)
  (unit u-load "Memory Load Unit" ()
	1 1 ; issue done
	() ; state
	((sr INT)) ; inputs
	((dr INT)) ; outputs
	() ; profile action (default)
	)
  (unit u-store "Memory Store Unit" ()
	1 1 ; issue done
	() ; state
	((src1 INT) (src2 INT)) ; inputs
	() ; outputs
	() ; profile action (default)
	)
)

(define-model
  (name m32r2) (comment "m32r2") (attrs)
  (mach m32r2)

  ; ??? It's 6 stages but I forget the details right now.
  (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
  (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
  (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))

  (unit u-exec "Execution Unit" ()
	1 1 ; issue done
	() ; state
	((sr INT -1) (dr INT -1)) ; inputs
	((dr INT -1)) ; outputs
	() ; profile action (default)
	)
  (unit u-cmp "Compare Unit" ()
	1 1 ; issue done
	() ; state
	((src1 INT -1) (src2 INT -1)) ; inputs
	() ; outputs
	() ; profile action (default)
	)
  (unit u-mac "Multiply/Accumulate Unit" ()
	1 1 ; issue done
	() ; state
	((src1 INT -1) (src2 INT -1)) ; inputs
	() ; outputs
	() ; profile action (default)
	)
  (unit u-cti "Branch Unit" ()
	1 1 ; issue done
	() ; state
	((sr INT -1)) ; inputs
	((pc)) ; outputs
	() ; profile action (default)
	)
  (unit u-load "Memory Load Unit" ()
	1 1 ; issue done
	() ; state
	((sr INT)) ; inputs
	((dr INT)) ; outputs
	() ; profile action (default)
	)
  (unit u-store "Memory Store Unit" ()
	1 1 ; issue done
	() ; state
	((src1 INT) (src2 INT)) ; inputs
	() ; outputs
	() ; profile action (default)
	)
)

; The instruction fetch/execute cycle.
; This is split into two parts as sometimes more than one instruction is
; decoded at once.
; The `const SI' argument to decode/execute is used to distinguish
; multiple instructions processed at the same time (e.g. m32r).
;
; ??? This is wip, and not currently used.
; ??? Needs to be moved to define-isa.

; This is how to fetch and decode an instruction.

;(define-extract
;  (sequence VOID
;	    (if VOID (ne AI (and AI pc (const AI 3)) (const AI 0))
;		(sequence VOID
;			  (set-quiet USI (scratch UHI insn1) (ifetch UHI pc))
;			  (decode VOID pc (and UHI insn1 (const UHI #x7fff))
;				  (const SI 0)))
;		(sequence VOID
;			  (set-quiet USI (scratch USI insn) (ifetch USI pc))
;			  (if VOID (ne USI (and USI insn (const USI #x80000000))
;				     (const USI 0))
;			      (decode VOID pc (srl USI insn (const WI 16)) (const SI 0))
;			      (sequence VOID
;					; ??? parallel support
;					(decode VOID pc (srl USI insn (const WI 16))
;						(const SI 0))
;					(decode VOID (add AI pc (const AI 2))
;						(and USI insn (const WI #x7fff))
;						(const SI 1))))))
;	    )
;)

; This is how to execute a decoded instruction.

;(define-execute
;  (sequence VOID () ; () is empty option list
;	     ((AI new_pc))
;	     (set AI new_pc (execute: AI (const 0)) #:quiet)
;	     (set AI pc new_pc #:direct)
;	     )
;)

; FIXME: It might simplify things to separate the execute process from the
; one that updates the PC.

; Instruction fields.
;
; Attributes:
; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
; RESERVED: bits are not used to decode insn, must be all 0
; RELOC: there is a relocation associated with this field (experiment)

(define-attr
  (for ifield operand)
  (type boolean)
  (name RELOC)
  (comment "there is a reloc associated with this field (experiment)")
)

(dnf f-op1       "op1"                 () 0 4)
(dnf f-op2       "op2"                 () 8 4)
(dnf f-cond      "cond"                () 4 4)
(dnf f-r1        "r1"                  () 4 4)
(dnf f-r2        "r2"                  () 12 4)
(df f-simm8      "simm8"               () 8 8 INT #f #f)
(df f-simm16     "simm16"              () 16 16 INT #f #f)
(dnf f-shift-op2 "shift op2"           () 8 3)
(dnf f-uimm3     "uimm3"               () 5 3)
(dnf f-uimm4     "uimm4"               () 12 4)
(dnf f-uimm5     "uimm5"               () 11 5)
(dnf f-uimm8     "uimm8"               () 8 8)
(dnf f-uimm16    "uimm16"              () 16 16)
(dnf f-uimm24    "uimm24"              (ABS-ADDR RELOC) 8 24)
(dnf f-hi16      "high 16 bits"        (SIGN-OPT) 16 16)
(df f-disp8      "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT
    ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2)))
    ((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4)))))
(df f-disp16     "disp16"              (PCREL-ADDR RELOC) 16 16 INT
    ((value pc) (sra WI (sub WI value pc) (const 2)))
    ((value pc) (add WI (sll WI value (const 2)) pc)))
(df f-disp24     "disp24"              (PCREL-ADDR RELOC) 8 24 INT
    ((value pc) (sra WI (sub WI value pc) (const 2)))
    ((value pc) (add WI (sll WI value (const 2)) pc)))

(dnf f-op23      "op2.3"               ()  9 3)
(dnf f-op3       "op3"                 () 14 2)
(dnf f-acc       "acc"                 ()  8 1)
(dnf f-accs      "accs"                () 12 2)
(dnf f-accd      "accd"                ()  4 2)
(dnf f-bits67    "bits67"              ()  6 2)
(dnf f-bit4      "bit4"                ()  4 1)
(dnf f-bit14     "bit14"               () 14 1)

(define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2")
  (attrs)
  (start 15) (length 1)
  (encode (value pc) (sub WI value (const WI 1)))
  (decode (value pc) (add WI value (const WI 1)))
)

; Enums.

; insn-op1: bits 0-3
; FIXME: should use die macro or some such
(define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
  ("0" "1" "2" "3" "4" "5" "6" "7"
   "8" "9" "10" "11" "12" "13" "14" "15")
)

; insn-op2: bits 8-11
; FIXME: should use die macro or some such
(define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2
  ("0" "1" "2" "3" "4" "5" "6" "7"
   "8" "9" "10" "11" "12" "13" "14" "15")
)

; Hardware pieces.
; These entries list the elements of the raw hardware.
; They're also used to provide tables and other elements of the assembly
; language.

(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())

(dnh h-hi16 "high 16 bits" ()
     (immediate (UINT 16))
     () () ()
)

; These two aren't technically needed.
; They're here for illustration sake mostly.
; Plus they cause the value to be stored in the extraction buffers to only
; be 16 bits wide (vs 32 or 64).  Whoopie ding.  But it's fun.
(dnh h-slo16 "signed low 16 bits" ()
     (immediate (INT 16))
     () () ()
)
(dnh h-ulo16 "unsigned low 16 bits" ()
     (immediate (UINT 16))
     () () ()
)

(define-keyword
  (name gr-names)
  (print-name h-gr)
  (prefix "")
  (values (fp 13) (lr 14) (sp 15)
	  (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
	  (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15))
)

(define-hardware
  (name h-gr)
  (comment "general registers")
  (attrs PROFILE CACHE-ADDR)
  (type register WI (16))
  (indices extern-keyword gr-names)
)

(define-keyword
  (name cr-names)
  (print-name h-cr)
  (prefix "")
  (values (psw 0)   (cbr 1)   (spi 2)   (spu 3)
	  (bpc 6)   (bbpsw 8) (bbpc 14) (evb 5)
	  (cr0 0)   (cr1 1)   (cr2 2)   (cr3 3)
	  (cr4 4)   (cr5 5)   (cr6 6)   (cr7 7)
	  (cr8 8)   (cr9 9)   (cr10 10) (cr11 11)
	  (cr12 12) (cr13 13) (cr14 14) (cr15 15))
)

(define-hardware
  (name h-cr)
  (comment "control registers")
  (type register UWI (16))
  (indices extern-keyword cr-names)
  (get (index) (c-call UWI "@cpu@_h_cr_get_handler" index))
  (set (index newval) (c-call VOID "@cpu@_h_cr_set_handler" index newval))
)

; The actual accumulator is only 56 bits.
; The top 8 bits are sign extended from bit 8 (when counting msb = bit 0).
; To simplify the accumulator instructions, no attempt is made to keep the
; top 8 bits properly sign extended (currently there's no point since they
; all ignore them).  When the value is read it is properly sign extended
; [in the `get' handler].
(define-hardware
  (name h-accum)
  (comment "accumulator")
  (type register DI)
  (get () (c-call DI "@cpu@_h_accum_get_handler"))
  (set (newval) (c-call VOID "@cpu@_h_accum_set_handler" newval))
)

; FIXME: Revisit after sanitization can be removed.  Remove h-accum.
(define-hardware
  (name h-accums)
  (comment "accumulators")
  (attrs (MACH m32rx,m32r2))
  (type register DI (2))
  (indices keyword "" ((a0 0) (a1 1)))
  ; get/set so a0 accesses are redirected to h-accum.
  ; They're also so reads can properly sign extend the value.
  ; FIXME: Needn't be a function call.
  (get (index) (c-call DI "@cpu@_h_accums_get_handler" index))
  (set (index newval) (c-call VOID "@cpu@_h_accums_set_handler" index newval))
)

; For condbit operand.  FIXME: Need to allow spec of get/set of operands.
; Having this separate from h-psw keeps the parts that use it simpler
; [since they greatly outnumber those that use h-psw].
(dsh h-cond "condition bit" () (register BI))

; The actual values of psw,bpsw,bbpsw are recorded here to allow access
; to them as a unit.
(define-hardware
  (name h-psw)
  (comment "psw part of psw")
  (type register UQI)
  ; get/set to handle cond bit.
  ; FIXME: missing: use's and clobber's
  ; FIXME: remove c-call?
  (get () (c-call UQI "@cpu@_h_psw_get_handler"))
  (set (newval) (c-call VOID "@cpu@_h_psw_set_handler" newval))
)
(dsh h-bpsw  "backup psw"      () (register UQI))
(dsh h-bbpsw "backup bpsw"     () (register UQI))

; FIXME: Later make add get/set specs and support SMP.
(dsh h-lock  "lock"  () (register BI))

; Instruction Operands.
; These entries provide a layer between the assembler and the raw hardware
; description, and are used to refer to hardware elements in the semantic
; code.  Usually there's a bit of over-specification, but in more complicated
; instruction sets there isn't.

;; Print some operands take a hash prefix.
;; ??? Why don't we also handle one when parsing?

(define-pmacro (duhpo x-name x-comment x-attrs x-type x-index)
  (define-operand (name x-name) (comment x-comment)
    (.splice attrs (.unsplice x-attrs))
    (type x-type) (index x-index)
    (handlers (print "unsigned_with_hash_prefix")))
)

(define-pmacro (dshpo x-name x-comment x-attrs x-type x-index)
  (define-operand (name x-name) (comment x-comment)
    (.splice attrs (.unsplice x-attrs))
    (type x-type) (index x-index)
    (handlers (print "signed_with_hash_prefix")))
)

; ??? Convention says this should be o-sr, but then the insn definitions
; should refer to o-sr which is clumsy.  The "o-" could be implicit, but
; then it should be implicit for all the symbols here, but then there would
; be confusion between (f-)simm8 and (h-)simm8.
; So for now the rule is exactly as it appears here.

(dnop sr     "source register"              () h-gr   f-r2)
(dnop dr     "destination register"         () h-gr   f-r1)
;; The assembler relies upon the fact that dr and src1 are the same field.
;; FIXME: Revisit.
(dnop src1   "source register 1"            () h-gr   f-r1)
(dnop src2   "source register 2"            () h-gr   f-r2)
(dnop scr    "source control register"      () h-cr   f-r2)
(dnop dcr    "destination control register" () h-cr   f-r1)

(dshpo simm8  "8 bit signed immediate"       () h-sint f-simm8)
(dshpo simm16 "16 bit signed immediate"      () h-sint f-simm16)
(duhpo uimm3  "3 bit unsigned number"        () h-uint f-uimm3)
(duhpo uimm4  "4 bit trap number"            () h-uint f-uimm4)
(duhpo uimm5  "5 bit shift count"            () h-uint f-uimm5)
(duhpo uimm8  "8 bit unsigned immediate"     () h-uint f-uimm8)
(duhpo uimm16 "16 bit unsigned immediate"    () h-uint f-uimm16)

(duhpo imm1 "1 bit immediate" ((MACH m32rx,m32r2)) h-uint f-imm1)

(dnop accd   "accumulator destination register" ((MACH m32rx,m32r2)) h-accums f-accd)
(dnop accs   "accumulator source register"  ((MACH m32rx,m32r2))     h-accums f-accs)
(dnop acc    "accumulator reg (d)"          ((MACH m32rx,m32r2))     h-accums f-acc)

; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases.
; e.g. add3 r3,r3,#1 and ld r3,@(4,r4).  We could use special handlers on
; the operands themselves.
; Instead we create a fake operand `hash'.  The m32r is an illustration port,
; so we often try out various ways of doing things.

(define-operand (name hash) (comment "# prefix") (attrs)
  (type h-sint) ; doesn't really matter
  (index f-nil)
  (handlers (parse "hash") (print "hash"))
)

; For high(foo),shigh(foo).
(define-operand
  (name hi16)
  (comment "high 16 bit immediate, sign optional")
  (attrs)
  (type h-hi16)
  (index f-hi16)
  (handlers (parse "hi16"))
)

; For low(foo),sda(foo).
(define-operand
  (name slo16)
  (comment "16 bit signed immediate, for low()")
  (attrs)
  (type h-slo16)
  (index f-simm16)
  (handlers (parse "slo16"))
)

; For low(foo).
(define-operand
  (name ulo16)
  (comment "16 bit unsigned immediate, for low()")
  (attrs)
  (type h-ulo16)
  (index f-uimm16)
  (handlers (parse "ulo16"))
)

(dnop uimm24 "24 bit address" () h-addr f-uimm24)

(define-operand
  (name disp8)
  (comment "8 bit displacement")
  (attrs RELAX)
  (type h-iaddr)
  (index f-disp8)
  ; ??? Early experiments had insert/extract fields here.
  ; Moving these to f-disp8 made things cleaner, but may wish to re-introduce
  ; fields here to handle more complicated cases.
)

(dnop disp16 "16 bit displacement" () h-iaddr f-disp16)
(dnop disp24 "24 bit displacement" (RELAX) h-iaddr f-disp24)

; These hardware elements are refered to frequently.

(dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil)
(dnop accum "accumulator" (SEM-ONLY) h-accum f-nil)

; Instruction definitions.
;
; Notes while wip:
; - dni is a cover macro to the real "this is an instruction" keyword.
;   The syntax of the real one is yet to be determined.
;   At the lowest level (i.e. the "real" one) it will probably take a variable
;   list of arguments where each argument [perhaps after the standard three of
;   name, comment, attrs] is "(keyword arg-to-keyword)".  This syntax is simple
;   and yet completely upward extensible.  And given the macro facility, one
;   needn't code at that low a level so even though it'll be more verbose than
;   necessary it won't matter.  This same reasoning can be applied to most
;   types of entries in this file.

; M32R specific instruction attributes:

; FILL-SLOT: Need next insn to begin on 32 bit boundary.
; (A "slot" as used here is a 32 bit quantity that can either be filled with
; one 32 bit insn or two 16 bit insns which go in the "left bin" and "right
; bin" where the left bin is the one with a lower address).

(define-attr
  (for insn)
  (type boolean)
  (name FILL-SLOT)
  (comment "fill right bin with `nop' if insn is in left bin")
)

(define-attr
  (for insn)
  (type boolean)
  (name SPECIAL)
  (comment "non-public m32rx insn")
)

(define-attr
  (for insn)
  (type boolean)
  (name SPECIAL_M32R)
  (comment "non-public m32r insn")
)

(define-attr
  (for insn)
  (type boolean)
  (name SPECIAL_FLOAT)
  (comment "floating point insn")
)

; IDOC attribute for instruction documentation.

(define-attr
  (for insn)
  (type enum)
  (name IDOC)
  (comment "insn kind for documentation")
  (attrs META)
  (values
   (MEM - () "Memory")
   (ALU - () "ALU")
   (BR - () "Branch")
   (ACCUM - () "Accumulator")
   (MAC - () "Multiply/Accumulate")
   (MISC - () "Miscellaneous")
  )
)

(define-pmacro (bin-op mnemonic op2-op sem-op imm-prefix imm)
  (begin
     (dni mnemonic
	  (.str mnemonic " reg/reg")
	  ((PIPE OS) (IDOC ALU))
	  (.str mnemonic " $dr,$sr")
	  (+ OP1_0 op2-op dr sr)
	  (set dr (sem-op dr sr))
	  ()
     )
     (dni (.sym mnemonic "3")
	  (.str mnemonic " reg/" imm)
	  ((IDOC ALU))
	  (.str mnemonic "3 $dr,$sr," imm-prefix "$" imm)
	  (+ OP1_8 op2-op dr sr imm)
	  (set dr (sem-op sr imm))
	  ()
     )
   )
)
(bin-op add OP2_10 add "$hash" slo16)
; sub isn't present because sub3 doesn't exist.
(bin-op and OP2_12 and "" uimm16)
(bin-op or OP2_14 or "$hash" ulo16)
(bin-op xor OP2_13 xor "" uimm16)

(dni addi "addi"
     ((PIPE OS) (IDOC ALU))
     ;#.(string-append "addi " "$dr,$simm8") ; #. experiment
     "addi $dr,$simm8"
     (+ OP1_4 dr simm8)
     (set dr (add dr simm8))
     ((m32r/d (unit u-exec))
      (m32rx (unit u-exec))
      (m32r2 (unit u-exec)))
)

(dni addv "addv"
     ((PIPE OS) (IDOC ALU))
     "addv $dr,$sr"
     (+ OP1_0 OP2_8 dr sr)
     (parallel ()
	       (set dr (add dr sr))
	       (set condbit (add-oflag dr sr (const 0))))
     ()
)

(dni addv3 "addv3"
     ((IDOC ALU))
     "addv3 $dr,$sr,$simm16"
     (+ OP1_8 OP2_8 dr sr simm16)
     (parallel ()
	       (set dr (add sr simm16))
	       (set condbit (add-oflag sr simm16 (const 0))))
     ()
)

(dni addx "addx"
     ((PIPE OS) (IDOC ALU))
     "addx $dr,$sr"
     (+ OP1_0 OP2_9 dr sr)
     (parallel ()
	       (set dr (addc dr sr condbit))
	       (set condbit (add-cflag dr sr condbit)))
     ()
)

(dni bc8 "bc with 8 bit displacement"
     (COND-CTI (PIPE O) (IDOC BR))
     "bc.s $disp8"
     (+ OP1_7 (f-r1 12) disp8)
     (if condbit (set pc disp8))
     ((m32r/d (unit u-cti))
      (m32rx (unit u-cti))
      (m32r2 (unit u-cti)))
)

(dnmi bc8r "relaxable bc8"
     (COND-CTI RELAXABLE (PIPE O) (IDOC BR))
     "bc $disp8"
     (emit bc8 disp8)
)

(dni bc24 "bc with 24 bit displacement"
     (COND-CTI (IDOC BR))
     "bc.l $disp24"
     (+ OP1_15 (f-r1 12) disp24)
     (if condbit (set pc disp24))
     ((m32r/d (unit u-cti))
      (m32rx (unit u-cti))
      (m32r2 (unit u-cti)))
)

(dnmi bc24r "relaxable bc24"
     (COND-CTI RELAXED (IDOC BR))
     "bc $disp24"
     (emit bc24 disp24)
)

(dni beq "beq"
     (COND-CTI (IDOC BR))
     "beq $src1,$src2,$disp16"
     (+ OP1_11 OP2_0 src1 src2 disp16)
     (if (eq src1 src2) (set pc disp16))
     ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
      (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
      (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
)

(define-pmacro (cbranch sym comment op2-op comp-op)
  (dni sym comment (COND-CTI (IDOC BR))
	(.str sym " $src2,$disp16")
	(+ OP1_11 op2-op (f-r1 0) src2 disp16)
	(if (comp-op src2 (const WI 0)) (set pc disp16))
	((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
	 (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
	 (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
	)
)
(cbranch beqz "beqz" OP2_8 eq)
(cbranch bgez "bgez" OP2_11 ge)
(cbranch bgtz "bgtz" OP2_13 gt)
(cbranch blez "blez" OP2_12 le)
(cbranch bltz "bltz" OP2_10 lt)
(cbranch bnez "bnez" OP2_9 ne)

(dni bl8 "bl with 8 bit displacement"
     (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
     "bl.s $disp8"
     (+ OP1_7 (f-r1 14) disp8)
     (sequence ()
	       (set (reg h-gr 14)
		    (add (and pc (const -4)) (const 4)))
	       (set pc disp8))
     ((m32r/d (unit u-cti))
      (m32rx (unit u-cti))
      (m32r2 (unit u-cti)))
)

(dnmi bl8r "relaxable bl8"
     (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR))
     "bl $disp8"
     (emit bl8 disp8)
)

(dni bl24 "bl with 24 bit displacement"
     (UNCOND-CTI (IDOC BR))
     "bl.l $disp24"
     (+ OP1_15 (f-r1 14) disp24)
     (sequence ()
	       (set (reg h-gr 14) (add pc (const 4)))
	       (set pc disp24))
     ((m32r/d (unit u-cti))
      (m32rx (unit u-cti))
      (m32r2 (unit u-cti)))
)

(dnmi bl24r "relaxable bl24"
     (UNCOND-CTI RELAXED (IDOC BR))
     "bl $disp24"
     (emit bl24 disp24)
)

(dni bcl8 "bcl with 8 bit displacement"
     (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
     "bcl.s $disp8"
     (+ OP1_7 (f-r1 8) disp8)
     (if condbit
         (sequence ()
		   (set (reg h-gr 14)
			(add (and pc (const -4))
			     (const 4)))
		   (set pc disp8)))
     ((m32rx (unit u-cti))
      (m32r2 (unit u-cti)))
)

(dnmi bcl8r "relaxable bcl8"
     (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
     "bcl $disp8"
     (emit bcl8 disp8)
)

(dni bcl24 "bcl with 24 bit displacement"
     (COND-CTI (MACH m32rx,m32r2) (IDOC BR))
     "bcl.l $disp24"
     (+ OP1_15 (f-r1 8) disp24)
     (if condbit
         (sequence ()
		   (set (reg h-gr 14) (add pc (const 4)))
		   (set pc disp24)))
     ((m32rx (unit u-cti))
      (m32r2 (unit u-cti)))
)

(dnmi bcl24r "relaxable bcl24"
     (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
     "bcl $disp24"
     (emit bcl24 disp24)
)

(dni bnc8 "bnc with 8 bit displacement"
     (COND-CTI (PIPE O) (IDOC BR))
     "bnc.s $disp8"
     (+ OP1_7 (f-r1 13) disp8)
     (if (not condbit) (set pc disp8))
     ((m32r/d (unit u-cti))
      (m32rx (unit u-cti))
      (m32r2 (unit u-cti)))
)

(dnmi bnc8r "relaxable bnc8"
     (COND-CTI RELAXABLE (PIPE O) (IDOC BR))
     "bnc $disp8"
     (emit bnc8 disp8)
)

(dni bnc24 "bnc with 24 bit displacement"
     (COND-CTI (IDOC BR))
     "bnc.l $disp24"
     (+ OP1_15 (f-r1 13) disp24)
     (if (not condbit) (set pc disp24))
     ((m32r/d (unit u-cti))
      (m32rx (unit u-cti))
      (m32r2 (unit u-cti)))
)

(dnmi bnc24r "relaxable bnc24"
     (COND-CTI RELAXED (IDOC BR))
     "bnc $disp24"
     (emit bnc24 disp24)
)

(dni bne "bne"
     (COND-CTI (IDOC BR))
     "bne $src1,$src2,$disp16"
     (+ OP1_11 OP2_1 src1 src2 disp16)
     (if (ne src1 src2) (set pc disp16))
     ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
      (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
      (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
)

(dni bra8 "bra with 8 bit displacement"
     (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
     "bra.s $disp8"
     (+ OP1_7 (f-r1 15) disp8)
     (set pc disp8)
     ((m32r/d (unit u-cti))
      (m32rx (unit u-cti))
      (m32r2 (unit u-cti)))
)

(dnmi bra8r "relaxable bra8"
     (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR))
     "bra $disp8"
     (emit bra8 disp8)
)

(dni bra24 "bra with 24 displacement"
     (UNCOND-CTI (IDOC BR))
     "bra.l $disp24"
     (+ OP1_15 (f-r1 15) disp24)
     (set pc disp24)
     ((m32r/d (unit u-cti))
      (m32rx (unit u-cti))
      (m32r2 (unit u-cti)))
)

(dnmi bra24r "relaxable bra24"
     (UNCOND-CTI RELAXED (IDOC BR))
     "bra $disp24"
     (emit bra24 disp24)
)

(dni bncl8 "bncl with 8 bit displacement"
     (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
     "bncl.s $disp8"
     (+ OP1_7 (f-r1 9) disp8)
     (if (not condbit) 
         (sequence ()
		   (set (reg h-gr 14)
			(add (and pc (const -4))
			     (const 4)))
		   (set pc disp8)))
     ((m32rx (unit u-cti))
      (m32r2 (unit u-cti)))
)

(dnmi bncl8r "relaxable bncl8"
     (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
     "bncl $disp8"
     (emit bncl8 disp8)
)

(dni bncl24 "bncl with 24 bit displacement"
     (COND-CTI (MACH m32rx,m32r2) (IDOC BR))
     "bncl.l $disp24"
     (+ OP1_15 (f-r1 9) disp24)
     (if (not condbit)
         (sequence ()
		   (set (reg h-gr 14) (add pc (const 4)))
		   (set pc disp24)))
     ((m32rx (unit u-cti))
      (m32r2 (unit u-cti)))
)

(dnmi bncl24r "relaxable bncl24"
     (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
     "bncl $disp24"
     (emit bncl24 disp24)
)

(dni cmp "cmp"
     ((PIPE OS) (IDOC ALU))
     "cmp $src1,$src2"
     (+ OP1_0 OP2_4 src1 src2)
     (set condbit (lt src1 src2))
     ((m32r/d (unit u-cmp))
      (m32rx (unit u-cmp))
      (m32r2 (unit u-cmp)))
)

(dni cmpi "cmpi"
     ((IDOC ALU))
     "cmpi $src2,$simm16"
     (+ OP1_8 (f-r1 0) OP2_4 src2 simm16)
     (set condbit (lt src2 simm16))
     ((m32r/d (unit u-cmp))
      (m32rx (unit u-cmp))
      (m32r2 (unit u-cmp)))
)

(dni cmpu "cmpu"
     ((PIPE OS) (IDOC ALU))
     "cmpu $src1,$src2"
     (+ OP1_0 OP2_5 src1 src2)
     (set condbit (ltu src1 src2))
     ((m32r/d (unit u-cmp))
      (m32rx (unit u-cmp))
      (m32r2 (unit u-cmp)))
)

(dni cmpui "cmpui"
     ((IDOC ALU))
     "cmpui $src2,$simm16"
     (+ OP1_8 (f-r1 0) OP2_5 src2 simm16)
     (set condbit (ltu src2 simm16))
     ((m32r/d (unit u-cmp))
      (m32rx (unit u-cmp))
      (m32r2 (unit u-cmp)))
)

(dni cmpeq "cmpeq"
     ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
     "cmpeq $src1,$src2"
     (+ OP1_0 OP2_6 src1 src2)
     (set condbit (eq src1 src2))
     ((m32rx (unit u-cmp))
      (m32r2 (unit u-cmp)))
)

(dni cmpz "cmpz"
     ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
     "cmpz $src2"
     (+ OP1_0 OP2_7 (f-r1 0) src2)
     (set condbit (eq src2 (const 0)))
     ((m32rx (unit u-cmp))
      (m32r2 (unit u-cmp)))
)

(dni div "div"
     ((IDOC ALU))
     "div $dr,$sr"
     (+ OP1_9 OP2_0 dr sr (f-simm16 0))
     (if (ne sr (const 0)) (set dr (div dr sr)))
     ((m32r/d (unit u-exec (cycles 37)))
      (m32rx (unit u-exec (cycles 37)))
      (m32r2 (unit u-exec (cycles 37))))
)

(dni divu "divu"
     ((IDOC ALU))
     "divu $dr,$sr"
     (+ OP1_9 OP2_1 dr sr (f-simm16 0))
     (if (ne sr (const 0)) (set dr (udiv dr sr)))
     ((m32r/d (unit u-exec (cycles 37)))
      (m32rx (unit u-exec (cycles 37)))
      (m32r2 (unit u-exec (cycles 37))))
)

(dni rem "rem"
     ((IDOC ALU))
     "rem $dr,$sr"
     (+ OP1_9 OP2_2 dr sr (f-simm16 0))
     ; FIXME: Check rounding direction.
     (if (ne sr (const 0)) (set dr (mod dr sr)))
     ((m32r/d (unit u-exec (cycles 37)))
      (m32rx (unit u-exec (cycles 37)))
      (m32r2 (unit u-exec (cycles 37))))
)

(dni remu "remu"
     ((IDOC ALU))
     "remu $dr,$sr"
     (+ OP1_9 OP2_3 dr sr (f-simm16 0))
     ; FIXME: Check rounding direction.
     (if (ne sr (const 0)) (set dr (umod dr sr)))
     ((m32r/d (unit u-exec (cycles 37)))
      (m32rx (unit u-exec (cycles 37)))
      (m32r2 (unit u-exec (cycles 37))))
)

(dni remh "remh"
     ((MACH m32r2))
     "remh $dr,$sr"
     (+ OP1_9 OP2_2 dr sr (f-simm16 #x10))
     ; FIXME: Check rounding direction.
     (if (ne sr (const 0)) (set dr (mod (ext WI (trunc HI dr)) sr)))
     ((m32r2 (unit u-exec (cycles 21))))
)

(dni remuh "remuh"
     ((MACH m32r2))
     "remuh $dr,$sr"
     (+ OP1_9 OP2_3 dr sr (f-simm16 #x10))
     ; FIXME: Check rounding direction.
     (if (ne sr (const 0)) (set dr (umod dr sr)))
     ((m32r2 (unit u-exec (cycles 21))))
)

(dni remb "remb"
     ((MACH m32r2))
     "remb $dr,$sr"
     (+ OP1_9 OP2_2 dr sr (f-simm16 #x18))
     ; FIXME: Check rounding direction.
     (if (ne sr (const 0)) (set dr (mod (ext WI (trunc BI dr)) sr)))
     ((m32r2 (unit u-exec (cycles 21))))
)

(dni remub "remub"
     ((MACH m32r2))
     "remub $dr,$sr"
     (+ OP1_9 OP2_3 dr sr (f-simm16 #x18))
     ; FIXME: Check rounding direction.
     (if (ne sr (const 0)) (set dr (umod dr sr)))
     ((m32r2 (unit u-exec (cycles 21))))
)

(dni divuh "divuh"
     ((MACH m32r2))
     "divuh $dr,$sr"
     (+ OP1_9 OP2_1 dr sr (f-simm16 #x10))
     (if (ne sr (const 0)) (set dr (udiv dr sr)))
     ((m32r2 (unit u-exec (cycles 21))))
)

(dni divb "divb"
     ((MACH m32r2))
     "divb $dr,$sr"
     (+ OP1_9 OP2_0 dr sr (f-simm16 #x18))
     (if (ne sr (const 0)) (set dr (div (ext WI (trunc BI dr)) sr)))
     ((m32r2 (unit u-exec (cycles 21))))
)

(dni divub "divub"
     ((MACH m32r2))
     "divub $dr,$sr"
     (+ OP1_9 OP2_1 dr sr (f-simm16 #x18))
     (if (ne sr (const 0)) (set dr (udiv dr sr)))
     ((m32r2 (unit u-exec (cycles 21))))
)

(dni divh "divh"
     ((MACH m32rx,m32r2) (IDOC ALU))
     "divh $dr,$sr"
     (+ OP1_9 OP2_0 dr sr (f-simm16 #x10))
     (if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr)))
     ((m32rx (unit u-exec (cycles 21)))
      (m32r2 (unit u-exec (cycles 21))))
)

(dni jc "jc"
     (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
     "jc $sr"
     (+ OP1_1 (f-r1 12) OP2_12 sr)
     (if condbit (set pc (and sr (const -4))))
     ((m32rx (unit u-cti))
      (m32r2 (unit u-cti)))
)

(dni jnc "jnc"
     (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
     "jnc $sr"
     (+ OP1_1 (f-r1 13) OP2_12 sr)
     (if (not condbit) (set pc (and sr (const -4))))
     ((m32rx (unit u-cti))
      (m32r2 (unit u-cti)))
)

(dni jl "jl"
     (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
     "jl $sr"
     (+ OP1_1 (f-r1 14) OP2_12 sr)
     (parallel ()
	       (set (reg h-gr 14)
		    (add (and pc (const -4)) (const 4)))
	       (set pc (and sr (const -4))))
     ((m32r/d (unit u-cti))
      (m32rx (unit u-cti))
      (m32r2 (unit u-cti)))
)

(dni jmp "jmp"
     (UNCOND-CTI (PIPE O) (IDOC BR))
     "jmp $sr"
     (+ OP1_1 (f-r1 15) OP2_12 sr)
     (set pc (and sr (const -4)))
     ; The above works now so this kludge has been commented out.
     ; It's kept around because the f-r1 reference in the semantic part
     ; should work.
     ; FIXME: kludge, instruction decoding not finished.
     ; But this should work, so that's another FIXME.
     ;(sequence VOID (if VOID (eq SI f-r1 (const SI 14))
     ; FIXME: abuf->insn should be a macro of some sort.
     ;(sequence VOID
     ;	       (if VOID (eq SI (c-code SI "((abuf->insn >> 8) & 15)")
     ;			  (const SI 14))
     ;		   (set WI (reg WI h-gr 14)
     ;			(add WI (and WI pc (const WI -4)) (const WI 4))))
     ;	       (set WI pc sr))
     ((m32r/d (unit u-cti))
      (m32rx (unit u-cti))
      (m32r2 (unit u-cti)))
)

(define-pmacro (no-ext-expr mode expr) expr)
(define-pmacro (ext-expr mode expr) (ext mode expr))
(define-pmacro (zext-expr mode expr) (zext mode expr))

(define-pmacro (load-op suffix op2-op mode ext-op)
  (begin
    (dni (.sym ld suffix) (.str "ld" suffix)
	 ((PIPE O) (IDOC MEM))
	 (.str "ld" suffix " $dr,@$sr")
	 (+ OP1_2 op2-op dr sr)
	 (set dr (ext-op WI (mem mode sr)))
	 ((m32r/d (unit u-load))
	  (m32rx (unit u-load))
	  (m32r2 (unit u-load)))
	 )
    (dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2")
	  (NO-DIS (PIPE O) (IDOC MEM))
	  (.str "ld" suffix " $dr,@($sr)")
	  (emit (.sym ld suffix) dr sr))
    (dni (.sym ld suffix -d) (.str "ld" suffix "-d")
	 ((IDOC MEM))
	 (.str "ld" suffix " $dr,@($slo16,$sr)")
	 (+ OP1_10 op2-op dr sr slo16)
	 (set dr (ext-op WI (mem mode (add sr slo16))))
	 ((m32r/d (unit u-load (cycles 2)))
	  (m32rx (unit u-load (cycles 2)))
	  (m32r2 (unit u-load (cycles 2))))
	 )
    (dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2")
	  (NO-DIS (IDOC MEM))
	  (.str "ld" suffix " $dr,@($sr,$slo16)")
	  (emit (.sym ld suffix -d) dr sr slo16))
    )
)
(load-op "" OP2_12 WI no-ext-expr)
(load-op b OP2_8 QI ext-expr)
(load-op h OP2_10 HI ext-expr)
(load-op ub OP2_9 QI zext-expr)
(load-op uh OP2_11 HI zext-expr)

(dni ld-plus "ld+"
     ((PIPE O) (IDOC MEM))
     "ld $dr,@$sr+"
     (+ OP1_2 dr OP2_14 sr)
     (parallel ()
	       ; wip: memory addresses in profiling support
	       ;(set dr (name ld-mem (mem WI sr)))
	       (set dr (mem WI sr))
	       (set sr (add sr (const 4))))
     ; Note: `pred' is the constraint.  Also useful here is (ref name)
     ; and returns true if operand <name> was referenced
     ; (where "referenced" means _read_ if input operand and _written_ if
     ; output operand).
     ; args to unit are "unit-name (name1 value1) ..."
     ; - cycles(done),issue,pred are also specified this way
     ; - if unspecified, default is used
     ; - for ins/outs, extra arg is passed that says what was specified
     ;   - this is AND'd with `written' for outs
     ((m32r/d (unit u-load (pred (const 1)))
	      (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
      (m32rx (unit u-load)
	     (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
      (m32r2 (unit u-load)
	     (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
      )
)

(dnmi pop "pop"
      ((PIPE O) (IDOC MEM))
      "pop $dr"
      (emit ld-plus dr (sr 15)) ; "ld %0,@sp+"
)

(dni ld24 "ld24"
     ((IDOC MEM))
     "ld24 $dr,$uimm24"
     (+ OP1_14 dr uimm24)
     (set dr uimm24)
     ()
)

; ldi8 appears before ldi16 so we try the shorter version first

(dni ldi8 "ldi8"
     ((PIPE OS) (IDOC ALU))
     "ldi8 $dr,$simm8"
     (+ OP1_6 dr simm8)
     (set dr simm8)
     ()
)

(dnmi ldi8a "ldi8 alias"
     ((PIPE OS) (IDOC ALU))
     "ldi $dr,$simm8"
     (emit ldi8 dr simm8)
)

(dni ldi16 "ldi16"
     ((IDOC ALU))
     "ldi16 $dr,$hash$slo16"
     (+ OP1_9 OP2_15 (f-r2 0) dr slo16)
     (set dr slo16)
     ()
)

(dnmi ldi16a "ldi16 alias"
     ((IDOC ALU))
     "ldi $dr,$hash$slo16"
     (emit ldi16 dr slo16)
)

(dni lock "lock"
     ((PIPE O) (IDOC MISC))
     "lock $dr,@$sr"
     (+ OP1_2 OP2_13 dr sr)
     (sequence ()
	       (set (reg h-lock) (const BI 1))
	       (set dr (mem WI sr)))
     ((m32r/d (unit u-load))
      (m32rx (unit u-load))
      (m32r2 (unit u-load)))
)

(dni machi "machi"
     (
      ; (MACH m32r) is a temporary hack.  This insn collides with machi-a
      ; in the simulator so disable it for m32rx.
      (MACH m32r) (PIPE S) (IDOC MAC)
     )
     "machi $src1,$src2"
     (+ OP1_3 OP2_4 src1 src2)
     ; FIXME: TRACE_RESULT will print the wrong thing since we
     ; alter one of the arguments.
     (set accum
	  (sra DI
	       (sll DI
		    (add DI
			 accum
			 (mul DI
			      (ext DI (and WI src1 (const #xffff0000)))
			      (ext DI (trunc HI (sra WI src2 (const 16))))))
		    (const 8))
	       (const 8)))
     ((m32r/d (unit u-mac)))
)

(dni machi-a "machi-a"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
     "machi $src1,$src2,$acc"
     (+ OP1_3 src1 acc (f-op23 4) src2)
     (set acc
	  (sra DI
	       (sll DI
		    (add DI
			 acc
			 (mul DI
			      (ext DI (and WI src1 (const #xffff0000)))
			      (ext DI (trunc HI (sra WI src2 (const 16))))))
		    (const 8))
	       (const 8)))
     ((m32rx (unit u-mac))
      (m32r2 (unit u-mac)))
)

(dni maclo "maclo"
     ((MACH m32r) (PIPE S) (IDOC MAC))
     "maclo $src1,$src2"
     (+ OP1_3 OP2_5 src1 src2)
     (set accum
	  (sra DI
	       (sll DI
		    (add DI
			 accum
			 (mul DI
			      (ext DI (sll WI src1 (const 16)))
			      (ext DI (trunc HI src2))))
		    (const 8))
	       (const 8)))
     ((m32r/d (unit u-mac)))
)

(dni maclo-a "maclo-a"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
     "maclo $src1,$src2,$acc"
     (+ OP1_3 src1 acc (f-op23 5) src2)
     (set acc
	  (sra DI
	       (sll DI
		    (add DI
			 acc
			 (mul DI
			      (ext DI (sll WI src1 (const 16)))
			      (ext DI (trunc HI src2))))
		    (const 8))
	       (const 8)))
     ((m32rx (unit u-mac))
      (m32r2 (unit u-mac)))
)

(dni macwhi "macwhi"
     ((MACH m32r) (PIPE S) (IDOC MAC))
     "macwhi $src1,$src2"
     (+ OP1_3 OP2_6 src1 src2)
     (set accum
	  (sra DI
	       (sll DI
		    (add DI
			 accum
			 (mul DI
			      (ext DI src1)
			      (ext DI (trunc HI (sra WI src2 (const 16))))))
		    (const 8))
	       (const 8)))
     ((m32r/d (unit u-mac)))
)

(dni macwhi-a "macwhi-a"
     ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
     "macwhi $src1,$src2,$acc"
     (+ OP1_3 src1 acc (f-op23 6) src2)
     ; Note that this doesn't do the sign extension, which is correct.
     (set acc
	  (add acc
	       (mul (ext DI src1)
		    (ext DI (trunc HI (sra src2 (const 16)))))))
     ((m32rx (unit u-mac))
      (m32r2 (unit u-mac)))
)

(dni macwlo "macwlo"
     ((MACH m32r) (PIPE S) (IDOC MAC))
     "macwlo $src1,$src2"
     (+ OP1_3 OP2_7 src1 src2)
     (set accum
	  (sra DI
	       (sll DI
		    (add DI
			 accum
			 (mul DI
			      (ext DI src1)
			      (ext DI (trunc HI src2))))
		    (const 8))
	       (const 8)))
     ((m32r/d (unit u-mac)))
)

(dni macwlo-a "macwlo-a"
     ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
     "macwlo $src1,$src2,$acc"
     (+ OP1_3 src1 acc (f-op23 7) src2)
     ; Note that this doesn't do the sign extension, which is correct.
     (set acc
	  (add acc
	       (mul (ext DI src1)
		    (ext DI (trunc HI src2)))))
     ((m32rx (unit u-mac))
      (m32r2 (unit u-mac)))
)

(dni mul "mul"
     ((PIPE S) (IDOC ALU))
     "mul $dr,$sr"
     (+ OP1_1 OP2_6 dr sr)
     (set dr (mul dr sr))
     ((m32r/d (unit u-exec (cycles 4)))
      (m32rx (unit u-exec (cycles 4)))
      (m32r2 (unit u-exec (cycles 4))))
)

(dni mulhi "mulhi"
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
     "mulhi $src1,$src2"
     (+ OP1_3 OP2_0 src1 src2)
     (set accum
	  (sra DI
	       (sll DI
		    (mul DI
			 (ext DI (and WI src1 (const #xffff0000)))
			 (ext DI (trunc HI (sra WI src2 (const 16)))))
		    (const 16))
	       (const 16)))
     ((m32r/d (unit u-mac)))
)

(dni mulhi-a "mulhi-a"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
     "mulhi $src1,$src2,$acc"
     (+ OP1_3 (f-op23 0) src1 acc src2)
     (set acc
	  (sra DI
	       (sll DI
		    (mul DI
			 (ext DI (and WI src1 (const #xffff0000)))
			 (ext DI (trunc HI (sra WI src2 (const 16)))))
		    (const 16))
	       (const 16)))
     ((m32rx (unit u-mac))
      (m32r2 (unit u-mac)))
)

(dni mullo "mullo"
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
     "mullo $src1,$src2"
     (+ OP1_3 OP2_1 src1 src2)
     (set accum
	  (sra DI
	       (sll DI
		    (mul DI
			 (ext DI (sll WI src1 (const 16)))
			 (ext DI (trunc HI src2)))
		    (const 16))
	       (const 16)))
     ((m32r/d (unit u-mac)))
)

(dni mullo-a "mullo-a"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
     "mullo $src1,$src2,$acc"
     (+ OP1_3 src1 acc (f-op23 1) src2)
     (set acc
	  (sra DI
	       (sll DI
		    (mul DI
			 (ext DI (sll WI src1 (const 16)))
			 (ext DI (trunc HI src2)))
		    (const 16))
	       (const 16)))
     ((m32rx (unit u-mac))
      (m32r2 (unit u-mac)))
)

(dni mulwhi "mulwhi"
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
     "mulwhi $src1,$src2"
     (+ OP1_3 OP2_2 src1 src2)
     (set accum
	  (sra DI
	       (sll DI
		    (mul DI
			 (ext DI src1)
			 (ext DI (trunc HI (sra WI src2 (const 16)))))
		    (const 8))
	       (const 8)))
     ((m32r/d (unit u-mac)))
)

(dni mulwhi-a "mulwhi-a"
     ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
     "mulwhi $src1,$src2,$acc"
     (+ OP1_3 src1 acc (f-op23 2) src2)
     ; Note that this doesn't do the sign extension, which is correct.
     (set acc
	  (mul (ext DI src1)
	       (ext DI (trunc HI (sra src2 (const 16))))))
     ((m32rx (unit u-mac))
      (m32r2 (unit u-mac)))
)

(dni mulwlo "mulwlo"
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
     "mulwlo $src1,$src2"
     (+ OP1_3 OP2_3 src1 src2)
     (set accum
	  (sra DI
	       (sll DI
		    (mul DI
			 (ext DI src1)
			 (ext DI (trunc HI src2)))
		    (const 8))
	       (const 8)))
     ((m32r/d (unit u-mac)))
)

(dni mulwlo-a "mulwlo-a"
     ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
     "mulwlo $src1,$src2,$acc"
     (+ OP1_3 src1 acc (f-op23 3) src2)
     ; Note that this doesn't do the sign extension, which is correct.
     (set acc
	  (mul (ext DI src1)
	       (ext DI (trunc HI src2))))
     ((m32rx (unit u-mac))
      (m32r2 (unit u-mac)))
)

(dni mv "mv"
     ((PIPE OS) (IDOC ALU))
     "mv $dr,$sr"
     (+ OP1_1 OP2_8 dr sr)
     (set dr sr)
     ()
)

(dni mvfachi "mvfachi"
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
     "mvfachi $dr"
     (+ OP1_5 OP2_15 (f-r2 0) dr)
     (set dr (trunc WI (sra DI accum (const 32))))
     ((m32r/d (unit u-exec (cycles 2))))
)

(dni mvfachi-a "mvfachi-a"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
     "mvfachi $dr,$accs"
     (+ OP1_5 dr OP2_15 accs (f-op3 0))
     (set dr (trunc WI (sra DI accs (const 32))))
     ((m32rx (unit u-exec (cycles 2)))
      (m32r2 (unit u-exec (cycles 2))))
)

(dni mvfaclo "mvfaclo"
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
     "mvfaclo $dr"
     (+ OP1_5 OP2_15 (f-r2 1) dr)
     (set dr (trunc WI accum))
     ((m32r/d (unit u-exec (cycles 2))))
)

(dni mvfaclo-a "mvfaclo-a"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
     "mvfaclo $dr,$accs"
     (+ OP1_5 dr OP2_15 accs (f-op3 1))
     (set dr (trunc WI accs))
     ((m32rx (unit u-exec (cycles 2)))
      (m32r2 (unit u-exec (cycles 2))))
)

(dni mvfacmi "mvfacmi"
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
     "mvfacmi $dr"
     (+ OP1_5 OP2_15 (f-r2 2) dr)
     (set dr (trunc WI (sra DI accum (const 16))))
     ((m32r/d (unit u-exec (cycles 2))))
)

(dni mvfacmi-a "mvfacmi-a"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
     "mvfacmi $dr,$accs"
     (+ OP1_5 dr OP2_15 accs (f-op3 2))
     (set dr (trunc WI (sra DI accs (const 16))))
     ((m32rx (unit u-exec (cycles 2)))
      (m32r2 (unit u-exec (cycles 2))))
)

(dni mvfc "mvfc"
     ((PIPE O) (IDOC MISC))
     "mvfc $dr,$scr"
     (+ OP1_1 OP2_9 dr scr)
     (set dr scr)
     ()
)

(dni mvtachi "mvtachi"
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
     "mvtachi $src1"
     (+ OP1_5 OP2_7 (f-r2 0) src1)
     (set accum
	  (or DI
	      (and DI accum (const DI #xffffffff))
	      (sll DI (ext DI src1) (const 32))))
     ((m32r/d (unit u-exec (in sr src1))))
)

(dni mvtachi-a "mvtachi-a"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
     "mvtachi $src1,$accs"
     (+ OP1_5 src1 OP2_7 accs (f-op3 0))
     (set accs
	  (or DI
	      (and DI accs (const DI #xffffffff))
	      (sll DI (ext DI src1) (const 32))))
     ((m32rx (unit u-exec (in sr src1)))
      (m32r2 (unit u-exec (in sr src1))))
)

(dni mvtaclo "mvtaclo"
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
     "mvtaclo $src1"
     (+ OP1_5 OP2_7 (f-r2 1) src1)
     (set accum
	  (or DI
	      (and DI accum (const DI #xffffffff00000000))
	      (zext DI src1)))
     ((m32r/d (unit u-exec (in sr src1))))
)

(dni mvtaclo-a "mvtaclo-a"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
     "mvtaclo $src1,$accs"
     (+ OP1_5 src1 OP2_7 accs (f-op3 1))
     (set accs
	  (or DI
	      (and DI accs (const DI #xffffffff00000000))
	      (zext DI src1)))
     ((m32rx (unit u-exec (in sr src1)))
      (m32r2 (unit u-exec (in sr src1))))
)

(dni mvtc "mvtc"
     ((PIPE O) (IDOC MISC))
     "mvtc $sr,$dcr"
     (+ OP1_1 OP2_10 dcr sr)
     (set dcr sr)
     ()
)

(dni neg "neg"
     ((PIPE OS) (IDOC ALU))
     "neg $dr,$sr"
     (+ OP1_0 OP2_3 dr sr)
     (set dr (neg sr))
     ()
)

(dni nop "nop"
     ((PIPE OS) (IDOC MISC))
     "nop"
     (+ OP1_7 OP2_0 (f-r1 0) (f-r2 0))
     (c-code VOID "PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);\n")
     ; FIXME: quick hack: parallel nops don't contribute to cycle count.
     ; Other kinds of nops do however (which we currently ignore).
     ((m32r/d (unit u-exec (cycles 0)))
      (m32rx (unit u-exec (cycles 0)))
      (m32r2 (unit u-exec (cycles 0))))
)

(dni not "not"
     ((PIPE OS) (IDOC ALU))
     "not $dr,$sr"
     (+ OP1_0 OP2_11 dr sr)
     (set dr (inv sr))
     ()
)

(dni rac "rac"
     ((MACH m32r) (PIPE S) (IDOC MAC))
     "rac"
     (+ OP1_5 OP2_9 (f-r1 0) (f-r2 0))
     (sequence ((DI tmp1))
	       (set tmp1 (sll DI accum (const 1)))
	       (set tmp1 (add DI tmp1 (const DI #x8000)))
	       (set accum
		    (cond DI
			  ((gt tmp1 (const DI #x00007fffffff0000))
			   (const DI #x00007fffffff0000))
			  ((lt tmp1 (const DI #xffff800000000000))
			   (const DI #xffff800000000000))
			  (else (and tmp1 (const DI #xffffffffffff0000)))))
	       )
     ((m32r/d (unit u-mac)))
)

(dni rac-dsi "rac-dsi"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
     "rac $accd,$accs,$imm1"
     (+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1)
     (sequence ((DI tmp1))
	       (set tmp1 (sll accs imm1))
	       (set tmp1 (add tmp1 (const DI #x8000)))
	       (set accd
		    (cond DI
			  ((gt tmp1 (const DI #x00007fffffff0000))
			   (const DI #x00007fffffff0000))
			  ((lt tmp1 (const DI #xffff800000000000))
			   (const DI #xffff800000000000))
			  (else (and tmp1 (const DI #xffffffffffff0000)))))
	       )
     ((m32rx (unit u-mac))
      (m32r2 (unit u-mac)))
)

(dnmi rac-d "rac-d"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
     "rac $accd"
     (emit rac-dsi accd (f-accs 0) (f-imm1 0))
)

(dnmi rac-ds "rac-ds"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
     "rac $accd,$accs"
     (emit rac-dsi accd accs (f-imm1 0))
)


(dni rach "rach"
     ((MACH m32r) (PIPE S) (IDOC MAC))
     "rach"
     (+ OP1_5 OP2_8 (f-r1 0) (f-r2 0))
     (sequence ((DI tmp1))
	       ; Lop off top 8 bits.
	       ; The sign bit we want to use is bit 55 so the 64 bit value
	       ; isn't properly signed which we deal with in the if's below.
	       (set tmp1 (and accum (const DI #xffffffffffffff)))
	       (if (andif (ge tmp1 (const DI #x003fff80000000))
			  (le tmp1 (const DI #x7fffffffffffff)))
		   (set tmp1 (const DI #x003fff80000000))
		   ; else part
		   (if (andif (ge tmp1 (const DI #x80000000000000))
			      (le tmp1 (const DI #xffc00000000000)))
		       (set tmp1 (const DI #xffc00000000000))
		       (set tmp1 (and (add accum (const DI #x40000000))
				      (const DI #xffffffff80000000)))))
	       (set tmp1 (sll tmp1 (const 1)))
	       ; Sign extend top 8 bits.
	       (set accum
		    ; FIXME: 7?
		    (sra DI (sll DI tmp1 (const 7)) (const 7)))
	       )
     ((m32r/d (unit u-mac)))
)

(dni rach-dsi "rach-dsi"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
     "rach $accd,$accs,$imm1"
     (+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1)
     (sequence ((DI tmp1))
	       (set tmp1 (sll accs imm1))
	       (set tmp1 (add tmp1 (const DI #x80000000)))
	       (set accd
		    (cond DI
			  ((gt tmp1 (const DI #x00007fff00000000))
			   (const DI #x00007fff00000000))
			  ((lt tmp1 (const DI #xffff800000000000))
			   (const DI #xffff800000000000))
			  (else (and tmp1 (const DI #xffffffff00000000)))))
	       )
     ((m32rx (unit u-mac))
      (m32r2 (unit u-mac)))
)

(dnmi rach-d "rach-d"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
     "rach $accd"
     (emit rach-dsi accd (f-accs 0) (f-imm1 0))
)

(dnmi rach-ds "rach-ds"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
     "rach $accd,$accs"
     (emit rach-dsi accd accs (f-imm1 0))
)

(dni rte "rte"
     (UNCOND-CTI (PIPE O) (IDOC BR))
     "rte"
     (+ OP1_1 OP2_13 (f-r1 0) (f-r2 6))
     (sequence ()
	       ; pc = bpc & -4
	       (set pc (and (reg h-cr 6) (const -4)))
	       ; bpc = bbpc
	       (set (reg h-cr 6) (reg h-cr 14))
	       ; psw = bpsw
	       (set (reg h-psw) (reg h-bpsw))
	       ; bpsw = bbpsw
	       (set (reg h-bpsw) (reg h-bbpsw))
     )
     ()
)

(dni seth "seth"
     ((IDOC ALU))
     "seth $dr,$hash$hi16"
     (+ OP1_13 OP2_12 dr (f-r2 0) hi16)
     (set dr (sll WI hi16 (const 16)))
     ()
)

(define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op)
  (begin
     (dni sym sym ((PIPE O_OS) (IDOC ALU))
	  (.str sym " $dr,$sr")
	  (+ OP1_1 op2-r-op dr sr)
	  (set dr (sem-op dr (and sr (const 31))))
	  ()
     )
     (dni (.sym sym "3") sym ((IDOC ALU))
	  (.str sym "3 $dr,$sr,$simm16")
	  (+ OP1_9 op2-3-op dr sr simm16)
	  (set dr (sem-op sr (and WI simm16 (const 31))))
	  ()
     )
     (dni (.sym sym "i") sym ((PIPE O_OS) (IDOC ALU))
	  (.str sym "i $dr,$uimm5")
	  (+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5)
	  (set dr (sem-op dr uimm5))
	  ()
     )
   )
)
(shift-op sll OP2_4 OP2_12 2 sll)
(shift-op sra OP2_2 OP2_10 1 sra)
(shift-op srl OP2_0 OP2_8 0 srl)

(define-pmacro (store-op suffix op2-op mode)
  (begin
    (dni (.sym st suffix) (.str "st" suffix)
	 ((PIPE O) (IDOC MEM))
	 (.str "st" suffix " $src1,@$src2")
	 (+ OP1_2 op2-op src1 src2)
	 (set mode (mem mode src2) src1)
	 ((m32r/d (unit u-store (cycles 1)))
	  (m32rx (unit u-store (cycles 1)))
	  (m32r2 (unit u-store (cycles 1))))
	 )
    (dnmi (.sym st suffix "-2") (.str "st" suffix "-2")
	  (NO-DIS (PIPE O) (IDOC MEM))
	  (.str "st" suffix " $src1,@($src2)")
	  (emit (.sym st suffix) src1 src2))
    (dni (.sym st suffix -d) (.str "st" suffix "-d")
	 ((IDOC MEM))
	 (.str "st" suffix " $src1,@($slo16,$src2)")
	 (+ OP1_10 op2-op src1 src2 slo16)
	 (set mode (mem mode (add src2 slo16)) src1)
	 ((m32r/d (unit u-store (cycles 2)))
	  (m32rx (unit u-store (cycles 2)))
	  (m32r2 (unit u-store (cycles 2))))
	 )
    (dnmi (.sym st suffix -d2) (.str "st" suffix "-d2")
	  (NO-DIS (IDOC MEM))
	  (.str "st" suffix " $src1,@($src2,$slo16)")
	  (emit (.sym st suffix -d) src1 src2 slo16))
    )
)
(store-op "" OP2_4 WI)
(store-op b OP2_0 QI)
(store-op h OP2_2 HI)

(dni st-plus "st+"
     ((PIPE O) (IDOC MEM))
     "st $src1,@+$src2"
     (+ OP1_2 OP2_6 src1 src2)
     ; This has to be coded carefully to avoid an "earlyclobber" of src2.
     (sequence ((WI new-src2))
	       (set new-src2 (add WI src2 (const WI 4)))
	       (set (mem WI new-src2) src1)
	       (set src2 new-src2))
     ((m32r/d (unit u-store)
	      (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
      (m32rx (unit u-store)
	     (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
      (m32r2 (unit u-store)
	     (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
      )
)

(dni sth-plus "sth+"
     ((MACH m32rx,m32r2) (PIPE O) SPECIAL)
     "sth $src1,@$src2+"
     (+ OP1_2 OP2_3 src1 src2)
     ; This has to be coded carefully to avoid an "earlyclobber" of src2.
     (sequence ((WI new-src2))
	       (set new-src2 src2)
	       (set (mem HI new-src2) src1)
	       (set src2 (add new-src2 (const 2))))
     ((m32rx (unit u-store)
           (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
      (m32r2 (unit u-store)
           (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
      )
)

(dni stb-plus "stb+"
     ((MACH m32rx,m32r2) (PIPE O) SPECIAL)
     "stb $src1,@$src2+"
     (+ OP1_2 OP2_1 src1 src2)
     ; This has to be coded carefully to avoid an "earlyclobber" of src2.
     (sequence ((WI new-src2))
	       (set new-src2 src2)
	       (set (mem QI new-src2) src1)
	       (set src2 (add new-src2 (const 1))))
     ((m32rx (unit u-store)
           (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
      (m32r2 (unit u-store)
           (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
      )
)

(dni st-minus "st-"
     ((PIPE O) (IDOC MEM))
     "st $src1,@-$src2"
     (+ OP1_2 OP2_7 src1 src2)
     ; This is the original way.  It doesn't work for parallel execution
     ; because of the earlyclobber of src2.
     ;(sequence ()
     ;	       (set src2 (sub src2 (const 4)))
     ;	       (set (mem WI src2) src1))
     (sequence ((WI new-src2))
	       (set new-src2 (sub src2 (const 4)))
	       (set (mem WI new-src2) src1)
	       (set src2 new-src2))
     ((m32r/d (unit u-store)
	      (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
      (m32rx (unit u-store)
	     (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
      (m32r2 (unit u-store)
	     (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
      )
)

(dnmi push "push" ((PIPE O) (IDOC MEM))
  "push $src1"
  (emit st-minus src1 (src2 15)) ; "st %0,@-sp"
)

(dni sub "sub"
     ((PIPE OS) (IDOC ALU))
     "sub $dr,$sr"
     (+ OP1_0 OP2_2 dr sr)
     (set dr (sub dr sr))
     ()
)

(dni subv "sub:rv"
     ((PIPE OS) (IDOC ALU))
     "subv $dr,$sr"
     (+ OP1_0 OP2_0 dr sr)
     (parallel ()
	       (set dr (sub dr sr))
	       (set condbit (sub-oflag dr sr (const 0))))
     ()
)

(dni subx "sub:rx"
     ((PIPE OS) (IDOC ALU))
     "subx $dr,$sr"
     (+ OP1_0 OP2_1 dr sr)
     (parallel ()
	       (set dr (subc dr sr condbit))
	       (set condbit (sub-cflag dr sr condbit)))
     ()
)

(dni trap "trap"
     (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC MISC))
     "trap $uimm4"
     (+ OP1_1 OP2_15 (f-r1 0) uimm4)
     (sequence ()
	       ; bbpc = bpc
	       (set (reg h-cr 14) (reg h-cr 6))
	       ; Set bpc to the return address.  Actually it's not quite the
	       ; return address as RTE rounds the address down to a word
	       ; boundary.
	       (set (reg h-cr 6) (add pc (const 4)))
	       ; bbpsw = bpsw
	       (set (reg h-bbpsw) (reg h-bpsw))
	       ; bpsw = psw
	       (set (reg h-bpsw) (reg h-psw))
	       ; sm is unchanged, ie,c are set to zero.
	       (set (reg h-psw) (and (reg h-psw) (const #x80)))
	       ; m32r_trap handles operating vs user mode
	       (set WI pc (c-call WI "m32r_trap" pc uimm4))
     )
     ()
)

(dni unlock "unlock"
     ((PIPE O) (IDOC MISC))
     "unlock $src1,@$src2"
     (+ OP1_2 OP2_5 src1 src2)
     (sequence ()
	       (if (reg h-lock)
		   (set (mem WI src2) src1))
	       (set (reg h-lock) (const BI 0)))
     ((m32r/d (unit u-load))
      (m32rx (unit u-load))
      (m32r2 (unit u-load)))
)

; Saturate into byte.
(dni satb "satb"
     ((MACH m32rx,m32r2) (IDOC ALU))
     "satb $dr,$sr"
     (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300))
     (set dr
	  ; FIXME: min/max would simplify this nicely of course.
	  (cond WI
		((ge sr (const 127)) (const 127))
		((le sr (const -128)) (const -128))
		(else sr)))
     ()
)

; Saturate into half word.
(dni sath "sath"
     ((MACH m32rx,m32r2) (IDOC ALU))
     "sath $dr,$sr"
     (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200))
     (set dr
	  (cond WI
		((ge sr (const 32767)) (const 32767))
		((le sr (const -32768)) (const -32768))
		(else sr)))
     ()
)

; Saturate word.
(dni sat "sat"
     ((MACH m32rx,m32r2) SPECIAL (IDOC ALU))
     "sat $dr,$sr"
     (+ OP1_8 dr OP2_6 sr (f-uimm16 0))
     (set dr
	  (if WI condbit
	       (if WI (lt sr (const 0))
		    (const #x7fffffff)
		    (const #x80000000))
	       sr))
     ()
)

; Parallel compare byte zeros.
; Set C bit in condition register if any byte in source register is zero.
(dni pcmpbz "pcmpbz"
     ((MACH m32rx,m32r2) (PIPE OS) SPECIAL (IDOC ALU))
     "pcmpbz $src2"
     (+ OP1_0 (f-r1 3) OP2_7 src2)
     (set condbit
	  (cond BI
		 ((eq (and src2 (const #xff)) (const 0)) (const BI 1))
		 ((eq (and src2 (const #xff00)) (const 0)) (const BI 1))
		 ((eq (and src2 (const #xff0000)) (const 0)) (const BI 1))
		 ((eq (and src2 (const #xff000000)) (const 0)) (const BI 1))
		 (else (const BI 0))))
     ((m32rx (unit u-cmp))
      (m32r2 (unit u-cmp)))
)

; Add accumulators
(dni sadd "sadd"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
     "sadd"
     (+ OP1_5 (f-r1 0) OP2_14 (f-r2 4))
     (set (reg h-accums 0)
	  (add (sra (reg h-accums 1) (const 16))
	       (reg h-accums 0)))
     ((m32rx (unit u-mac))
      (m32r2 (unit u-mac)))
)

; Multiply and add into accumulator 1
(dni macwu1 "macwu1"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
     "macwu1 $src1,$src2"
     (+ OP1_5 src1 OP2_11 src2)
     (set (reg h-accums 1)
	  (sra DI
		(sll DI
		      (add DI
			    (reg h-accums 1)
			    (mul DI
				  (ext DI src1)
				  (ext DI (and src2 (const #xffff)))))
		      (const 8))
		(const 8)))
     ((m32rx (unit u-mac))
      (m32r2 (unit u-mac)))
)

; Multiply and subtract from accumulator 0
(dni msblo "msblo"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
     "msblo $src1,$src2"
     (+ OP1_5 src1 OP2_13 src2)
     (set accum
	  (sra DI
		(sll DI
		      (sub accum
			   (sra DI
				 (sll DI
				       (mul DI
					     (ext DI (trunc HI src1))
					     (ext DI (trunc HI src2)))
				       (const 32))
				 (const 16)))
		      (const 8))
		(const 8)))
     ((m32rx (unit u-mac))
      (m32r2 (unit u-mac)))
)

; Multiply into accumulator 1
(dni mulwu1 "mulwu1"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
     "mulwu1 $src1,$src2"
     (+ OP1_5 src1 OP2_10 src2)
     (set (reg h-accums 1)
	  (sra DI
		(sll DI
		      (mul DI
			    (ext DI src1)
			    (ext DI (and src2 (const #xffff))))
		      (const 16))
		(const 16)))
     ((m32rx (unit u-mac))
      (m32r2 (unit u-mac)))
)

; Multiply and add into accumulator 1
(dni maclh1 "maclh1"
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
     "maclh1 $src1,$src2"
     (+ OP1_5 src1 OP2_12 src2)
     (set (reg h-accums 1)
	  (sra DI
		(sll DI
		    (add DI
			  (reg h-accums 1)
			  (sll DI
				(ext DI
				      (mul SI
					    (ext SI (trunc HI src1))
					    (sra SI src2 (const SI 16))))
			      (const 16)))
		    (const 8))
	       (const 8)))
     ((m32rx (unit u-mac))
      (m32r2 (unit u-mac)))
)

; skip instruction if C
(dni sc "sc"
     ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
     "sc"
     (+ OP1_7 (f-r1 4) OP2_0 (f-r2 1))
     (skip (zext INT condbit))
     ()
)

; skip instruction if not C
(dni snc "snc"
     ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
     "snc"
     (+ OP1_7 (f-r1 5) OP2_0 (f-r2 1))
     (skip (zext INT (not condbit)))
     ()
)

; PSW &= ((~ uimm8) | 0xff00)
(dni clrpsw "clrpsw"
     ((PIPE O) SPECIAL_M32R)
     "clrpsw $uimm8"
     (+ OP1_7 (f-r1 2) uimm8)
     (set USI (reg h-cr 0)
              (and USI (reg h-cr 0)
		   (or USI (zext SI (inv QI uimm8)) (const #xff00))))
     ()
)

; PSW |= (unsigned char) uimm8
(dni setpsw "setpsw"
     ((PIPE O) SPECIAL_M32R)
     "setpsw $uimm8"
     (+ OP1_7 (f-r1 1) uimm8)
     (set USI (reg h-cr 0) uimm8)
     ()
)

; bset
(dni bset "bset"
     (SPECIAL_M32R)
     "bset $uimm3,@($slo16,$sr)"
     (+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16)
     (set QI (mem QI (add sr slo16))
             (or QI (mem QI (add sr slo16))
		 (sll QI (const 1) (sub (const 7) uimm3))))
     ()
)

; bclr
(dni bclr "bclr"
     (SPECIAL_M32R)
     "bclr $uimm3,@($slo16,$sr)"
     (+ OP1_10 (f-bit4 0) uimm3  OP2_7 sr slo16)
     (set QI (mem QI (add sr slo16))
             (and QI (mem QI (add sr slo16))
                   (inv QI (sll QI (const 1) (sub (const 7) uimm3)))))
     ()
)

; btst
(dni btst "btst"
     (SPECIAL_M32R (PIPE O))
     "btst $uimm3,$sr"
     (+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr)
     (set condbit (and QI (srl QI sr (sub (const 7) uimm3)) (const 1)))
     ()
)