File: test_verilog.sch

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file content (222 lines) | stat: -rw-r--r-- 3,942 bytes parent folder | download | duplicates (11)
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v 20031011 1
C 9600 13100 0 0 0 title-B.sym
T 20400 14100 3 10 1 0 0 0 1
EXAMPLE SCHEMATIC FOR VERILOG NETLISTING
T 24200 13200 3 10 1 0 0 0 1
MIKE JARABEK
C 14300 20100 1 0 0 test_verilog.sym
{
T 15300 21100 5 10 1 1 0 0 1
refdes=TEST1
}
C 18100 19100 1 0 0 block-1.sym
{
T 19700 21000 5 10 1 1 0 0 1
refdes=U1
}
C 18100 16500 1 0 0 block-1.sym
{
T 19700 18400 5 10 1 1 0 0 1
refdes=U2
}
C 14300 18900 1 0 0 test_verilog.sym
{
T 15300 19900 5 10 1 1 0 0 1
refdes=TEST2
}
C 21700 19700 1 0 0 test_verilog.sym
{
T 23000 20700 5 10 1 1 0 0 1
refdes=U3
}
C 10500 21700 1 0 0 ipad-1.sym
{
T 10200 21800 5 10 1 1 0 0 1
refdes=P1
}
C 10500 21300 1 0 0 ipad-1.sym
{
T 10200 21300 5 10 1 1 0 0 1
refdes=P2
}
C 10500 15200 1 0 0 ipad-1.sym
{
T 10200 15200 5 10 1 1 0 0 1
refdes=P5
T 25600 20300 5 10 1 1 0 0 1
refdes=P6
}
C 25400 17300 1 0 1 iopad-1.sym
{
T 25500 17400 5 10 1 1 0 0 1
refdes=P9
}
C 25400 17600 1 0 1 iopad-1.sym
{
T 25500 17700 5 10 1 1 0 0 1
refdes=P8
}
C 24600 20200 1 0 0 opad-1.sym
{
T 25600 20300 5 10 1 1 0 0 1
refdes=P6
}
C 24600 19400 1 0 0 opad-1.sym
{
T 25600 19500 5 10 1 1 0 0 1
refdes=P7
}
C 10500 15900 1 0 0 ipad-1.sym
{
T 10200 16000 5 10 1 1 0 0 1
refdes=P4
}
N 23500 20300 24600 20300 4
{
T 24300 20400 5 10 1 1 0 0 1
netname=OUT1
}
N 20200 20300 21700 20300 4
N 20200 20000 21200 20000 4
N 21200 20000 21200 19500 4
N 21200 19500 24600 19500 4
{
T 24200 19600 5 10 1 1 0 0 1
netname=OUT2
}
N 20200 17700 24400 17700 4
{
T 23900 17800 5 10 1 1 0 0 1
netname=INOUT1
}
N 20200 17400 24400 17400 4
{
T 23900 17500 5 10 1 1 0 0 1
netname=INOUT2
}
C 10500 20800 1 0 0 ipad-1.sym
{
T 10200 20900 5 10 1 1 0 0 1
refdes=P3
}
N 18100 20600 17600 20600 4
N 17600 20600 17600 21800 4
N 17600 21800 11400 21800 4
{
T 11500 21900 5 10 1 1 0 0 1
netname=IN1
}
N 16100 20700 17000 20700 4
N 17000 20700 17000 20300 4
N 17000 20300 18100 20300 4
N 18100 20000 17000 20000 4
N 17000 20000 17000 19500 4
N 17000 19500 16100 19500 4
N 18100 19700 17600 19700 4
{
T 17100 19600 5 10 1 1 0 0 1
netname=REF1
}
N 11400 21400 13400 21400 4
{
T 11500 21400 5 10 1 1 0 0 1
netname=IN2
}
N 13400 21400 13400 20700 4
N 13400 20700 14300 20700 4
N 11400 20900 12900 20900 4
{
T 11500 21000 5 10 1 1 0 0 1
netname=IN3
}
N 12900 20900 12900 19500 4
N 12900 19500 14300 19500 4
N 18100 18000 13700 18000 4
N 13700 18000 13700 20700 4
N 18100 17700 16800 17700 4
N 16800 17700 16800 19500 4
{
T 16900 18800 5 10 1 1 0 0 1
netname=MIDDLE
}
N 11400 16000 12200 16000 4
{
T 12300 16000 5 10 1 1 0 0 1
netname=REF1
}
N 11400 15300 12200 15300 4
{
T 12300 15300 5 10 1 1 0 0 1
netname=REF2
}
N 18100 17400 17400 17400 4
{
T 16900 17400 5 10 1 1 0 0 1
netname=REF1
}
N 18100 17100 17400 17100 4
{
T 16800 17100 5 10 1 1 0 0 1
netname=REF2
}
T 16500 23300 3 10 1 0 0 0 1
Unnamed Nets
L 16900 20900 17200 23200 3 0 0 0 -1 -1
L 16800 21100 16900 20900 3 0 0 0 -1 -1
L 16900 20900 17100 21100 3 0 0 0 -1 -1
L 17600 23100 20900 20500 3 0 0 0 -1 -1
L 20900 20500 20900 20600 3 0 0 0 -1 -1
L 20900 20500 20800 20500 3 0 0 0 -1 -1
C 15300 15400 1 0 0 low-1.sym
{
T 15600 15600 5 10 1 1 0 0 1
refdes=PWR0
}
C 15400 16400 1 0 0 high-1.sym
{
T 15600 16700 5 10 1 1 0 0 1
refdes=PWR1
}
N 15500 16400 15500 15700 4
{
T 15600 16000 5 10 1 1 0 0 1
netname=MUNGLE_NET
}
C 21600 21500 1 0 0 block-1.sym
{
T 21900 21600 5 10 1 1 0 0 1
refdes=NO_CONNECTIONS
}
C 21700 14700 1 0 0 block_pos-1.sym
{
T 22000 14800 5 10 1 1 0 0 1
refdes=BLOCK_POS
}
N 20900 17700 20900 15900 4
N 20900 15900 21700 15900 4
N 21700 16200 21100 16200 4
N 21100 16200 21100 17400 4
N 20800 20000 20800 15600 4
N 20800 15600 21700 15600 4
N 23800 15900 24500 15900 4
{
T 25500 15800 5 10 1 1 0 0 1
netname=POS_OUT1
}
N 23800 15600 24500 15600 4
{
T 25500 15500 5 10 1 1 0 0 1
netname=POS_OUT2
}
C 24500 15800 1 0 0 opad-1.sym
{
T 24400 16000 5 10 1 1 0 0 1
refdes=P10
}
C 24500 15500 1 0 0 opad-1.sym
{
T 24400 15700 5 10 1 1 0 0 1
refdes=P11
}
T 19100 14600 5 10 1 0 0 0 1
module_name=VERILOG_TEST