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-- This is an implementation of -*- vhdl -*- ieee.std_logic_1164 based only
-- on the specifications. This file is part of GHDL.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
-- This is a template file. To avoid errors and duplication, the python
-- script build.py generate most of the bodies.
package body std_logic_1164 is
type table_1d is array (std_ulogic) of std_ulogic;
type table_2d is array (std_ulogic, std_ulogic) of std_ulogic;
constant resolution : table_2d :=
-- UX01ZWLH-
("UUUUUUUUU", -- U
"UXXXXXXXX", -- X
"UX0X0000X", -- 0
"UXX11111X", -- 1
"UX01ZWLHX", -- Z
"UX01WWWWX", -- W
"UX01LWLWX", -- L
"UX01HWWHX", -- H
"UXXXXXXXX" -- -
);
function resolved (s : std_ulogic_vector) return std_ulogic
is
variable res : std_ulogic := 'Z';
begin
for I in s'range loop
res := resolution (res, s (I));
end loop;
return res;
end resolved;
@TAB
@LOG
-- Conversion functions.
-- The result range (for vectors) is S'Length - 1 downto 0.
-- XMAP is return for values not in '0', '1', 'L', 'H'.
function to_bit (s : std_ulogic; xmap : bit := '0') return bit is
begin
case s is
when '0' | 'L' =>
return '0';
when '1' | 'H' =>
return '1';
when others =>
return xmap;
end case;
end to_bit;
type bit_to_std_table is array (bit) of std_ulogic;
constant bit_to_std : bit_to_std_table := "01";
@CONV
function to_stdulogic (b : bit) return std_ulogic is
begin
return bit_to_std (b);
end to_stdulogic;
-- Normalization.
type table_std_x01 is array (std_ulogic) of X01;
constant std_to_x01 : table_std_x01 := ('U' | 'X' | 'Z' | 'W' | '-' => 'X',
'0' | 'L' => '0',
'1' | 'H' => '1');
type table_bit_x01 is array (bit) of X01;
constant bit_to_x01 : table_bit_x01 := ('0' => '0',
'1' => '1');
type table_std_x01z is array (std_ulogic) of X01Z;
constant std_to_x01z : table_std_x01z := ('U' | 'X' | 'W' | '-' => 'X',
'0' | 'L' => '0',
'1' | 'H' => '1',
'Z' => 'Z');
type table_std_ux01 is array (std_ulogic) of UX01;
constant std_to_ux01 : table_std_ux01 := ('U' => 'U',
'X' | 'Z' | 'W' | '-' => 'X',
'0' | 'L' => '0',
'1' | 'H' => '1');
@NORM
function rising_edge (signal s : std_ulogic) return boolean is
begin
return s'event
and to_x01 (s'last_value) = '0'
and to_x01 (s) = '1';
end rising_edge;
function falling_edge (signal s : std_ulogic) return boolean is
begin
return s'event
and to_x01 (s'last_value) = '1'
and to_x01 (s) = '0';
end falling_edge;
type std_x_array is array (std_ulogic) of boolean;
constant std_x : std_x_array := ('U' | 'X' | 'Z' | 'W' | '-' => true,
'0' | '1' | 'L' | 'H' => false);
@ISX
end std_logic_1164;
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