File: simple-enumeration-assign.vhdl

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entity foo is
end foo;

use std.textio.all;

architecture only of foo is
begin  -- only
  process
    variable x : boolean := false;
  begin  -- process
    x := true;
    assert x = true report "TEST FAILED - x does not equal true" severity failure;
    assert x /= true report "TEST PASSED" severity note;
    wait;
  end process;
end only;